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library/common/ad_dds: Fix initialization when 'valid' not constant 

If dac_valid is not a constant '1' it gets synchronized with the
dac_data_sync signal. This causes that dac_valid never asserts while
dac_data_sync is high, this way skipping the phase initialization.
main
Laszlo Nagy 2020-08-25 14:38:57 +01:00 committed by Laszlo Nagy
parent eb2f211d30
commit 5d803d6b6e
1 changed files with 1 additions and 3 deletions
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4
library/common/ad_dds.v
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@ -118,7 +118,6 @@ module ad_dds #(
// phase accumulator // phase accumulator
for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase
always @(posedge clk) begin always @(posedge clk) begin
if (dac_valid == 1'b1) begin
if (dac_data_sync == 1'b1) begin if (dac_data_sync == 1'b1) begin
dac_dds_phase_0[i] <= 'd0; dac_dds_phase_0[i] <= 'd0;
dac_dds_phase_1[i] <= 'd0; dac_dds_phase_1[i] <= 'd0;
@ -130,11 +129,10 @@ module ad_dds #(
dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word; dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word;
dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word; dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word;
end end
end else begin end else if (dac_valid == 1'b1) begin
dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0; dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0;
dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1; dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1;
end end
end
end end
// phase to amplitude convertor // phase to amplitude convertor