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axi_dmac: Allow wider FIFO/AXI Stream interface 

On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.

This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
main
Laszlo Nagy 2021-02-19 08:11:34 +00:00 committed by Laszlo Nagy
parent 63b6711cfa
commit 5dd9fd4832
1 changed files with 2 additions and 1 deletions
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3
library/axi_dmac/axi_dmac_ip.tcl
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@ -258,7 +258,7 @@ set_property -dict [list \
foreach dir {"SRC" "DEST"} {
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" "16 32 64 128 256 512 1024" \
"value_validation_list" "16 32 64 128 256 512 1024 2048" \
] \
[ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc]
@ -308,6 +308,7 @@ foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] {
ipgui::move_param -component $cc -order 2 $p -parent $group
set_property -dict [list \
"display_name" "Bus Width" \
"tooltip" "Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits" \
] $p
set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc]