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daq2/a10gx- xcvr sharing

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Rejeesh Kutty 2016-09-12 14:50:54 -04:00
parent c6998dd396
commit 5df30ac6b0
3 changed files with 28 additions and 12 deletions
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12
projects/daq2/a10gx/system_constr.sdc
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@ -19,25 +19,25 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]

10
projects/daq2/a10gx/system_project.tcl
View File

@ -60,6 +60,16 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
# gpio
set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P

18
projects/daq2/a10gx/system_top.v
View File

@ -238,10 +238,13 @@ module system_top (
assign gpio_bd_o = gpio_o[15:0];
system_bd i_system_bd (
.rx_data_rx_serial_data (rx_data),
.rx_data_0_rx_serial_data (rx_data[0]),
.rx_data_1_rx_serial_data (rx_data[1]),
.rx_data_2_rx_serial_data (rx_data[2]),
.rx_data_3_rx_serial_data (rx_data[3]),
.rx_ref_clk_clk (rx_ref_clk),
.rx_sync_rx_sync (rx_sync),
.rx_sysref_rx_ext_sysref_in (rx_sysref),
.rx_sync_export (rx_sync),
.rx_sysref_export (rx_sysref),
.sys_clk_clk (sys_clk),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
@ -277,10 +280,13 @@ module system_top (
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
.tx_data_tx_serial_data (tx_data),
.tx_data_0_tx_serial_data (tx_data[0]),
.tx_data_1_tx_serial_data (tx_data[1]),
.tx_data_2_tx_serial_data (tx_data[2]),
.tx_data_3_tx_serial_data (tx_data[3]),
.tx_ref_clk_clk (tx_ref_clk),
.tx_sync_tx_sync (tx_sync),
.tx_sysref_tx_ext_sysref_in (tx_sysref));
.tx_sync_export (tx_sync),
.tx_sysref_export (tx_sysref));
endmodule