ccbox- added
Rejeesh Kutty
parent
fb5d36b250
commit
5e6b931150
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@ -0,0 +1,82 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/pzsdr2_constr_lvds.xdc
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M_DEPS += ../common/pzsdr2_constr.xdc
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M_DEPS += ../common/pzsdr2_bd.tcl
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M_DEPS += ../common/ccbrk_constr.xdc
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M_DEPS += ../common/ccbrk_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
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M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib pzsdr2_ccbrk_lvds.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_ad9361 clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_gpreg clean
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make -C ../../../library/xilinx/axi_xcvrlb clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_tdd_sync clean
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make -C ../../../library/util_upack clean
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make -C ../../../library/util_wfifo clean
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pzsdr2_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_lvds_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_ad9361
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_gpreg
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make -C ../../../library/xilinx/axi_xcvrlb
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make -C ../../../library/util_cpack
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make -C ../../../library/util_tdd_sync
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make -C ../../../library/util_upack
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make -C ../../../library/util_wfifo
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####################################################################################
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####################################################################################
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@ -0,0 +1,6 @@
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source ../common/pzsdr2_bd.tcl
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source ../common/ccbrk_bd.tcl
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cfg_ad9361_interface LVDS
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@ -0,0 +1,18 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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set p_device "xc7z035ifbg676-2L"
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adi_project_create pzsdr2_ccbrk_lvds
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adi_project_files pzsdr2_ccbrk_lvds [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"../common/pzsdr2_constr.xdc" \
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"../common/pzsdr2_constr_lvds.xdc" \
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"../common/ccbrk_constr.xdc" \
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"system_top.v" ]
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set_property is_enabled false [get_files *axi_gpreg_constr.xdc]
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adi_project_run pzsdr2_ccbrk_lvds
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@ -0,0 +1,247 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout iic_scl,
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inout iic_sda,
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inout [19:0] gpio_bd,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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output enable,
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output txnrx,
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input clkout_in,
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output clkout_out,
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inout gpio_clksel,
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inout gpio_resetb,
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inout gpio_sync,
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inout gpio_en_agc,
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inout [ 3:0] gpio_ctl,
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inout [ 7:0] gpio_status,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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output [85:0] gp_out,
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input [85:0] gp_in,
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input gt_ref_clk_p,
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input gt_ref_clk_n,
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output [ 3:0] gt_tx_p,
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output [ 3:0] gt_tx_n,
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input [ 3:0] gt_rx_p,
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input [ 3:0] gt_rx_n);
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// internal signals
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wire gt_ref_clk;
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wire [95:0] gp_out_s;
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wire [95:0] gp_in_s;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// assignments
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assign clkout_out = clkout_in;
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assign gp_out[85:0] = gp_out_s[85:0];
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assign gp_in_s[95:86] = gp_out_s[95:86];
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assign gp_in_s[85: 0] = gp_in[85:0];
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// instantiations
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IBUFDS_GTE2 i_ibufds_gt_ref_clk (
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.CEB (1'd0),
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.I (gt_ref_clk_p),
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.IB (gt_ref_clk_n),
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.O (gt_ref_clk),
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.ODIV2 ());
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ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
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.dio_t ({gpio_t[51], gpio_t[46:32]}),
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.dio_i ({gpio_o[51], gpio_o[46:32]}),
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.dio_o ({gpio_i[51], gpio_i[46:32]}),
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.dio_p ({ gpio_clksel, // 51:51
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gpio_resetb, // 46:46
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gpio_sync, // 45:45
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gpio_en_agc, // 44:44
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gpio_ctl, // 43:40
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gpio_status})); // 39:32
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ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
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.dio_t (gpio_t[19:0]),
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.dio_i (gpio_o[19:0]),
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.dio_o (gpio_i[19:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gp_in_0 (gp_in_s[31:0]),
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.gp_in_1 (gp_in_s[63:32]),
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.gp_in_2 (gp_in_s[95:64]),
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.gp_in_3 (32'd0),
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.gp_out_0 (gp_out_s[31:0]),
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.gp_out_1 (gp_out_s[63:32]),
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.gp_out_2 (gp_out_s[95:64]),
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.gp_out_3 (),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.gt_ref_clk (gt_ref_clk),
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.gt_rx_n (gt_rx_n),
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.gt_rx_p (gt_rx_p),
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.gt_tx_n (gt_tx_n),
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.gt_tx_p (gt_tx_p),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.otg_vbusoc (1'b0),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.ps_intr_15 (1'b0),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o (),
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.tdd_sync_i (1'b0),
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.tdd_sync_o (),
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.tdd_sync_t (),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx),
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.up_enable (gpio_o[47]),
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.up_txnrx (gpio_o[48]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,46 @@
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# unused
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ad_connect sys_ps7/ENET1_GMII_RX_CLK GND
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ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
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# GPS-UART
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set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA2 1 [get_bd_cells sys_ps7]
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# i2s
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create_bd_port -dir O -type clk i2s_mclk
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create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
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set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
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set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
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set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
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ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
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ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA2_ACLK
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
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ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
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ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
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ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
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ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
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ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
|
||||
ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
|
||||
ad_connect i2s axi_i2s_adi/I2S
|
||||
|
||||
ad_cpu_interconnect 0x77600000 axi_i2s_adi
|
||||
|
||||
Loading…
Reference in New Issue