axi_spi_engine: Fix the SYNC interface

The ready signal of the SYNC interface should be always 1'b1,
regardless of ASYNC_SPI_VALUE.

Drive the ready with one in both branches of the ASYNC_SPI_CLK
generate block.

library/spi_engine/axi_spi_engine/axi_spi_engine.v

@@ -515,6 +515,7 @@ module axi_spi_engine #(
 
       assign sync_fifo_valid = sync_valid;
       assign sync_fifo_data = sync_data;
+      assign sync_ready = 1'b1;
 
       assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
       assign offload0_cmd_wr_data = up_wdata_s[15:0];