From 5ec87615b038ca18fa139e6faccbdbf92ee61c66 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Wed, 11 Sep 2019 16:43:45 +0300 Subject: [PATCH] axi_spi_engine: Fix the SYNC interface The ready signal of the SYNC interface should be always 1'b1, regardless of ASYNC_SPI_VALUE. Drive the ready with one in both branches of the ASYNC_SPI_CLK generate block. --- library/spi_engine/axi_spi_engine/axi_spi_engine.v | 1 + 1 file changed, 1 insertion(+) diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 793da5ec6..1ba576fdb 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -515,6 +515,7 @@ module axi_spi_engine #( assign sync_fifo_valid = sync_valid; assign sync_fifo_data = sync_data; + assign sync_ready = 1'b1; assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; assign offload0_cmd_wr_data = up_wdata_s[15:0];