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axi_ad9371: Update dac_clk_ratio to 2 

DAC sampling frequency is two times of the JESD204
core clock.
main
Istvan Csomortani 2017-05-10 11:12:45 +03:00
parent 0e5a24ee7c
commit 5fe008d887
1 changed files with 1 additions and 1 deletions
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2
library/axi_ad9371/axi_ad9371_tx.v
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@ -258,7 +258,7 @@ module axi_ad9371_tx #(
.dac_status (1'b1), .dac_status (1'b1),
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1), .dac_clk_ratio (32'd2),
.up_drp_sel (), .up_drp_sel (),
.up_drp_wr (), .up_drp_wr (),
.up_drp_addr (), .up_drp_addr (),