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util_dacfifo: Update the bypass logic

main
Istvan Csomortani 2018-08-21 13:59:25 +01:00 committed by István Csomortáni
parent 6be4658d49
commit 6044aa3956
5 changed files with 67 additions and 43 deletions
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2
library/util_dacfifo/Makefile
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@ -8,6 +8,8 @@ LIBRARY_NAME := util_dacfifo
GENERIC_DEPS += ../common/ad_b2g.v
GENERIC_DEPS += ../common/ad_g2b.v
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += ../common/ad_mem_asym.v
GENERIC_DEPS += util_dacfifo_bypass.v
GENERIC_DEPS += util_dacfifo.v
XILINX_DEPS += util_dacfifo_constr.xdc

73
library/util_dacfifo/util_dacfifo.v
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@ -74,11 +74,9 @@ module util_dacfifo #(
reg [(ADDRESS_WIDTH-1):0] dma_raddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_addr_diff = 'b0;
reg dma_ready_fifo = 1'b0;
reg dma_ready_bypass = 1'b0;
reg dma_bypass = 1'b0;
reg dma_bypass_m1 = 1'b0;
reg dma_xfer_out_fifo = 1'b0;
reg dma_xfer_out_bypass = 1'b0;
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dac_raddr_g = 'b0;
@ -92,15 +90,16 @@ module util_dacfifo #(
reg dac_mem_ready = 1'b0;
reg dac_xfer_out_fifo = 1'b0;
reg dac_xfer_out_fifo_m1 = 1'b0;
reg dac_xfer_out_bypass = 1'b0;
reg dac_xfer_out_bypass_m1 = 1'b0;
reg dac_xfer_out_fifo_d = 1'b0;
reg dac_bypass = 1'b0;
reg dac_bypass_m1 = 1'b0;
// internal wires
wire dma_wren_s;
wire [(DATA_WIDTH-1):0] dac_data_s;
wire dma_ready_bypass_s;
wire [(DATA_WIDTH-1):0] dac_data_fifo_s;
wire [(DATA_WIDTH-1):0] dac_data_bypass_s;
wire [ADDRESS_WIDTH:0] dma_addr_diff_s;
wire [ADDRESS_WIDTH:0] dac_addr_diff_s;
wire [(ADDRESS_WIDTH-1):0] dma_waddr_b2g_s;
@ -112,18 +111,6 @@ module util_dacfifo #(
// DMA / Write interface
// fifo is always ready, if it's not in bypass mode
always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin
dma_ready_fifo <= 1'b0;
end else begin
dma_ready_fifo <= 1'b1;
end
end
// if bypass is enabled, fifo request data until reaches the high threshold.
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
always @(posedge dma_clk) begin
@ -132,16 +119,16 @@ module util_dacfifo #(
dma_raddr_m1 <= 'b0;
dma_raddr_m2 <= 'b0;
dma_raddr <= 'b0;
dma_ready_bypass <= 1'b0;
dma_ready_fifo <= 1'b0;
end else begin
dma_raddr_m1 <= dac_raddr_g;
dma_raddr_m2 <= dma_raddr_m1;
dma_raddr <= dma_raddr_g2b_s;
dma_addr_diff <= dma_addr_diff_s[ADDRESS_WIDTH-1:0];
if (dma_addr_diff >= FIFO_THRESHOLD_HI) begin
dma_ready_bypass <= 1'b0;
dma_ready_fifo <= 1'b0;
end else begin
dma_ready_bypass <= 1'b1;
dma_ready_fifo <= 1'b1;
end
end
end
@ -161,18 +148,15 @@ module util_dacfifo #(
dma_waddr <= 'b0;
dma_waddr_g <= 'b0;
dma_xfer_out_fifo <= 1'b0;
dma_xfer_out_bypass <= 1'b0;
end else begin
if (dma_wren_s == 1'b1) begin
dma_waddr <= dma_waddr + 1'b1;
dma_xfer_out_fifo <= 1'b0;
end
if (dma_xfer_last == 1'b1) begin
dma_waddr <= 'b0;
dma_xfer_out_fifo <= 1'b1;
end
dma_waddr_g <= dma_waddr_b2g_s;
dma_xfer_out_bypass <= dma_xfer_req;
end
end
@ -234,16 +218,14 @@ module util_dacfifo #(
dac_lastaddr_m2 <= 1'b0;
dac_xfer_out_fifo_m1 <= 1'b0;
dac_xfer_out_fifo <= 1'b0;
dac_xfer_out_bypass_m1 <= 1'b0;
dac_xfer_out_bypass <= 1'b0;
dac_xfer_out_fifo_d <= 1'b0;
end else begin
dac_lastaddr_m1 <= dma_lastaddr_g;
dac_lastaddr_m2 <= dac_lastaddr_m1;
dac_lastaddr <= dac_lastaddr_g2b_s;
dac_xfer_out_fifo_m1 <= dma_xfer_out_fifo;
dac_xfer_out_fifo <= dac_xfer_out_fifo_m1;
dac_xfer_out_bypass_m1 <= dma_xfer_out_bypass;
dac_xfer_out_bypass <= dac_xfer_out_bypass_m1;
dac_xfer_out_fifo_d <= dac_xfer_out_fifo; // read consume at least one clock cycle
end
end
@ -255,7 +237,8 @@ module util_dacfifo #(
// generate dac read address
assign dac_mem_ren_s = (dac_bypass == 1'b1) ? (dac_valid & dac_mem_ready) : (dac_valid & dac_xfer_out_fifo);
assign dac_mem_ren_s = (dac_bypass == 1'b1) ? (dac_valid & dac_mem_ready) :
(dac_valid & dac_xfer_out_fifo);
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
@ -263,7 +246,7 @@ module util_dacfifo #(
dac_raddr_g <= 'b0;
end else begin
if (dac_mem_ren_s == 1'b1) begin
if (dac_lastaddr == 'b0 || dac_raddr < dac_lastaddr) begin
if (dac_lastaddr == 'b0 || dac_raddr != dac_lastaddr) begin
dac_raddr <= dac_raddr + 1'b1;
end else begin
dac_raddr <= 'b0;
@ -292,7 +275,7 @@ module util_dacfifo #(
.clkb (dac_clk),
.reb (1'b1),
.addrb (dac_raddr),
.doutb (dac_data_s));
.doutb (dac_data_fifo_s));
// define underflow
// underflow make sense just if bypass is enabled
@ -301,11 +284,28 @@ module util_dacfifo #(
if (dac_rst == 1'b1) begin
dac_dunf <= 1'b0;
end else begin
dac_dunf <= (dac_bypass == 1'b1) ? (dac_valid & dac_xfer_out_bypass & ~dac_mem_ren_s) : 1'b0;
dac_dunf <= (dac_bypass == 1'b1) ? (dac_valid & dac_xfer_req & ~dac_mem_ren_s) : 1'b0;
end
end
// output logic
// bypass logic
util_dacfifo_bypass #(
.DAC_DATA_WIDTH (DATA_WIDTH),
.DMA_DATA_WIDTH (DATA_WIDTH)
) i_dacfifo_bypass (
.dma_clk(dma_clk),
.dma_data(dma_data),
.dma_ready(dma_ready),
.dma_ready_out(dma_ready_bypass_s),
.dma_valid(dma_valid),
.dma_xfer_req(dma_xfer_req),
.dac_clk(dac_clk),
.dac_rst(dac_rst),
.dac_valid(dac_valid),
.dac_data(dac_data_bypass_s),
.dac_dunf(dac_dunf_bypass_s)
);
always @(posedge dma_clk) begin
dma_bypass_m1 <= bypass;
@ -318,12 +318,15 @@ module util_dacfifo #(
end
always @(posedge dma_clk) begin
dma_ready <= (dma_bypass == 1'b1) ? dma_ready_bypass : dma_ready_fifo;
dma_ready <= (dma_bypass == 1'b1) ? dma_ready_bypass_s : dma_ready_fifo;
end
always @(posedge dac_clk) begin
dac_data <= dac_data_s;
dac_xfer_out <= (dac_bypass == 1'b1) ? dac_xfer_out_bypass : dac_xfer_out_fifo;
if (dac_valid) begin
dac_data <= (dac_bypass == 1'b1) ? dac_data_bypass_s : dac_data_fifo_s;
end
// this signal along with the dac_valid validate the data coming out from the buffer
dac_xfer_out <= (dac_bypass == 1'b1) ? dac_xfer_req : dac_xfer_out_fifo_d;
end
endmodule

5
library/util_dacfifo/util_dacfifo_constr.sdc
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@ -7,3 +7,8 @@ set_false_path -from [get_registers *dma_waddr_g*] -to [get_registers *dac_waddr
set_false_path -from [get_registers *dma_lastaddr_g*] -to [get_registers *dac_lastaddr_m1*]
set_false_path -from [get_registers *dma_xfer_out_fifo*] -to [get_registers *dac_xfer_out_fifo_m1*]
set_false_path -from [get_registers *dma_xfer_out_bypass*] -to [get_registers *dac_xfer_out_bypass_m1*]
set_false_path -from [get_registers *dma_mem_waddr_g*] -to [get_registers *dac_mem_waddr_m1*]
set_false_path -from [get_registers *dac_mem_raddr_g*] -to [get_registers *dma_mem_raddr_m1*]
set_false_path -to [get_registers *dma_rst_m1*]

28
library/util_dacfifo/util_dacfifo_constr.xdc
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@ -1,10 +1,10 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_raddr_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_waddr_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_lastaddr_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_xfer_out*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_bypass*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_bypass*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_raddr_m*}] \
[get_cells -hier -filter {name =~ *dac_waddr_m*}] \
[get_cells -hier -filter {name =~ *dac_lastaddr_m*}] \
[get_cells -hier -filter {name =~ *dac_xfer_out_*}] \
[get_cells -hier -filter {name =~ *dma_bypass*}] \
[get_cells -hier -filter {name =~ *dac_bypass*}]
set_false_path -from [get_cells -hier -filter {name =~ *dac_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_raddr_m1* && IS_SEQUENTIAL}]
@ -14,7 +14,19 @@ set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_g* && IS_SE
-to [get_cells -hier -filter {name =~ *dac_lastaddr_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_fifo* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_xfer_out_fifo_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_bypass* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_xfer_out_bypass_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_bypass_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dma_bypass_m1* && IS_SEQUENTIAL}]
# util_dacfifo_bypass CDC false-paths
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_mem_*_m*}] \
[get_cells -hier -filter {name =~ *dma_mem_*_m*}] \
[get_cells -hier -filter {name =~ *dma_rst_m1*}] \
[get_cells -hier -filter {name =~ *dac_xfer_out_m1*}]
set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]

2
library/util_dacfifo/util_dacfifo_ip.tcl
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@ -6,9 +6,11 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_dacfifo
adi_ip_files util_dacfifo [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/ad_b2g.v" \
"$ad_hdl_dir/library/common/ad_g2b.v" \
"util_dacfifo.v" \
"util_dacfifo_bypass.v" \
"util_dacfifo_constr.xdc"]
adi_ip_properties_lite util_dacfifo