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ad7606x: Add configurable digital interface support 

Unified the ad7606x_fmc project, where both the serial and the parallel interface are implemented.
---------

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
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PIoandan 2024-04-26 12:03:31 +03:00 committed by GitHub
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11 changed files with 795 additions and 368 deletions
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242
library/axi_ad7606x/axi_ad7606x.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -37,142 +37,142 @@
module axi_ad7606x #(
parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_CH_DW = 16,
parameter ADC_N_BITS = 16,
parameter EXTERNAL_CLK = 0
parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_TO_DMA_N_BITS = 16,
parameter ADC_N_BITS = 16,
parameter EXTERNAL_CLK = 0
) (
// physical data interface
output rx_cs_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
input external_clk,
output rx_cs_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
input external_clk,
// physical control interface
input rx_busy,
input first_data,
input rx_busy,
input first_data,
// AXI Slave Memory Map
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input adc_dovf,
output adc_clk,
input adc_dovf,
output adc_clk,
output adc_valid,
output [ADC_CH_DW-1:0] adc_data_0,
output [ADC_CH_DW-1:0] adc_data_1,
output [ADC_CH_DW-1:0] adc_data_2,
output [ADC_CH_DW-1:0] adc_data_3,
output [ADC_CH_DW-1:0] adc_data_4,
output [ADC_CH_DW-1:0] adc_data_5,
output [ADC_CH_DW-1:0] adc_data_6,
output [ADC_CH_DW-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_reset
output adc_valid,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_0,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_1,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_2,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_3,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_4,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_5,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_6,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_reset
);
localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;
localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
// internal signals
wire [ADC_N_BITS-1:0] adc_data_0_s;
wire [ADC_N_BITS-1:0] adc_data_1_s;
wire [ADC_N_BITS-1:0] adc_data_2_s;
wire [ADC_N_BITS-1:0] adc_data_3_s;
wire [ADC_N_BITS-1:0] adc_data_4_s;
wire [ADC_N_BITS-1:0] adc_data_5_s;
wire [ADC_N_BITS-1:0] adc_data_6_s;
wire [ADC_N_BITS-1:0] adc_data_7_s;
wire [(8*ADC_N_BITS)-1:0] adc_data_s;
wire [ 7:0] adc_status_header[0:7];
wire adc_status;
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;
wire [ADC_N_BITS-1:0] adc_data_0_s;
wire [ADC_N_BITS-1:0] adc_data_1_s;
wire [ADC_N_BITS-1:0] adc_data_2_s;
wire [ADC_N_BITS-1:0] adc_data_3_s;
wire [ADC_N_BITS-1:0] adc_data_4_s;
wire [ADC_N_BITS-1:0] adc_data_5_s;
wire [ADC_N_BITS-1:0] adc_data_6_s;
wire [ADC_N_BITS-1:0] adc_data_7_s;
wire [(8*ADC_N_BITS)-1:0] adc_data_s;
wire [ 7:0] adc_status_header[0:7];
wire adc_status;
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;
wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
wire adc_dfmt_se_s[0:7];
wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
wire adc_dfmt_se_s[0:7];
wire adc_clk_s;
wire [ 7:0] adc_enable;
wire adc_reset_s;
wire adc_clk_s;
wire [ 7:0] adc_enable;
wire adc_reset_s;
wire [(8*ADC_CH_DW)-1:0] dma_data;
wire dma_dvalid;
wire [(8*ADC_TO_DMA_N_BITS)-1:0] dma_data;
wire dma_dvalid;
wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire [31:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [31:0] adc_config_ctrl_s;
wire adc_ctrl_status_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
wire [31:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [31:0] adc_config_ctrl_s;
wire adc_ctrl_status_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
// defaults
@ -287,13 +287,13 @@ module axi_ad7606x #(
for (k = 0;k < 8;k = k + 1) begin
ad_datafmt #(
.DATA_WIDTH (ADC_N_BITS),
.BITS_PER_SAMPLE (ADC_CH_DW)
.BITS_PER_SAMPLE (ADC_TO_DMA_N_BITS)
) i_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]),
.valid_out (dma_dvalid),
.data_out (dma_data[k*ADC_CH_DW+(ADC_CH_DW-1):k*ADC_CH_DW]),
.data_out (dma_data[k*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):k*ADC_TO_DMA_N_BITS]),
.dfmt_enable (adc_dfmt_enable_s[k]),
.dfmt_type (adc_dfmt_type_s[k]),
.dfmt_se (adc_dfmt_se_s[k]));
@ -385,14 +385,14 @@ module axi_ad7606x #(
endgenerate
assign adc_data_s = {adc_data_0_s,adc_data_1_s,adc_data_2_s,adc_data_3_s,adc_data_4_s,adc_data_5_s,adc_data_6_s,adc_data_7_s};
assign adc_data_7 = dma_data[0*ADC_CH_DW+(ADC_CH_DW-1):0*ADC_CH_DW];
assign adc_data_6 = dma_data[1*ADC_CH_DW+(ADC_CH_DW-1):1*ADC_CH_DW];
assign adc_data_5 = dma_data[2*ADC_CH_DW+(ADC_CH_DW-1):2*ADC_CH_DW];
assign adc_data_4 = dma_data[3*ADC_CH_DW+(ADC_CH_DW-1):3*ADC_CH_DW];
assign adc_data_3 = dma_data[4*ADC_CH_DW+(ADC_CH_DW-1):4*ADC_CH_DW];
assign adc_data_2 = dma_data[5*ADC_CH_DW+(ADC_CH_DW-1):5*ADC_CH_DW];
assign adc_data_1 = dma_data[6*ADC_CH_DW+(ADC_CH_DW-1):6*ADC_CH_DW];
assign adc_data_0 = dma_data[7*ADC_CH_DW+(ADC_CH_DW-1):7*ADC_CH_DW];
assign adc_data_7 = dma_data[0*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):0*ADC_TO_DMA_N_BITS];
assign adc_data_6 = dma_data[1*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):1*ADC_TO_DMA_N_BITS];
assign adc_data_5 = dma_data[2*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):2*ADC_TO_DMA_N_BITS];
assign adc_data_4 = dma_data[3*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):3*ADC_TO_DMA_N_BITS];
assign adc_data_3 = dma_data[4*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):4*ADC_TO_DMA_N_BITS];
assign adc_data_2 = dma_data[5*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):5*ADC_TO_DMA_N_BITS];
assign adc_data_1 = dma_data[6*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):6*ADC_TO_DMA_N_BITS];
assign adc_data_0 = dma_data[7*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):7*ADC_TO_DMA_N_BITS];
up_adc_common #(
.ID (ID),

27
projects/ad7606x_fmc/Readme.md
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@ -3,9 +3,9 @@
Here are some pointers to help you:
* [EVAL-AD7606B Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7606b-fmcz.html)
* [EVAL-AD7606C-16/18 Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7606c-18.html)
* Parts : AD7606B [8 Channels, 16-bit, 800 kSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606b.html)
* Parts : AD7606C-16 [8 Channels, 16-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-16.html)
* Parts : AD7606B [8 Channels, 18-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-18.html)
* Parts : [AD7606B, 8 Channels, 16-bit, 800 kSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606b.html)
* Parts : [AD7606B, 8 Channels, 18-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-18.html)
* Parts : [AD7606C-16, 8 Channels, 16-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC](https://www.analog.com/en/products/ad7606c-16.html)
* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmcz
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl
* NO-OS Drivers: [AD7606 - No-OS Driver](https://wiki.analog.com/resources/tools-software/uc-drivers/ad7606)
@ -16,7 +16,24 @@ IMPORTANT: Set AD7606X device model, ADC Read Mode option and external clock opt
How to use over-writable parameters from the environment:
```
hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=0 SIMPLE_STATUS_CRC=0
hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=4
DEV_CONFIG - Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
SIMPLE_STATUS_CRC - Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS.
INTF - Defines the operation interface: 0 - Parallel, 1 - Serial
NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4, 8
EXT_CLK - Defines the external clock option for the ADC clock: 0 - No, 1 - Yes.
For the serial interface, the following parameters will be used in make command: DEV_CONFIG, INTF, NUM_OF_SDI.
For the parallel interface, the following parameters will be used in make command: DEV_CONFIG, INTF,EXT_CLK.
**Example:**
make DEV_CONFIG=0 INTF=1 NUM_OF_SDI=1
make DEV_CONFIG=1 INTF=1 NUM_OF_SDI=2
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=1
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=2
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=4
make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=8
make DEV_CONFIG=0 INTF=0 EXT_CLK=0
make DEV_CONFIG=1 INTF=0 EXT_CLK=0
make DEV_CONFIG=2 INTF=0 EXT_CLK=0
...

291
projects/ad7606x_fmc/common/ad7606x_bd.tcl
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@ -1,125 +1,218 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# system level parameters
set DEV_CONFIG $ad_project_params(DEV_CONFIG)
set INTF $ad_project_params(INTF)
set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
set ADC_N_BITS [expr {$DEV_CONFIG == 2 ? 18 : 16}]
set ADC_CH_DW [expr {$ADC_N_BITS == 16 ? 16 : 32}]
set ADC_TO_DMA_N_BITS [expr {$ADC_N_BITS == 16 ? 16 : 32}]
set EXT_CLK $ad_project_params(EXT_CLK)
set TOTAL_N_BITS_DMA [expr {$ADC_CH_DW*8}]
set TOTAL_N_BITS_DMA [expr {$ADC_TO_DMA_N_BITS*8}]
puts "build parameters: DEV_CONFIG: $DEV_CONFIG"
puts "build parameters: INTF: $INTF"
puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI"
puts "build parameters: EXT_CLK: $EXT_CLK"
# data, read and write lines
create_bd_port -dir O -from 15 -to 0 rx_db_o
create_bd_port -dir I -from 15 -to 0 rx_db_i
create_bd_port -dir O rx_db_t
create_bd_port -dir O rx_rd_n
create_bd_port -dir O rx_wr_n
# control lines
create_bd_port -dir I rx_busy
create_bd_port -dir O rx_cnvst_n
create_bd_port -dir O rx_cs_n
create_bd_port -dir I rx_first_data
# instantiation
ad_ip_instance axi_ad7606x axi_ad7606x
ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
ad_ip_parameter axi_ad7606x CONFIG.ADC_N_BITS $ADC_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.ADC_CH_DW $ADC_CH_DW
ad_ip_parameter axi_ad7606x CONFIG.EXTERNAL_CLK $EXT_CLK
ad_ip_instance axi_pwm_gen axi_pwm_gen
ad_ip_parameter axi_pwm_gen CONFIG.ASYNC_CLK_EN 0
ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 1
if {$DEV_CONFIG == 0} {
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 124
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 125
} else {
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 99
ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 100
}
# axi_pwm_gen
ad_ip_instance axi_pwm_gen ad7606_pwm_gen
# dma
ad_ip_instance axi_dmac axi_ad7606x_dma
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7606x_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_SRC $TOTAL_N_BITS_DMA
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_cpack2 ad7606x_adc_pack
ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_CH_DW
switch $INTF {
0 {
# data, read and write lines
create_bd_port -dir O -from 15 -to 0 rx_db_o
create_bd_port -dir I -from 15 -to 0 rx_db_i
create_bd_port -dir O rx_db_t
create_bd_port -dir O rx_rd_n
create_bd_port -dir O rx_wr_n
if {$EXT_CLK == 1} {
# use Xilinx's clocking wizard in order to generate th clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP
ad_ip_instance clk_wiz adc_clk_generator
ad_ip_parameter adc_clk_generator CONFIG.PRIMITIVE PLL
ad_ip_parameter adc_clk_generator CONFIG.RESET_TYPE ACTIVE_LOW
ad_ip_parameter adc_clk_generator CONFIG.USE_LOCKED false
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100.000
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_PHASE 0.000
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000
ad_ip_parameter adc_clk_generator CONFIG.PRIM_SOURCE Global_buffer
ad_ip_parameter adc_clk_generator CONFIG.CLKIN1_UI_JITTER 0
ad_ip_parameter adc_clk_generator CONFIG.PRIM_IN_FREQ 100.000
# control lines
create_bd_port -dir O rx_cs_n
create_bd_port -dir I rx_first_data
ad_connect sys_cpu_clk adc_clk_generator/clk_in1
ad_connect sys_cpu_resetn adc_clk_generator/resetn
ad_connect adc_clk_generator/clk_out1 axi_ad7606x/external_clk
} else {
ad_connect sys_cpu_clk axi_ad7606x/external_clk
# instantiation
ad_ip_instance axi_ad7606x axi_ad7606x
ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
ad_ip_parameter axi_ad7606x CONFIG.ADC_N_BITS $ADC_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.ADC_TO_DMA_N_BITS $ADC_TO_DMA_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.EXTERNAL_CLK $EXT_CLK
# axi_pwm_gen
ad_ip_parameter ad7606_pwm_gen CONFIG.ASYNC_CLK_EN 0
ad_ip_parameter ad7606_pwm_gen CONFIG.N_PWMS 1
if {$DEV_CONFIG == 0} {
ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_WIDTH 124
ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 125
} else {
ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_WIDTH 99
ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 100
}
# dma
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_SRC $TOTAL_N_BITS_DMA
ad_ip_instance util_cpack2 ad7606x_adc_pack
ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_TO_DMA_N_BITS
if {$EXT_CLK == 1} {
# use Xilinx's clocking wizard in order to generate the clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP
ad_ip_instance clk_wiz adc_clk_generator
ad_ip_parameter adc_clk_generator CONFIG.PRIMITIVE PLL
ad_ip_parameter adc_clk_generator CONFIG.RESET_TYPE ACTIVE_LOW
ad_ip_parameter adc_clk_generator CONFIG.USE_LOCKED false
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100.000
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_PHASE 0.000
ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000
ad_ip_parameter adc_clk_generator CONFIG.PRIM_SOURCE Global_buffer
ad_ip_parameter adc_clk_generator CONFIG.CLKIN1_UI_JITTER 0
ad_ip_parameter adc_clk_generator CONFIG.PRIM_IN_FREQ 100.000
ad_connect sys_cpu_clk adc_clk_generator/clk_in1
ad_connect sys_cpu_resetn adc_clk_generator/resetn
ad_connect adc_clk_generator/clk_out1 axi_ad7606x/external_clk
} else {
ad_connect sys_cpu_clk axi_ad7606x/external_clk
}
# interface connections
ad_connect rx_db_o axi_ad7606x/rx_db_o
ad_connect rx_db_i axi_ad7606x/rx_db_i
ad_connect rx_db_t axi_ad7606x/rx_db_t
ad_connect rx_rd_n axi_ad7606x/rx_rd_n
ad_connect rx_wr_n axi_ad7606x/rx_wr_n
ad_connect rx_cs_n axi_ad7606x/rx_cs_n
ad_connect rx_cnvst_n ad7606_pwm_gen/pwm_0
ad_connect rx_busy axi_ad7606x/rx_busy
ad_connect rx_first_data axi_ad7606x/first_data
ad_connect sys_cpu_clk axi_ad7606x_dma/s_axi_aclk
ad_connect sys_cpu_clk ad7606_pwm_gen/s_axi_aclk
ad_connect sys_cpu_resetn ad7606_pwm_gen/s_axi_aresetn
ad_connect axi_ad7606x/adc_clk ad7606x_adc_pack/clk
ad_connect axi_ad7606x/adc_clk axi_ad7606x_dma/fifo_wr_clk
ad_connect axi_ad7606x/adc_reset ad7606x_adc_pack/reset
ad_connect axi_ad7606x/adc_valid ad7606x_adc_pack/fifo_wr_en
ad_connect ad7606x_adc_pack/packed_fifo_wr axi_ad7606x_dma/fifo_wr
ad_connect ad7606x_adc_pack/fifo_wr_overflow axi_ad7606x/adc_dovf
for {set i 0} {$i < 8} {incr i} {
ad_connect axi_ad7606x/adc_data_$i ad7606x_adc_pack/fifo_wr_data_$i
ad_connect axi_ad7606x/adc_enable_$i ad7606x_adc_pack/enable_$i
}
# interconnect
ad_cpu_interconnect 0x44a00000 axi_ad7606x
ad_cpu_interconnect 0x44a30000 axi_ad7606x_dma
ad_cpu_interconnect 0x44b00000 ad7606_pwm_gen
# memory interconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad7606x_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad7606x_dma/m_dest_axi_aresetn
# interrupt
ad_cpu_interrupt ps-13 mb-12 axi_ad7606x_dma/irq
}
1 {
# instantiation
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad7606_spi
# spi engine
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
set data_width $ADC_TO_DMA_N_BITS
set async_spi_clk 1
set num_cs 1
set num_sdi $NUM_OF_SDI
set num_sdo 1
set sdi_delay 1
set hier_spi_engine spi_ad7606
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay
# axi_clkgen
ad_ip_instance axi_clkgen spi_clkgen
ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 6
# axi_pwm_gen
ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 120
ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_WIDTH 1
# trigger to BUSY's negative edge
create_bd_cell -type module -reference sync_bits busy_sync
create_bd_cell -type module -reference ad_edge_detect busy_capture
set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
ad_connect spi_clk busy_capture/clk
ad_connect busy_capture/rst GND
ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn
ad_connect spi_clk busy_sync/out_clk
ad_connect busy_sync/in_bits rx_busy
ad_connect busy_sync/out_bits busy_capture/signal_in
ad_connect busy_capture/signal_out $hier_spi_engine/trigger
# dma
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad7606x_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad7606x_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad7606x_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $num_sdi]
# interface connections
ad_connect $sys_cpu_clk spi_clkgen/clk
ad_connect $sys_cpu_clk $hier_spi_engine/clk
ad_connect $sys_cpu_clk ad7606_pwm_gen/s_axi_aclk
ad_connect spi_clk spi_clkgen/clk_0
ad_connect spi_clk $hier_spi_engine/spi_clk
ad_connect spi_clk ad7606_pwm_gen/ext_clk
ad_connect spi_clk axi_ad7606x_dma/s_axis_aclk
ad_connect sys_cpu_resetn ad7606_pwm_gen/s_axi_aresetn
ad_connect sys_cpu_resetn $hier_spi_engine/resetn
ad_connect sys_cpu_resetn axi_ad7606x_dma/m_dest_axi_aresetn
ad_connect rx_cnvst_n ad7606_pwm_gen/pwm_0
ad_connect axi_ad7606x_dma/s_axis $hier_spi_engine/m_axis_sample
ad_connect ad7606_spi $hier_spi_engine/m_spi
# interconnect
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
ad_cpu_interconnect 0x44a30000 axi_ad7606x_dma
ad_cpu_interconnect 0x44a70000 spi_clkgen
ad_cpu_interconnect 0x44b00000 ad7606_pwm_gen
# interrupts
ad_cpu_interrupt ps-13 mb-13 axi_ad7606x_dma/irq
ad_cpu_interrupt ps-12 mb-12 /$hier_spi_engine/irq
# memory interconnect
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_ad7606x_dma/m_dest_axi
}
}
# interface connections
ad_connect rx_db_o axi_ad7606x/rx_db_o
ad_connect rx_db_i axi_ad7606x/rx_db_i
ad_connect rx_db_t axi_ad7606x/rx_db_t
ad_connect rx_rd_n axi_ad7606x/rx_rd_n
ad_connect rx_wr_n axi_ad7606x/rx_wr_n
ad_connect rx_cs_n axi_ad7606x/rx_cs_n
ad_connect rx_cnvst_n axi_pwm_gen/pwm_0
ad_connect rx_busy axi_ad7606x/rx_busy
ad_connect rx_first_data axi_ad7606x/first_data
ad_connect sys_cpu_clk axi_ad7606x_dma/s_axi_aclk
ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk
ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn
ad_connect axi_ad7606x/adc_clk ad7606x_adc_pack/clk
ad_connect axi_ad7606x/adc_clk axi_ad7606x_dma/fifo_wr_clk
ad_connect axi_ad7606x/adc_reset ad7606x_adc_pack/reset
ad_connect axi_ad7606x/adc_valid ad7606x_adc_pack/fifo_wr_en
ad_connect ad7606x_adc_pack/packed_fifo_wr axi_ad7606x_dma/fifo_wr
ad_connect ad7606x_adc_pack/fifo_wr_overflow axi_ad7606x/adc_dovf
for {set i 0} {$i < 8} {incr i} {
ad_connect axi_ad7606x/adc_data_$i ad7606x_adc_pack/fifo_wr_data_$i
ad_connect axi_ad7606x/adc_enable_$i ad7606x_adc_pack/enable_$i
}
# interconnect
ad_cpu_interconnect 0x44A00000 axi_ad7606x
ad_cpu_interconnect 0x44A30000 axi_ad7606x_dma
ad_cpu_interconnect 0x44A60000 axi_pwm_gen
# memory interconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad7606x_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad7606x_dma/m_dest_axi_aresetn
#interrupt
ad_cpu_interrupt ps-13 mb-12 axi_ad7606x_dma/irq

74
projects/ad7606x_fmc/common/ad7606x_fmc.txt
View File

@ -1,36 +1,46 @@
FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
# ad7606x
D08 LA01_CC_P DB0_1 adc_db[0] LVCMOS25 #N/A
D09 LA01_CC_N DB1_1 adc_db[1] LVCMOS25 #N/A
H08 LA02_N DB2_1 adc_db[2] LVCMOS25 #N/A
G10 LA03_N DB3_1 adc_db[3] LVCMOS25 #N/A
H11 LA04_N DB4_1 adc_db[4] LVCMOS25 #N/A
H14 LA07_N DB5_1 adc_db[5] LVCMOS25 #N/A
G13 LA08_N DB6_1 adc_db[6] LVCMOS25 #N/A
G07 LA00_CC_N DOUTA_1 adc_db[7] LVCMOS25 #N/A
C11 LA06_N DOUTB_1 adc_db[8] LVCMOS25 #N/A
D11 LA05_P DOUTC_1 adc_db[9] LVCMOS25 #N/A
D14 LA09_P DOUTD_1 adc_db[10] LVCMOS25 #N/A
G09 LA03_P SDI_1 adc_db[11] LVCMOS25 #N/A
H17 LA11_N DB12_1 adc_db[12] LVCMOS25 #N/A
G16 LA12_N DB13_1 adc_db[13] LVCMOS25 #N/A
D17 LA13_P DB14_1 adc_db[14] LVCMOS25 #N/A
D18 LA13_N DB15_1 adc_db[15] LVCMOS25 #N/A
G7 FMC_LA00_CC_N DOUTA_1 ad7606_spi_sdi[0] LVCMOS25 #N/A
C11 FMC_LA06_N DOUTB_1 ad7606_spi_sdi[1] LVCMOS25 #N/A
D11 FMC_LA05_P DOUTC_1 ad7606_spi_sdi[2] LVCMOS25 #N/A
D14 FMC_LA09_P DOUTD_1 ad7606_spi_sdi[3] LVCMOS25 #N/A
G10 FMC_LA03_N DB3_1 ad7606_spi_sdi[4] LVCMOS25 #N/A
H11 FMC_LA04_N DB4_1 ad7606_spi_sdi[5] LVCMOS25 #N/A
H14 FMC_LA07_N DB5_1 ad7606_spi_sdi[6] LVCMOS25 #N/A
G13 FMC_LA08_N DB6_1 ad7606_spi_sdi[7] LVCMOS25 #N/A
G6 FMC_LA00_CC_P SCLK_1 ad7606_spi_sclk LVCMOS25 #N/A
G9 FMC_LA03_P SDI_1 ad7606_spi_sdo LVCMOS25 #N/A
H10 FMC_LA04_P CS_1 ad7606_spi_cs LVCMOS25 #N/A
G06 LA00_CC_P SCLK_1 adc_rd_n LVCMOS25 #N/A
C14 LA10_P WR_SDP adc_wr_n LVCMOS25 #N/A
D08 LA01_CC_P DB0_1 adc_db[0] LVCMOS25 #N/A
D09 LA01_CC_N DB1_1 adc_db[1] LVCMOS25 #N/A
H08 LA02_N DB2_1 adc_db[2] LVCMOS25 #N/A
G10 LA03_N DB3_1 adc_db[3] LVCMOS25 #N/A
H11 LA04_N DB4_1 adc_db[4] LVCMOS25 #N/A
H14 LA07_N DB5_1 adc_db[5] LVCMOS25 #N/A
G13 LA08_N DB6_1 adc_db[6] LVCMOS25 #N/A
G07 LA00_CC_N DOUTA_1 adc_db[7] LVCMOS25 #N/A
C11 LA06_N DOUTB_1 adc_db[8] LVCMOS25 #N/A
D11 LA05_P DOUTC_1 adc_db[9] LVCMOS25 #N/A
D14 LA09_P DOUTD_1 adc_db[10] LVCMOS25 #N/A
G09 LA03_P SDI_1 adc_db[11] LVCMOS25 #N/A
H17 LA11_N DB12_1 adc_db[12] LVCMOS25 #N/A
G16 LA12_N DB13_1 adc_db[13] LVCMOS25 #N/A
D17 LA13_P DB14_1 adc_db[14] LVCMOS25 #N/A
D18 LA13_N DB15_1 adc_db[15] LVCMOS25 #N/A
G06 LA00_CC_P SCLK_1 adc_rd_n LVCMOS25 #N/A
C14 LA10_P WR_SDP adc_wr_n LVCMOS25 #N/A
H10 LA04_P CS_1 adc_cs_n LVCMOS25 #N/A
C19 LA14_N REFSEL adc_refsel LVCMOS25 #N/A
H13 LA07_P BUSY_SDP adc_busy LVCMOS25 #N/A
D12 LA05_N CNVST_SDP adc_cnvst_n LVCMOS25 #N/A
H10 LA04_P CS_1 adc_cs_n LVCMOS25 #N/A
G12 LA08_P FRSTDATA_SDP adc_first_data LVCMOS25 #N/A
C10 LA06_P RESET_1 adc_reset LVCMOS25 #N/A
G15 LA12_P OS0 adc_os[0] LVCMOS25 #N/A
H07 LA04_P OS1 adc_os[1] LVCMOS25 #N/A
H16 LA11_P OS2 adc_os[2] LVCMOS25 #N/A
C15 LA10_N STBY adc_stby LVCMOS25 #N/A
D15 LA09_N RANGE_1 adc_range LVCMOS25 #N/A
C18 LA14_P SERPAR adc_serpar LVCMOS25 #N/A
C19 LA14_N REFSEL adc_refsel LVCMOS25 #N/A
C18 FMC_LA14_P SERPAR adc_serpar LVCMOS25 #N/A
H13 FMC_LA07_P BUSY_SDP adc_busy LVCMOS25 #N/A
G12 FMC_LA08_P FRSTDATA_SDP adc_first_data LVCMOS25 #N/A
C10 FMC_LA06_P RESET_1 adc_reset LVCMOS25 #N/A
G15 FMC_LA12_P OS0 adc_os[0] LVCMOS25 #N/A
H7 FMC_LA02_P OS1 adc_os[1] LVCMOS25 #N/A
H16 FMC_LA11_P OS2 adc_os[2] LVCMOS25 #N/A
C15 FMC_LA10_N STBY adc_stby LVCMOS25 #N/A
D15 FMC_LA09_N RANGE_1 adc_range LVCMOS25 #N/A
D12 FMC_LA05_N CNVST_SDP adc_cnvst_n LVCMOS25 #N/A

9
projects/ad7606x_fmc/zed/Makefile
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@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@ -10,7 +10,10 @@ M_DEPS += ../common/ad7606x_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v
LIB_DEPS += axi_ad7606x
LIB_DEPS += axi_clkgen
@ -20,6 +23,10 @@ LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_pwm_gen
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += sysid_rom
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pack/util_cpack2

11
projects/ad7606x_fmc/zed/system_bd.tcl
View File

@ -1,19 +1,26 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
adi_project_files ad7606x_fmc_zed [list \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/util_cdc/sync_bits.v"]
source ../common/ad7606x_bd.tcl
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
set DEV_CONFIG $ad_project_params(DEV_CONFIG)
set EXT_CLK $ad_project_params(EXT_CLK)
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "$DEV_CONFIG,$EXT_CLK"
set sys_cstring "$DEV_CONFIG,$NUM_OF_SDI,$EXT_CLK"
sysid_gen_sys_init_file $sys_cstring

95
projects/ad7606x_fmc/zed/system_constr.tcl Normal file
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@ -0,0 +1,95 @@
###############################################################################
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7606x
if {![info exists INTF]} {
set INTF $::env(INTF)
}
switch $INTF {
0 {
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ]; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ]; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ]; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ]; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ]; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ]; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ]; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ]; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ]; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ]; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports adc_db[10]]; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports adc_db[11]]; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports adc_db[12]]; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports adc_db[13]]; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]]; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports adc_db[15]]; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_rd_n]; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_wr_n]; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports adc_cs_n]; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports adc_refsel]; ## C19 FMC_LPC_LA14_N
}
1 {
if {![info exists NUM_OF_SDI]} {
set NUM_OF_SDI $::env(NUM_OF_SDI)
}
switch $NUM_OF_SDI {
1 {
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[0]]; ## G07 FMC_LPC_LA00_CC_N
}
2 {
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[0]]; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[1]]; ## C11 FMC_LPC_LA06_N
}
4 {
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[0]]; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[1]]; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[2]]; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[3]]; ## D14 FMC_LPC_LA09_P
}
8 {
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[0]]; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[1]]; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[2]]; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[3]]; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[4]]; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[5]]; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[6]]; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdi[7]]; ## G13 FMC_LPC_LA08_N
}
}
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sclk]; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_sdo]; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad7606_spi_cs]; ## H10 FMC_LPC_LA04_P
# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
# relax the SDO path to help closing timing at high frequencies
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_ad7606_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_ad7606_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
}
}
# control lines
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports adc_serpar]; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports adc_busy]; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports adc_first_data]; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_reset]; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports adc_os[0]]; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]]; ## H07 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports adc_os[2]]; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_stby]; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_range]; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst_n]; ## D12 FMC_LPC_LA05_N

40
projects/ad7606x_fmc/zed/system_constr.xdc
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@ -1,40 +0,0 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7606x
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## C14 FMC_LPC_LA10_P
# control lines
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst_n] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports adc_first_data] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_reset] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## H07 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_stby] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_range] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports adc_serpar] ; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports adc_refsel] ; ## C19 FMC_LPC_LA14_N

37
projects/ad7606x_fmc/zed/system_project.tcl
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@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@ -10,21 +10,52 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# Parameter description
# DEV_CONFIG - The device which will be used
# - Options : AD7606B(0)/C-16(1)/C-18(2)
# INTF - Operation interface
# - Options : Parallel(0)/Serial(1)
# NUM_OF_SDI - Number of SDI lines used
# - Options: 1, 2, 4, 8
# EXT_CLK - Use external clock as ADC clock
# - Options : No(0), Yes(1)
set DEV_CONFIG [get_env_param DEV_CONFIG 0]
set INTF 1
if {[info exists ::env(INTF)]} {
set INTF $::env(INTF)
} else {
set env(INTF) $INTF
}
set NUM_OF_SDI 4
if {[info exists ::env(NUM_OF_SDI)]} {
set NUM_OF_SDI $::env(NUM_OF_SDI)
} else {
set env(NUM_OF_SDI) $NUM_OF_SDI
}
set EXT_CLK [get_env_param EXT_CLK 0]
adi_project ad7606x_fmc_zed 0 [list \
DEV_CONFIG $DEV_CONFIG \
INTF $INTF \
NUM_OF_SDI $NUM_OF_SDI \
EXT_CLK $EXT_CLK \
]
adi_project_files ad7606x_fmc_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"system_top.v" \
"system_constr.xdc"]
"system_constr.tcl"]
switch $INTF {
0 {
adi_project_files ad7606x_fmc_zed [list \
"system_top_pi.v" ]
}
1 {
adi_project_files ad7606x_fmc_zed [list \
"system_top_si.v" ]
}
}
adi_project_run ad7606x_fmc_zed

128
projects/ad7606x_fmc/zed/system_top.v → projects/ad7606x_fmc/zed/system_top_pi.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -37,83 +37,83 @@
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
input otg_vbusoc,
inout [15:0] adc_db,
output adc_rd_n,
output adc_wr_n,
inout [15:0] adc_db,
output adc_rd_n,
output adc_wr_n,
input adc_busy,
output adc_cnvst_n,
output adc_cs_n,
input adc_first_data,
output adc_reset,
output [2:0] adc_os,
output adc_stby,
output adc_range,
output adc_refsel,
output adc_serpar
input adc_busy,
output adc_cnvst_n,
output adc_cs_n,
input adc_first_data,
output adc_reset,
output [2:0] adc_os,
output adc_stby,
output adc_range,
output adc_refsel,
output adc_serpar
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;

207
projects/ad7606x_fmc/zed/system_top_si.v Normal file
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@ -0,0 +1,207 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top #(
parameter NUM_OF_SDI = 2
) (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [1:0] iic_mux_scl,
inout [1:0] iic_mux_sda,
input otg_vbusoc,
output ad7606_spi_cs,
output ad7606_spi_sclk,
input [NUM_OF_SDI-1:0] ad7606_spi_sdi,
output ad7606_spi_sdo,
inout adc_serpar,
input adc_busy,
output adc_cnvst_n,
inout adc_first_data,
output adc_reset,
output [2:0] adc_os,
output adc_stby,
output adc_range
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
assign gpio_i[63:40] = gpio_o[63:40];
// instantiations
ad_iobuf #(
.DATA_WIDTH(8)
) i_iobuf_adc_cntrl (
.dio_t (gpio_t[39:32]),
.dio_i (gpio_o[39:32]),
.dio_o (gpio_i[39:32]),
.dio_p ({adc_serpar, // 39
adc_first_data, // 38
adc_reset, // 37
adc_stby, // 36
adc_range, // 35
adc_os})); // 34:32
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.ad7606_spi_sdo (ad7606_spi_sdo),
.ad7606_spi_sdi (ad7606_spi_sdi),
.ad7606_spi_cs (ad7606_spi_cs),
.ad7606_spi_sclk (ad7606_spi_sclk),
.rx_busy (adc_busy),
.rx_cnvst_n (adc_cnvst_n));
endmodule