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avl_dacfifo: Control the avl_burstcount inside the FSM

main
Istvan Csomortani 2017-12-14 10:59:46 +00:00
parent b8e8410cbc
commit 60d2fb939d
1 changed files with 4 additions and 13 deletions
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17
library/altera/avl_dacfifo/avl_dacfifo_rd.v
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@ -194,6 +194,7 @@ module avl_dacfifo_rd #(
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_read_state <= IDLE;
avl_burstcount <= AVL_BURST_LENGTH;
end else begin
case (avl_read_state)
IDLE : begin
@ -208,8 +209,10 @@ module avl_dacfifo_rd #(
if (avl_mem_request_data == 1'b1) begin
if (avl_address + AVL_ARINCR <= avl_last_address) begin
avl_read_state <= XFER_FULL_BURST;
avl_burstcount <= AVL_BURST_LENGTH;
end else begin
avl_read_state <= XFER_PARTIAL_BURST;
avl_burstcount <= avl_last_burstcount;
end
end
end else begin
@ -280,7 +283,7 @@ module avl_dacfifo_rd #(
end
end
// Avalon burstcount
// Avalon burstcounter
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
@ -294,18 +297,6 @@ module avl_dacfifo_rd #(
end
end
always @(posedge avl_clk) begin
if (avl_fifo_reset_s) begin
avl_burstcount <= 'b0;
end else begin
if (avl_read_state == XFER_PARTIAL_BURST) begin
avl_burstcount <= avl_last_burstcount;
end else begin
avl_burstcount <= AVL_BURST_LENGTH;
end
end
end
assign avl_byteenable = {64{1'b1}};
// write data from Avalon interface into the async FIFO