zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

a5soc: removed jtag master control

main
Rejeesh Kutty 2014-07-01 12:27:37 -04:00
parent b6052773b7
commit 60dd14bcdb
5 changed files with 208 additions and 412 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -217,6 +217,9 @@ module axi_hdmi_tx (
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
// signal name changes

2
library/common/up_adc_common.v
View File

@ -204,6 +204,8 @@ module up_adc_common (
wire up_preset_s;
wire up_mmcm_preset_s;
wire up_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_status_s;

431
projects/fmcjesdadc1/a5soc/system_bd.qsys
View File

File diff suppressed because one or more lines are too long

60
projects/fmcjesdadc1/a5soc/system_top.v
View File

@ -248,7 +248,7 @@ module system_top (
// hdmi
output hdmi_out_clk;
output [ 3:0] hdmi_data;
output [ 15:0] hdmi_data;
// lane interface
@ -285,11 +285,8 @@ module system_top (
// internal signals
wire sys_pll_locked_s;
wire spi_csn_s;
wire spi_clk_s;
wire spi_mosi_s;
wire spi_miso_s;
wire spi_mosi;
wire spi_miso;
wire adc0_enable_a_s;
wire [ 31:0] adc0_data_a_s;
wire adc0_enable_b_s;
@ -340,6 +337,34 @@ module system_top (
adc1_data_a_s[15: 0]};
end
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (5),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (10311),
.sld_node_crc_loword (14297),
.sld_node_info (1076736),
.sld_ram_block_type ("AUTO"),
.sld_sample_depth (1024),
.sld_storage_qualifier_gap_record (0),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_in_enabled (0),
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (sys_clk),
.acq_data_in ({ spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio}),
.acq_trigger_in ({spi_csn, spi_clk}));
/*
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (130),
@ -368,6 +393,8 @@ module system_top (
adc0_data_a_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
*/
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
@ -400,14 +427,11 @@ module system_top (
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.sys_clk (sys_clk),
.spi4_csn (spi_csn_s),
.spi4_clk (spi_clk_s),
.spi4_mosi (spi_mosi_s),
.spi4_miso (spi_miso_s),
.spi3_csn (spi_csn),
.spi3_clk (spi_clk),
.spi3_sdio (spi_sdio));
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
// pipe line to fix timing
@ -483,16 +507,16 @@ module system_top (
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_rx_islockedtodata_export (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
.sys_hps_spim0_txd (spi_mosi_s),
.sys_hps_spim0_rxd (spi_miso_s),
.sys_hps_spim0_txd (spi_mosi),
.sys_hps_spim0_rxd (spi_miso),
.sys_hps_spim0_ss_in_n (1'b1),
.sys_hps_spim0_ssi_oe_n (),
.sys_hps_spim0_ss_0_n (spi_csn_s),
.sys_hps_spim0_ss_0_n (spi_csn),
.sys_hps_spim0_ss_1_n (),
.sys_hps_spim0_ss_2_n (),
.sys_hps_spim0_ss_3_n (),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
.sys_hps_spim0_sclk_out_clk (spi_clk_s),
.sys_hps_spim0_sclk_out_clk (spi_clk),
.sys_hps_f2h_stm_hw_events_stm_hwevents ({16'd0, led, push_buttons, dip_switches}),
.hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
.hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),

124
projects/fmcjesdadc1/common/fmcjesdadc1_spi.v
View File

@ -41,22 +41,12 @@
module fmcjesdadc1_spi (
// master clock
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
sys_clk,
// 4-wire spi interface
spi4_csn,
spi4_clk,
spi4_mosi,
spi4_miso,
// 3-wire spi interface
spi3_csn,
spi3_clk,
spi3_sdio);
spi_sdio);
// parameters
@ -67,83 +57,65 @@ module fmcjesdadc1_spi (
localparam FMC27X_AD9129_0 = 8'h82;
localparam FMC27X_AD9129_1 = 8'h83;
// master clock
// 4-wire
input sys_clk;
input spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 4-wire spi interface
// 3-wire
input spi4_csn;
input spi4_clk;
input spi4_mosi;
output spi4_miso;
// 3-wire spi interface
output spi3_csn;
output spi3_clk;
inout spi3_sdio;
inout spi_sdio;
// internal registers
reg spi4_clk_d = 'd0;
reg spi4_csn_d = 'd0;
reg [ 5:0] spi4_clkcnt = 'd0;
reg [ 6:0] spi4_bitcnt = 'd0;
reg [ 7:0] spi4_devid = 'd0;
reg spi4_rwn = 'd0;
reg spi3_enable = 'd0;
reg [ 7:0] spi_devid = 'd0;
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// pass through most of the stuff (no need to change clock or miso or mosi)
// internal signals
assign spi4_miso = spi3_sdio;
assign spi3_csn = spi4_csn;
assign spi3_clk = spi4_clk;
assign spi3_sdio = ((spi4_csn == 1'b0) && (spi3_enable == 1'b1)) ? 1'bz : spi4_mosi;
wire spi_enable_s;
// the spi4 format is a preamble that selects a particular device, so all we need
// to do is collect the first 8 bits, then control the tristate based on the
// device's address and data widths. the details of the spi formats can be found
// in the data sheet of the devices.
// check on rising edge and change on falling edge
always @(posedge sys_clk) begin
spi4_clk_d <= spi4_clk;
spi4_csn_d <= spi4_csn;
if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
spi4_clkcnt <= 6'd0;
assign spi_enable_s = spi_enable & ~spi_csn;
always @(posedge spi_clk or posedge spi_csn) begin
if (spi_csn == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi4_clkcnt <= spi4_clkcnt + 1'b1;
end
if ((spi4_csn == 1'b1) && (spi4_csn_d == 1'b0)) begin
spi4_bitcnt <= 7'd0;
spi4_devid <= 8'd0;
spi4_rwn <= 1'd0;
end else if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
spi4_bitcnt <= spi4_bitcnt + 1'b1;
if (spi4_bitcnt < 8) begin
spi4_devid <= {spi4_devid[6:0], spi4_mosi};
spi_count <= spi_count + 1'b1;
if (spi_count <= 6'd7) begin
spi_devid <= {spi_devid[6:0], spi_mosi};
end
if (spi4_bitcnt == 8) begin
spi4_rwn <= spi4_mosi;
if (spi_count == 6'd8) begin
spi_rd_wr_n <= spi_mosi;
end
end
if (spi4_csn == 1'b0) begin
if ((spi4_devid == FMC27X_CPLD) || (spi4_devid == FMC27X_AD9129_0) ||
(spi4_devid == FMC27X_AD9129_1)) begin
if ((spi4_bitcnt == 16) && (spi4_clkcnt == 8)) begin
spi3_enable <= spi4_rwn;
end
end else if ((spi4_devid == FMC27X_AD9517) || (spi4_devid == FMC27X_AD9250_0) ||
(spi4_devid == FMC27X_AD9250_1)) begin
if ((spi4_bitcnt == 24) && (spi4_clkcnt == 8)) begin
spi3_enable <= spi4_rwn;
end
end
end else begin
spi3_enable <= 1'b0;
end
end
always @(negedge spi_clk or posedge spi_csn) begin
if (spi_csn == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_devid == FMC27X_CPLD)) ||
((spi_count == 6'd16) && (spi_devid == FMC27X_AD9129_0)) ||
((spi_count == 6'd16) && (spi_devid == FMC27X_AD9129_1)) ||
((spi_count == 6'd24) && (spi_devid == FMC27X_AD9517)) ||
((spi_count == 6'd24) && (spi_devid == FMC27X_AD9250_0)) ||
((spi_count == 6'd24) && (spi_devid == FMC27X_AD9250_1))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = spi_sdio;
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
// ***************************************************************************