diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v
index 85995765b..080a39a7e 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx.v
@@ -217,6 +217,9 @@ module axi_hdmi_tx (
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
+ wire vdma_ovf_s;
+ wire vdma_unf_s;
+ wire vdma_tpm_oos_s;
// signal name changes
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index d4e082934..d8bc899c8 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -204,6 +204,8 @@ module up_adc_common (
wire up_preset_s;
wire up_mmcm_preset_s;
wire up_status_s;
+ wire up_status_ovf_s;
+ wire up_status_unf_s;
wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_status_s;
diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys
index c091d12fa..b303ee956 100755
--- a/projects/fmcjesdadc1/a5soc/system_bd.qsys
+++ b/projects/fmcjesdadc1/a5soc/system_bd.qsys
@@ -12,19 +12,11 @@
element $${FILENAME}
{
}
- element sys_uart.avalon_jtag_slave
- {
- datum baseAddress
- {
- value = "83280";
- type = "String";
- }
- }
element axi_ad9250_0
{
datum _sortIndex
{
- value = "13";
+ value = "9";
type = "int";
}
datum sopceditor_expanded
@@ -37,7 +29,7 @@
{
datum _sortIndex
{
- value = "15";
+ value = "11";
type = "int";
}
datum sopceditor_expanded
@@ -50,7 +42,7 @@
{
datum _sortIndex
{
- value = "14";
+ value = "10";
type = "int";
}
datum sopceditor_expanded
@@ -63,7 +55,7 @@
{
datum _sortIndex
{
- value = "16";
+ value = "12";
type = "int";
}
datum sopceditor_expanded
@@ -76,7 +68,7 @@
{
datum _sortIndex
{
- value = "11";
+ value = "7";
type = "int";
}
}
@@ -84,7 +76,7 @@
{
datum _sortIndex
{
- value = "12";
+ value = "8";
type = "int";
}
}
@@ -92,7 +84,7 @@
{
datum baseAddress
{
- value = "83288";
+ value = "83280";
type = "String";
}
}
@@ -120,14 +112,6 @@
type = "String";
}
}
- element sys_hps.f2h_sdram1_data
- {
- datum baseAddress
- {
- value = "0";
- type = "String";
- }
- }
element sys_jesd204b_s1.jesd204_rx_avs
{
datum baseAddress
@@ -168,14 +152,6 @@
type = "String";
}
}
- element axi_dmac_0.s_axi
- {
- datum baseAddress
- {
- value = "49152";
- type = "String";
- }
- }
element axi_ad9250_1.s_axi
{
datum baseAddress
@@ -184,14 +160,6 @@
type = "String";
}
}
- element axi_ad9250_0.s_axi
- {
- datum baseAddress
- {
- value = "65536";
- type = "String";
- }
- }
element axi_dmac_1.s_axi
{
datum baseAddress
@@ -200,6 +168,22 @@
type = "String";
}
}
+ element axi_dmac_0.s_axi
+ {
+ datum baseAddress
+ {
+ value = "49152";
+ type = "String";
+ }
+ }
+ element axi_ad9250_0.s_axi
+ {
+ datum baseAddress
+ {
+ value = "65536";
+ type = "String";
+ }
+ }
element sys_clk
{
datum _sortIndex
@@ -212,7 +196,7 @@
{
datum _sortIndex
{
- value = "8";
+ value = "4";
type = "int";
}
}
@@ -220,7 +204,7 @@
{
datum _sortIndex
{
- value = "9";
+ value = "5";
type = "int";
}
}
@@ -228,7 +212,7 @@
{
datum _sortIndex
{
- value = "10";
+ value = "6";
type = "int";
}
}
@@ -236,7 +220,7 @@
{
datum _sortIndex
{
- value = "4";
+ value = "1";
type = "int";
}
}
@@ -244,7 +228,7 @@
{
datum _sortIndex
{
- value = "5";
+ value = "3";
type = "int";
}
}
@@ -252,7 +236,7 @@
{
datum _sortIndex
{
- value = "6";
+ value = "2";
type = "int";
}
}
@@ -260,7 +244,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "16";
type = "int";
}
datum sopceditor_expanded
@@ -273,7 +257,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "14";
type = "int";
}
datum sopceditor_expanded
@@ -286,7 +270,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "13";
type = "int";
}
datum sopceditor_expanded
@@ -299,7 +283,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "15";
type = "int";
}
datum sopceditor_expanded
@@ -308,38 +292,6 @@
type = "boolean";
}
}
- element sys_jtag_hps_axi
- {
- datum _sortIndex
- {
- value = "1";
- type = "int";
- }
- }
- element sys_jtag_hps_sdram
- {
- datum _sortIndex
- {
- value = "2";
- type = "int";
- }
- }
- element sys_jtag_pl
- {
- datum _sortIndex
- {
- value = "3";
- type = "int";
- }
- }
- element sys_uart
- {
- datum _sortIndex
- {
- value = "7";
- type = "int";
- }
- }
}
]]>
@@ -890,8 +842,8 @@
- Avalon-MM Bidirectional,Avalon-MM Bidirectional
-
+ Avalon-MM Bidirectional
+
@@ -974,8 +926,8 @@
-
-
+
+
@@ -999,7 +951,7 @@
-
+
@@ -1027,32 +979,6 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- INTERACTIVE_ASCII_OUTPUT
-
-
-
-
-
-
-
@@ -1122,19 +1030,6 @@
ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
-
-
-
-
-
-
-
-
-
@@ -1713,66 +1608,13 @@
-
-
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-
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+
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+
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+
+
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diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v
index e0e85a3e2..df4798e76 100755
--- a/projects/fmcjesdadc1/a5soc/system_top.v
+++ b/projects/fmcjesdadc1/a5soc/system_top.v
@@ -248,7 +248,7 @@ module system_top (
// hdmi
output hdmi_out_clk;
- output [ 3:0] hdmi_data;
+ output [ 15:0] hdmi_data;
// lane interface
@@ -285,11 +285,8 @@ module system_top (
// internal signals
- wire sys_pll_locked_s;
- wire spi_csn_s;
- wire spi_clk_s;
- wire spi_mosi_s;
- wire spi_miso_s;
+ wire spi_mosi;
+ wire spi_miso;
wire adc0_enable_a_s;
wire [ 31:0] adc0_data_a_s;
wire adc0_enable_b_s;
@@ -340,6 +337,34 @@ module system_top (
adc1_data_a_s[15: 0]};
end
+ sld_signaltap #(
+ .sld_advanced_trigger_entity ("basic,1,"),
+ .sld_data_bits (5),
+ .sld_data_bit_cntr_bits (8),
+ .sld_enable_advanced_trigger (0),
+ .sld_mem_address_bits (10),
+ .sld_node_crc_bits (32),
+ .sld_node_crc_hiword (10311),
+ .sld_node_crc_loword (14297),
+ .sld_node_info (1076736),
+ .sld_ram_block_type ("AUTO"),
+ .sld_sample_depth (1024),
+ .sld_storage_qualifier_gap_record (0),
+ .sld_storage_qualifier_mode ("OFF"),
+ .sld_trigger_bits (2),
+ .sld_trigger_in_enabled (0),
+ .sld_trigger_level (1),
+ .sld_trigger_level_pipeline (1))
+ i_signaltap (
+ .acq_clk (sys_clk),
+ .acq_data_in ({ spi_csn,
+ spi_clk,
+ spi_mosi,
+ spi_miso,
+ spi_sdio}),
+ .acq_trigger_in ({spi_csn, spi_clk}));
+
+ /*
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (130),
@@ -368,6 +393,8 @@ module system_top (
adc0_data_a_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
+ */
+
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
@@ -400,14 +427,11 @@ module system_top (
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
- .sys_clk (sys_clk),
- .spi4_csn (spi_csn_s),
- .spi4_clk (spi_clk_s),
- .spi4_mosi (spi_mosi_s),
- .spi4_miso (spi_miso_s),
- .spi3_csn (spi_csn),
- .spi3_clk (spi_clk),
- .spi3_sdio (spi_sdio));
+ .spi_csn (spi_csn),
+ .spi_clk (spi_clk),
+ .spi_mosi (spi_mosi),
+ .spi_miso (spi_miso),
+ .spi_sdio (spi_sdio));
// pipe line to fix timing
@@ -483,16 +507,16 @@ module system_top (
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_rx_islockedtodata_export (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
- .sys_hps_spim0_txd (spi_mosi_s),
- .sys_hps_spim0_rxd (spi_miso_s),
+ .sys_hps_spim0_txd (spi_mosi),
+ .sys_hps_spim0_rxd (spi_miso),
.sys_hps_spim0_ss_in_n (1'b1),
.sys_hps_spim0_ssi_oe_n (),
- .sys_hps_spim0_ss_0_n (spi_csn_s),
+ .sys_hps_spim0_ss_0_n (spi_csn),
.sys_hps_spim0_ss_1_n (),
.sys_hps_spim0_ss_2_n (),
.sys_hps_spim0_ss_3_n (),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
- .sys_hps_spim0_sclk_out_clk (spi_clk_s),
+ .sys_hps_spim0_sclk_out_clk (spi_clk),
.sys_hps_f2h_stm_hw_events_stm_hwevents ({16'd0, led, push_buttons, dip_switches}),
.hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
.hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v
index 4000907b8..e283bb663 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v
@@ -41,22 +41,12 @@
module fmcjesdadc1_spi (
- // master clock
+ spi_csn,
+ spi_clk,
+ spi_mosi,
+ spi_miso,
- sys_clk,
-
- // 4-wire spi interface
-
- spi4_csn,
- spi4_clk,
- spi4_mosi,
- spi4_miso,
-
- // 3-wire spi interface
-
- spi3_csn,
- spi3_clk,
- spi3_sdio);
+ spi_sdio);
// parameters
@@ -67,83 +57,65 @@ module fmcjesdadc1_spi (
localparam FMC27X_AD9129_0 = 8'h82;
localparam FMC27X_AD9129_1 = 8'h83;
- // master clock
+ // 4-wire
- input sys_clk;
+ input spi_csn;
+ input spi_clk;
+ input spi_mosi;
+ output spi_miso;
- // 4-wire spi interface
+ // 3-wire
- input spi4_csn;
- input spi4_clk;
- input spi4_mosi;
- output spi4_miso;
-
- // 3-wire spi interface
-
- output spi3_csn;
- output spi3_clk;
- inout spi3_sdio;
+ inout spi_sdio;
// internal registers
- reg spi4_clk_d = 'd0;
- reg spi4_csn_d = 'd0;
- reg [ 5:0] spi4_clkcnt = 'd0;
- reg [ 6:0] spi4_bitcnt = 'd0;
- reg [ 7:0] spi4_devid = 'd0;
- reg spi4_rwn = 'd0;
- reg spi3_enable = 'd0;
+ reg [ 7:0] spi_devid = 'd0;
+ reg [ 5:0] spi_count = 'd0;
+ reg spi_rd_wr_n = 'd0;
+ reg spi_enable = 'd0;
- // pass through most of the stuff (no need to change clock or miso or mosi)
+ // internal signals
- assign spi4_miso = spi3_sdio;
- assign spi3_csn = spi4_csn;
- assign spi3_clk = spi4_clk;
- assign spi3_sdio = ((spi4_csn == 1'b0) && (spi3_enable == 1'b1)) ? 1'bz : spi4_mosi;
+ wire spi_enable_s;
- // the spi4 format is a preamble that selects a particular device, so all we need
- // to do is collect the first 8 bits, then control the tristate based on the
- // device's address and data widths. the details of the spi formats can be found
- // in the data sheet of the devices.
+ // check on rising edge and change on falling edge
- always @(posedge sys_clk) begin
- spi4_clk_d <= spi4_clk;
- spi4_csn_d <= spi4_csn;
- if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
- spi4_clkcnt <= 6'd0;
+ assign spi_enable_s = spi_enable & ~spi_csn;
+
+ always @(posedge spi_clk or posedge spi_csn) begin
+ if (spi_csn == 1'b1) begin
+ spi_count <= 6'd0;
+ spi_rd_wr_n <= 1'd0;
end else begin
- spi4_clkcnt <= spi4_clkcnt + 1'b1;
- end
- if ((spi4_csn == 1'b1) && (spi4_csn_d == 1'b0)) begin
- spi4_bitcnt <= 7'd0;
- spi4_devid <= 8'd0;
- spi4_rwn <= 1'd0;
- end else if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
- spi4_bitcnt <= spi4_bitcnt + 1'b1;
- if (spi4_bitcnt < 8) begin
- spi4_devid <= {spi4_devid[6:0], spi4_mosi};
+ spi_count <= spi_count + 1'b1;
+ if (spi_count <= 6'd7) begin
+ spi_devid <= {spi_devid[6:0], spi_mosi};
end
- if (spi4_bitcnt == 8) begin
- spi4_rwn <= spi4_mosi;
+ if (spi_count == 6'd8) begin
+ spi_rd_wr_n <= spi_mosi;
end
end
- if (spi4_csn == 1'b0) begin
- if ((spi4_devid == FMC27X_CPLD) || (spi4_devid == FMC27X_AD9129_0) ||
- (spi4_devid == FMC27X_AD9129_1)) begin
- if ((spi4_bitcnt == 16) && (spi4_clkcnt == 8)) begin
- spi3_enable <= spi4_rwn;
- end
- end else if ((spi4_devid == FMC27X_AD9517) || (spi4_devid == FMC27X_AD9250_0) ||
- (spi4_devid == FMC27X_AD9250_1)) begin
- if ((spi4_bitcnt == 24) && (spi4_clkcnt == 8)) begin
- spi3_enable <= spi4_rwn;
- end
- end
- end else begin
- spi3_enable <= 1'b0;
- end
end
+ always @(negedge spi_clk or posedge spi_csn) begin
+ if (spi_csn == 1'b1) begin
+ spi_enable <= 1'b0;
+ end else begin
+ if (((spi_count == 6'd16) && (spi_devid == FMC27X_CPLD)) ||
+ ((spi_count == 6'd16) && (spi_devid == FMC27X_AD9129_0)) ||
+ ((spi_count == 6'd16) && (spi_devid == FMC27X_AD9129_1)) ||
+ ((spi_count == 6'd24) && (spi_devid == FMC27X_AD9517)) ||
+ ((spi_count == 6'd24) && (spi_devid == FMC27X_AD9250_0)) ||
+ ((spi_count == 6'd24) && (spi_devid == FMC27X_AD9250_1))) begin
+ spi_enable <= spi_rd_wr_n;
+ end
+ end
+ end
+
+ assign spi_miso = spi_sdio;
+ assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
+
endmodule
// ***************************************************************************