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Merge branch 'dev' into hdl_2015_r1

main
Adrian Costina 2015-05-23 22:59:09 +03:00
parent 598ece4c8d 77eff35d67
commit 60f2894c8b
251 changed files with 9624 additions and 6855 deletions
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28
library/Makefile
View File

@ -11,7 +11,6 @@ all: lib
clean:
make -C axi_ad6676 clean
make -C axi_ad7175 clean
make -C axi_ad9122 clean
make -C axi_ad9144 clean
make -C axi_ad9152 clean
@ -30,6 +29,7 @@ clean:
make -C axi_adcfifo clean
make -C axi_clkgen clean
make -C axi_dmac clean
make -C axi_generic_adc clean
make -C axi_hdmi_rx clean
make -C axi_hdmi_tx clean
make -C axi_i2s_adi clean
@ -38,21 +38,29 @@ clean:
make -C axi_mc_current_monitor clean
make -C axi_mc_speed clean
make -C axi_spdif_tx clean
make -C cn0363/cn0363_dma_sequencer clean
make -C cn0363/cn0363_phase_data_sync clean
make -C controllerperipheralhdladi_pcore clean
make -C util_adcfifo clean
make -C cordic_demod clean
make -C spi_engine/axi_spi_engine clean
make -C spi_engine/spi_engine_execution clean
make -C spi_engine/spi_engine_interconnect clean
make -C spi_engine/spi_engine_offload clean
make -C util_adc_pack clean
make -C util_adcfifo clean
make -C util_axis_fifo clean
make -C util_axis_resize clean
make -C util_bsplit clean
make -C util_ccat clean
make -C util_cpack clean
make -C util_dacfifo clean
make -C util_dac_unpack clean
make -C util_dacfifo clean
make -C util_gmii_to_rgmii clean
make -C util_i2c_mixer clean
make -C util_pmod_adc clean
make -C util_pmod_fmeter clean
make -C util_rfifo clean
make -C util_sigma_delta_spi clean
make -C util_upack clean
make -C util_wfifo clean
@ -62,7 +70,6 @@ clean-all:clean
lib:
-make -C axi_ad6676
-make -C axi_ad7175
-make -C axi_ad9122
-make -C axi_ad9144
-make -C axi_ad9152
@ -81,6 +88,7 @@ lib:
-make -C axi_adcfifo
-make -C axi_clkgen
-make -C axi_dmac
-make -C axi_generic_adc
-make -C axi_hdmi_rx
-make -C axi_hdmi_tx
-make -C axi_i2s_adi
@ -89,21 +97,29 @@ lib:
-make -C axi_mc_current_monitor
-make -C axi_mc_speed
-make -C axi_spdif_tx
-make -C cn0363/cn0363_dma_sequencer
-make -C cn0363/cn0363_phase_data_sync
-make -C controllerperipheralhdladi_pcore
-make -C util_adcfifo
-make -C cordic_demod
-make -C spi_engine/axi_spi_engine
-make -C spi_engine/spi_engine_execution
-make -C spi_engine/spi_engine_interconnect
-make -C spi_engine/spi_engine_offload
-make -C util_adc_pack
-make -C util_adcfifo
-make -C util_axis_fifo
-make -C util_axis_resize
-make -C util_bsplit
-make -C util_ccat
-make -C util_cpack
-make -C util_dacfifo
-make -C util_dac_unpack
-make -C util_dacfifo
-make -C util_gmii_to_rgmii
-make -C util_i2c_mixer
-make -C util_pmod_adc
-make -C util_pmod_fmeter
-make -C util_rfifo
-make -C util_sigma_delta_spi
-make -C util_upack
-make -C util_wfifo

13
library/axi_ad6676/axi_ad6676.v
View File

@ -84,7 +84,6 @@ module axi_ad6676 (
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// rx_clk is (line-rate/40)
@ -259,21 +258,15 @@ module axi_ad6676 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

1
library/axi_ad6676/axi_ad6676_ip.tcl
View File

@ -12,7 +12,6 @@ adi_ip_files axi_ad6676 [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad6676_pnmon.v" \

423
library/axi_ad7175/ad7175_if.v
View File

@ -1,423 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module ad7175_if
(
// Clock and Reset signals
input fpga_clk_i,
input adc_clk_i,
input reset_n_i,
// Conversion control signals
input start_conversion_i,
output [31:0] dma_data_o,
output dma_data_rdy_o,
// Transmit data on request signals
input start_transmission_i,
input [31:0] tx_data_i,
output tx_data_rdy_o,
// Read data on request signals
input start_read_i,
output [31:0] rx_data_o,
output rx_data_rdy_o,
// AD7175 IC control signals
input adc_sdo_i,
output adc_sdi_o,
output adc_cs_o,
output adc_sclk_o,
// ADC status
output reg adc_status_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
// State Machine Registers
reg [10:0] present_state; // Present FSM State
reg [10:0] next_state; // Next FSM State
reg [10:0] present_state_m1; // Used to synchronise FSM States between different clock domains
// SCLK Registers
reg [7:0] sclk_cnt; // Used to count SCLK Ticks
reg [7:0] sclk_demand; // Used to set number of SCLK Ticks
// Transmit Data Registers
reg [47:0] tx_data_reg; // Used to shift data out
reg [47:0] tx_data_reg_switch; // Used to select data that is being sent
reg tx_data_rdy_int; // Used to signal the end of a transmit cycle
// Receive Data Registers
reg [47:0] rx_data_reg; // Used to shift data in
reg [31:0] rx_read_data_reg; // Used to store read data
reg rx_data_rdy_int; // Used to signal the end of a read cycle
// Conversion Data Registers
reg [31:0] dma_rx_data_reg; // Used to store conversion result (STATUS_REG[31:24] + DATA_REG[23:0])
reg dma_rdy_int; // Used to signal the end of a conversion read
// Internal registers used for external ports
reg adc_sdi_o_int; // Used for adc_sdi_o
reg cs_int; // Used for adc_cs_o
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
// ADC Controller State Machine States
parameter ADC_IDLE_STATE = 11'b00000000001; // Waits for Start Conversion / Start Transmission / Start Read
parameter ADC_WAIT_FOR_DATA_STATE = 11'b00000000010; // Waits for adc_sdo_i to go low (signals new data is available)
parameter ADC_PREP_READ_RESULT_STATE = 11'b00000000100; // Prepares data to perform Status + Data Register Read
parameter ADC_READ_RESULT_STATE = 11'b00000001000; // Reads Status + Data Register
parameter ADC_READ_RESULT_DONE_STATE = 11'b00000010000; // Signals completion of Status + Data Register Read
parameter ADC_PREP_SEND_DATA_STATE = 11'b00000100000; // Prepares data to perform Data Transmit
parameter ADC_SEND_DATA_STATE = 11'b00001000000; // Transmit Data
parameter ADC_SEND_DATA_DONE_STATE = 11'b00010000000; // Signals completion of Data Transmission
parameter ADC_PREP_READ_DATA_STATE = 11'b00100000000; // Prepares data to perform Data Read
parameter ADC_READ_DATA_STATE = 11'b01000000000; // Reads Data
parameter ADC_READ_DATA_DONE_STATE = 11'b10000000000; // Signals completion of Data Read
// Number of SCLK Periods required for Status + Data Read
parameter ADC_SCLK_PERIODS = 8'd48;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign adc_sdi_o = adc_sdi_o_int;
assign adc_sclk_o = (((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))&&(sclk_cnt != 8'd0)) ? adc_clk_i : 1'b1;
assign dma_data_o = dma_rx_data_reg;
assign dma_data_rdy_o = dma_rdy_int;
assign adc_cs_o = cs_int;
assign tx_data_rdy_o = tx_data_rdy_int;
assign rx_data_o = rx_read_data_reg;
assign rx_data_rdy_o = rx_data_rdy_int;
// Register States
always @(posedge fpga_clk_i)
begin
if(reset_n_i == 1'b0)
begin
present_state <= ADC_IDLE_STATE;
adc_status_o <= 1'b0;
end
else
begin
present_state <= next_state;
adc_status_o <= 1'b1;
end
end
// State switch logic
always @(posedge fpga_clk_i)
begin
next_state <= present_state;
case(present_state)
ADC_IDLE_STATE:
begin
// If transmit data is required
if(start_transmission_i == 1'b1)
begin
next_state <= ADC_PREP_SEND_DATA_STATE;
end
// If read data is required
else if(start_read_i == 1'b1)
begin
next_state <= ADC_PREP_READ_DATA_STATE;
end
// If start conversion has been requested
else if(start_conversion_i == 1'b1)
begin
next_state <= ADC_WAIT_FOR_DATA_STATE;
end
end
ADC_WAIT_FOR_DATA_STATE:
begin
// If new data is available
if(adc_sdo_i == 1'b0)
begin
next_state <= ADC_PREP_READ_RESULT_STATE;
end
// If transmit data is required
else if(start_transmission_i == 1'b1)
begin
next_state <= ADC_PREP_SEND_DATA_STATE;
end
// If read data is required
else if(start_read_i == 1'b1)
begin
next_state <= ADC_PREP_READ_DATA_STATE;
end
// If transmit data is not required anymore
else if(start_conversion_i == 1'b0)
begin
next_state <= ADC_IDLE_STATE;
end
end
ADC_PREP_READ_RESULT_STATE:
begin
if(present_state_m1 == ADC_PREP_READ_RESULT_STATE)
begin
next_state <= ADC_READ_RESULT_STATE;
end
end
ADC_READ_RESULT_STATE:
begin
// If data has been sent
if(sclk_cnt == 8'd0)
begin
next_state <= ADC_READ_RESULT_DONE_STATE;
end
end
ADC_READ_RESULT_DONE_STATE:
begin
next_state <= ADC_IDLE_STATE;
end
ADC_PREP_SEND_DATA_STATE:
begin
if(present_state_m1 == ADC_PREP_SEND_DATA_STATE)
begin
next_state <= ADC_SEND_DATA_STATE;
end
end
ADC_SEND_DATA_STATE:
begin
// If data has been sent
if(sclk_cnt == 8'd0)
begin
next_state <= ADC_SEND_DATA_DONE_STATE;
end
end
ADC_SEND_DATA_DONE_STATE:
begin
next_state <= ADC_IDLE_STATE;
end
ADC_PREP_READ_DATA_STATE:
begin
if(present_state_m1 == ADC_PREP_READ_DATA_STATE)
begin
next_state <= ADC_READ_DATA_STATE;
end
end
ADC_READ_DATA_STATE:
begin
// If data has been sent
if(sclk_cnt == 8'd0)
begin
next_state <= ADC_READ_DATA_DONE_STATE;
end
end
ADC_READ_DATA_DONE_STATE:
begin
next_state <= ADC_IDLE_STATE;
end
default:
begin
next_state <= ADC_IDLE_STATE;
end
endcase
end
// State output logic
always @(posedge fpga_clk_i)
begin
if(reset_n_i == 1'b0)
begin
dma_rdy_int <= 1'b0;
cs_int <= 1'b1;
tx_data_rdy_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
end
else
begin
case(present_state)
ADC_IDLE_STATE:
begin
dma_rdy_int <= 1'b0;
tx_data_rdy_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
cs_int <= 1'b1;
end
ADC_WAIT_FOR_DATA_STATE:
begin
cs_int <= 1'b0;
end
ADC_PREP_READ_RESULT_STATE:
begin
dma_rdy_int <= 1'b0;
tx_data_reg_switch <= 48'h400044000000;
cs_int <= 1'b0;
end
ADC_READ_RESULT_STATE:
begin
dma_rdy_int <= 1'b0;
cs_int <= 1'b0;
end
ADC_READ_RESULT_DONE_STATE:
begin
// Final data = Status Reg + Data Reg
dma_rx_data_reg <= {rx_data_reg[39:32], rx_data_reg[23:0]};
dma_rdy_int <= 1'b1;
cs_int <= 1'b1;
end
ADC_PREP_SEND_DATA_STATE:
begin
// Maximum 32 bits transmission (that is why I add 16'd0 to the LSB)
tx_data_rdy_int <= 1'b1;
cs_int <= 1'b1;
tx_data_reg_switch <= {tx_data_i, 16'd0};
end
ADC_SEND_DATA_STATE:
begin
tx_data_rdy_int <= 1'b0;
cs_int <= 1'b0;
end
ADC_SEND_DATA_DONE_STATE:
begin
tx_data_rdy_int <= 1'b1;
cs_int <= 1'b1;
end
ADC_PREP_READ_DATA_STATE:
begin
// Maximum 32 bits transmission (that is why I add 16'd0 to the LSB)
cs_int <= 1'b1;
rx_data_rdy_int <= 1'b1;
tx_data_reg_switch <= {2'b01, tx_data_i[29:0], 16'd0};
end
ADC_READ_DATA_STATE:
begin
cs_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
end
ADC_READ_DATA_DONE_STATE:
begin
rx_read_data_reg <= rx_data_reg[31:0];
cs_int <= 1'b1;
rx_data_rdy_int <= 1'b1;
end
default:
begin
tx_data_rdy_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
dma_rdy_int <= 1'b0;
cs_int <= 1'b1;
end
endcase
end
end
// Synchronise States between different clock domains
always @(posedge adc_clk_i)
begin
present_state_m1 <= present_state;
end
// Select size of transfered data according to desired registers (see AD7176_2 Datasheet for details)
always @(posedge fpga_clk_i)
begin
case(tx_data_i[29:24])
6'h00:
begin
sclk_demand <= 8'd16;
end
6'h01, 6'h02, 6'h06, 6'h07, 6'h10, 6'h11, 6'h12, 6'h13, 6'h20, 6'h21, 6'h22, 6'h23, 6'h28, 6'h29, 6'h2a, 6'h2b:
begin
sclk_demand <= 8'd24;
end
6'h03, 6'h04, 6'h30, 6'h31, 6'h32, 6'h33, 6'h38, 6'h39, 6'h3a, 6'h3b:
begin
sclk_demand <= 8'd32;
end
default:
begin
sclk_demand <= 8'd16;
end
endcase
end
// Serial Data In
always @(posedge adc_clk_i)
begin
if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))
begin
sclk_cnt <= sclk_cnt - 8'd1;
rx_data_reg <= {rx_data_reg[46:0], adc_sdo_i};
end
else
begin
if((present_state_m1 == ADC_PREP_SEND_DATA_STATE)||(present_state_m1 == ADC_PREP_READ_DATA_STATE))
begin
sclk_cnt <= sclk_demand;
end
else
begin
sclk_cnt <= ADC_SCLK_PERIODS;
end
if(present_state_m1 == ADC_IDLE_STATE)
begin
rx_data_reg <= 48'd0;
end
end
end
// Serial Data Out
always @(negedge adc_clk_i)
begin
if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))
begin
adc_sdi_o_int <= tx_data_reg[47];
tx_data_reg <= {tx_data_reg[46:0], 1'b0};
end
else
begin
tx_data_reg <= tx_data_reg_switch;
end
end
endmodule

427
library/axi_ad7175/axi_ad7175.v
View File

@ -1,427 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7175 (
// adc interface (clk, data, over-range)
adc_sdo_i,
adc_sdi_o,
adc_cs_o,
adc_sclk_o,
adc_clk_i,
led_clk_o,
// dma interface
adc_clk,
adc_enable_0,
adc_data_0,
adc_enable_1,
adc_data_1,
adc_enable_2,
adc_data_2,
adc_enable_3,
adc_data_3,
adc_valid_o,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
input adc_sdo_i;
output adc_sdi_o;
output adc_cs_o;
output adc_sclk_o;
input adc_clk_i;
output led_clk_o;
// dma interface
output adc_clk;
output adc_enable_0;
output [31:0] adc_data_0;
output adc_enable_1;
output [31:0] adc_data_1;
output adc_enable_2;
output [31:0] adc_data_2;
output adc_enable_3;
output [31:0] adc_data_3;
output adc_valid_o;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
wire adc_valid_s;
reg adc_valid_d1;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
// internal signals
wire adc_status_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:4];
wire up_rack_s[0:4];
wire up_wack_s[0:4];
wire [31:0] adc_data_s;
wire [ 1:0] adc_reg_rw_s;
wire [31:0] adc_reg_address_s;
wire [31:0] adc_reg_data_w_s;
wire [31:0] adc_rx_data_s;
wire adc_rx_data_rdy_s;
wire adc_tx_data_rdy_s;
wire [31:0] adc_gpio_out;
wire clk_div_update_rdy_s;
wire [31:0] phase_data_s;
// signal name changes
assign adc_clk = s_axi_aclk;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid_o = adc_valid_s & ~adc_valid_d1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
adc_valid_d1 <= adc_valid_s;
end
end
// channel
axi_ad7175_channel #(
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data ({8'b0, adc_data_s[23:0]}),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)),
.adc_data_out (adc_data_0),
.adc_valid (),
.adc_enable (adc_enable_0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad7175_channel #(
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (phase_data_s),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)),
.adc_data_out (adc_data_1),
.adc_valid (),
.adc_enable (adc_enable_1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel
axi_ad7175_channel #(
.CHID(3),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data ({8'b0, adc_data_s[23:0]}),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)),
.adc_data_out (adc_data_2),
.adc_valid (),
.adc_enable (adc_enable_2),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
axi_ad7175_channel #(
.CHID(4),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (phase_data_s),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)),
.adc_data_out (adc_data_3),
.adc_valid (adc_valid_s),
.adc_enable (adc_enable_3),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// clock divider
clk_div clk_div_i (
.clk_i(s_axi_aclk),
.reset_n_i(up_rstn),
.new_div_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h40)),
.div_i(adc_reg_data_w_s[31:0]),
.new_phase_inc_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h41)),
.phase_inc_i(adc_reg_data_w_s[31:0]),
.reg_update_rdy_o(clk_div_update_rdy_s),
.clk_o(led_clk_o),
.phase_o(phase_data_s));
// main (device interface)
ad7175_if ad7175_if_i(
.fpga_clk_i(s_axi_aclk),
.adc_clk_i(adc_clk_i),
.reset_n_i(~adc_rst),
.start_conversion_i(adc_gpio_out[0]),
.dma_data_o(adc_data_s),
.dma_data_rdy_o(data_rd_ready_s),
.start_transmission_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] < 8'h39)),
.tx_data_i({adc_reg_address_s[7:0], adc_reg_data_w_s[23:0]}),
.tx_data_rdy_o(adc_tx_data_rdy_s),
.start_read_i(adc_reg_rw_s[0] && (adc_reg_address_s[7:0] < 8'h39)),
.rx_data_o(adc_rx_data_s),
.rx_data_rdy_o(adc_rx_data_rdy_s),
.adc_sdo_i(adc_sdo_i),
.adc_sdi_o(adc_sdi_o),
.adc_cs_o(adc_cs_o),
.adc_sclk_o(adc_sclk_o),
.adc_status_o(adc_status_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_reg_address(adc_reg_address_s),
.adc_reg_data_r(adc_rx_data_s),
.adc_reg_data_w(adc_reg_data_w_s),
.adc_reg_rw(adc_reg_rw_s),
.adc_reg_done(adc_tx_data_rdy_s | adc_rx_data_rdy_s | clk_div_update_rdy_s),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.delay_clk (),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (),
.delay_ack_t (),
.delay_locked (),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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@ -1,174 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad7175_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_valid_in,
// channel interface
adc_data_out,
adc_valid,
adc_enable,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [31:0] adc_data;
input adc_valid_in;
// channel interface
output [31:0] adc_data_out;
output adc_valid;
output adc_enable;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
generate
if (DP_DISABLE == 1) begin
assign adc_valid = adc_valid_in;
assign adc_data_out = {8'b0, adc_data};
end else begin
ad_datafmt #(
.DATA_WIDTH(32),
.DATA_WIDTH_OUT(32))
i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid_in),
.data (adc_data),
.valid_out (adc_valid),
.data_out (adc_data_out),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module clk_div
(
// Clock and Reset signals
input clk_i,
input reset_n_i,
// Clock divider
input new_div_i,
input [31:0] div_i,
input new_phase_inc_i,
input [31:0] phase_inc_i,
// Divided clock output
output reg reg_update_rdy_o,
output clk_o,
output [31:0] phase_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [31:0] div;
reg [31:0] div_cnt;
reg [31:0] phase;
reg [31:0] phase_inc;
reg clk_div;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign clk_o = clk_div;
assign phase_o = phase;
// Register update logic
always @(posedge clk_i)
begin
if(reset_n_i == 1'b0)
begin
div <= 'd0;
phase_inc <= 'd0;
reg_update_rdy_o <= 1'b0;
end
else
begin
if(new_div_i == 1'b1)
begin
div <= div_i;
end
if(new_phase_inc_i == 1'b1)
begin
phase_inc <= phase_inc_i;
end
reg_update_rdy_o <= new_div_i | new_phase_inc_i;
end
end
// Clock division logic
always @(posedge clk_i)
begin
if(reset_n_i == 1'b0)
begin
clk_div <= 'd1;
phase <= 'd0;
end
else
begin
if(div_cnt < div)
begin
div_cnt <= div_cnt + 'd1;
end
else
begin
div_cnt <= 'd1;
//clk_div <= ~clk_div;
end
phase <= phase + phase_inc;
clk_div <= phase[31];
end
end
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_adc_common (
// clock reset
mmcm_rst,
// adc interface
adc_clk,
adc_rst,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode,
adc_status,
adc_sync_status,
adc_status_ovf,
adc_status_unf,
adc_clk_ratio,
adc_start_code,
adc_sync,
adc_reg_address,
adc_reg_data_r,
adc_reg_data_w,
adc_reg_rw,
adc_reg_done,
// channel interface
up_status_pn_err,
up_status_pn_oos,
up_status_or,
// delay interface
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
// user channel control
up_usr_chanmax,
adc_usr_chanmax,
up_adc_gpio_in,
up_adc_gpio_out,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00080062;
parameter PCORE_ID = 0;
// clock reset
output mmcm_rst;
// adc interface
input adc_clk;
output adc_rst;
output adc_r1_mode;
output adc_ddr_edgesel;
output adc_pin_mode;
input adc_status;
input adc_sync_status;
input adc_status_ovf;
input adc_status_unf;
input [31:0] adc_clk_ratio;
output [31:0] adc_start_code;
output adc_sync;
output [31:0] adc_reg_address;
input [31:0] adc_reg_data_r;
output [31:0] adc_reg_data_w;
output [ 1:0] adc_reg_rw;
input adc_reg_done;
// channel interface
input up_status_pn_err;
input up_status_pn_oos;
input up_status_or;
// delay interface
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
// user channel control
output [ 7:0] up_usr_chanmax;
input [ 7:0] adc_usr_chanmax;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_delay_sel = 'd0;
reg up_delay_rwn = 'd0;
reg [ 7:0] up_delay_addr = 'd0;
reg [ 4:0] up_delay_wdata = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_adc_gpio_out = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg up_adc_sync = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg [31:0] up_adc_reg_address = 'd0;
reg [31:0] up_adc_reg_data = 'd0;
reg up_adc_reg_write = 'd0;
reg up_adc_reg_read = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_mmcm_preset_s;
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire up_cntrl_xfer_done;
wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_status_s;
wire up_delay_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire up_drp_locked_s;
wire [31:0] up_adc_reg_data_s;
wire up_adc_reg_done_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
assign up_mmcm_preset_s = ~up_mmcm_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_delay_sel <= 'd0;
up_delay_rwn <= 'd0;
up_delay_addr <= 'd0;
up_delay_wdata <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_adc_gpio_out <= 'd0;
up_adc_start_code <= 'd0;
up_adc_reg_address <= 'd0;
up_adc_reg_data <= 'd0;
up_adc_reg_read <= 'd0;
up_adc_reg_write <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_adc_sync == 1'b1) begin
if (up_cntrl_xfer_done == 1'b1) begin
up_adc_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sync <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_r1_mode <= up_wdata[2];
up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_adc_reg_address <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_adc_reg_data <= up_wdata;
end
else if((up_adc_reg_done_s == 1'b1) && (up_adc_reg_read == 1'b1))
begin
up_adc_reg_data <= up_adc_reg_data_s;
end
if (up_adc_reg_read == 1'b1) begin
if (up_adc_reg_done_s == 1'b1) begin
up_adc_reg_read <= 1'b0;
end
end else if (up_adc_reg_write == 1'b1) begin
if (up_adc_reg_done_s == 1'b1) begin
up_adc_reg_write <= 1'b0;
end
end
else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_adc_reg_write <= up_wdata[1];
up_adc_reg_read <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
up_delay_sel <= up_wdata[17];
up_delay_rwn <= up_wdata[16];
up_delay_addr <= up_wdata[15:8];
up_delay_wdata <= up_wdata[4:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[2];
end
if (up_status_unf_s == 1'b1) begin
up_status_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h12: up_rdata <= up_adc_reg_address;
8'h13: up_rdata <= up_adc_reg_data;
8'h14: up_rdata <= {30'd0, up_adc_reg_write, up_adc_reg_read};
8'h15: up_rdata <= up_adc_clk_count_s;
8'h16: up_rdata <= adc_clk_ratio;
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata};
8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s};
8'h1a: up_rdata <= {31'd0, up_sync_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h23: up_rdata <= 32'd8;
8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
8'h29: up_rdata <= up_adc_start_code;
8'h2e: up_rdata <= up_adc_gpio_in;
8'h2f: up_rdata <= up_adc_gpio_out;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
ad_rst i_delay_rst_reg (.preset(up_preset_s), .clk(delay_clk), .rst(delay_rst));
ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(70)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_reg_address,
up_adc_reg_data,
up_adc_reg_write,
up_adc_reg_read,
up_adc_sync,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
.up_xfer_done (up_cntrl_xfer_done),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_reg_address,
adc_reg_data_w,
adc_reg_rw[1],
adc_reg_rw[0],
adc_sync,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(37)) i_adc_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_adc_reg_data_s,
up_adc_reg_done_s,
up_sync_status_s,
up_status_s,
up_status_ovf_s,
up_status_unf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_reg_data_r,
adc_reg_done,
adc_sync_status,
adc_status,
adc_status_ovf,
adc_status_unf}));
up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl (up_adc_start_code),
.up_xfer_done (),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl (adc_start_code));
// adc clock monitor
up_clock_mon i_adc_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_adc_clk_count_s),
.d_rst (adc_rst),
.d_clk (adc_clk));
// delay control & status
up_delay_cntrl i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.up_delay_rdata (up_delay_rdata_s),
.up_delay_status (up_delay_status_s),
.up_delay_locked (up_delay_locked_s));
// drp control & status
up_drp_cntrl i_drp_cntrl (
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_drp_sel_t (up_drp_sel_t),
.up_drp_rwn (up_drp_rwn),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_status (up_drp_status_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************

1
library/axi_ad9122/axi_ad9122.v
View File

@ -99,7 +99,6 @@ module axi_ad9122 (
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// dac interface

4
library/axi_ad9144/axi_ad9144.v
View File

@ -71,6 +71,7 @@ module axi_ad9144 (
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
@ -81,6 +82,7 @@ module axi_ad9144 (
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
@ -123,6 +125,7 @@ module axi_ad9144 (
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
@ -133,6 +136,7 @@ module axi_ad9144 (
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;

52
library/axi_ad9144/axi_ad9144_hw.tcl
View File

@ -2,11 +2,13 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9144
set_module_property DESCRIPTION "AXI AD9144 Interface"
set_module_property VERSION 1.0
set_module_property DISPLAY_NAME axi_ad9144
set_module_property ELABORATION_CALLBACK p_axi_ad9144
# files
@ -81,32 +83,36 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
add_interface xcvr_clk clock end
add_interface_port xcvr_clk tx_clk clk Input 1
add_interface if_tx_clk clock end
add_interface_port if_tx_clk tx_clk clk Input 1
add_interface xcvr_data conduit end
set_interface_property xcvr_data associatedClock xcvr_clk
add_interface_port xcvr_data tx_data data Output 128*(PCORE_QUAD_DUAL_N+1)
add_interface if_tx_data avalon_streaming start
add_interface_port if_tx_data tx_data data Output 128*(PCORE_QUAD_DUAL_N+1)
# dma interface
add_interface dac_clock clock start
add_interface_port dac_clock dac_clk clk Output 1
ad_alt_intf clock dac_clk output 1
ad_alt_intf signal dac_valid_0 output 1
ad_alt_intf signal dac_enable_0 output 1
ad_alt_intf signal dac_ddata_0 input 64
ad_alt_intf signal dac_valid_1 output 1
ad_alt_intf signal dac_enable_1 output 1
ad_alt_intf signal dac_ddata_1 input 64
ad_alt_intf signal dac_dovf input 1
ad_alt_intf signal dac_dunf input 1
add_interface dac_dma_if conduit start
set_interface_property dac_dma_if associatedClock dac_clock
add_interface_port dac_dma_if dac_valid_0 dac_valid_0 Output 1
add_interface_port dac_dma_if dac_enable_0 dac_enable_0 Output 1
add_interface_port dac_dma_if dac_data_0 dac_data_0 Input 64
add_interface_port dac_dma_if dac_valid_1 dac_valid_1 Output 1
add_interface_port dac_dma_if dac_enable_1 dac_enable_1 Output 1
add_interface_port dac_dma_if dac_data_1 dac_data_1 Input 64
add_interface_port dac_dma_if dac_valid_2 dac_valid_2 Output 1
add_interface_port dac_dma_if dac_enable_2 dac_enable_2 Output 1
add_interface_port dac_dma_if dac_data_2 dac_data_2 Input 64
add_interface_port dac_dma_if dac_valid_3 dac_valid_3 Output 1
add_interface_port dac_dma_if dac_enable_3 dac_enable_3 Output 1
add_interface_port dac_dma_if dac_data_3 dac_data_3 Input 64
add_interface_port dac_dma_if dac_dovf dac_dovf Input 1
add_interface_port dac_dma_if dac_dunf dac_dunf Input 1
proc p_axi_ad9144 {} {
set p_pcore_quad_dual_n [get_parameter_value "PCORE_QUAD_DUAL_N"]
set_interface_property if_tx_data associatedClock if_tx_clk
set_interface_property if_tx_data dataBitsPerSymbol [expr (128*($p_pcore_quad_dual_n+1))]
if {[get_parameter_value PCORE_QUAD_DUAL_N] == 1} {
ad_alt_intf signal dac_valid_2 output 1
ad_alt_intf signal dac_enable_2 output 1
ad_alt_intf signal dac_ddata_2 input 64
ad_alt_intf signal dac_valid_3 output 1
ad_alt_intf signal dac_enable_3 output 1
ad_alt_intf signal dac_ddata_3 input 64
}
}

1
library/axi_ad9152/axi_ad9152.v
View File

@ -85,7 +85,6 @@ module axi_ad9152 (
parameter PCORE_ID = 0;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// tx_clk is (line-rate/40)

13
library/axi_ad9234/axi_ad9234.v
View File

@ -84,7 +84,6 @@ module axi_ad9234 (
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// rx_clk is (line-rate/40)
@ -259,21 +258,15 @@ module axi_ad9234 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd40),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

2
library/axi_ad9234/axi_ad9234_ip.tcl
View File

@ -7,13 +7,11 @@ adi_ip_create axi_ad9234
adi_ip_files axi_ad9234 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9234_pnmon.v" \

13
library/axi_ad9250/axi_ad9250.v
View File

@ -84,7 +84,6 @@ module axi_ad9250 (
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// rx_clk is (line-rate/40)
@ -259,21 +258,15 @@ module axi_ad9250 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

3
library/axi_ad9250/axi_ad9250_alt.v
View File

@ -172,8 +172,7 @@ module axi_ad9250_alt (
axi_ad9250 #(
.PCORE_ID (PCORE_ID),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff))
.PCORE_IODELAY_GROUP ("adc_if_delay_group"))
i_ad9250 (
.rx_clk (rx_clk),
.rx_data (rx_data),

1
library/axi_ad9250/axi_ad9250_ip.tcl
View File

@ -13,7 +13,6 @@ adi_ip_files axi_ad9250 [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9250_pnmon.v" \

70
library/axi_ad9265/axi_ad9265.v
View File

@ -92,7 +92,6 @@ module axi_ad9265 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
@ -153,6 +152,7 @@ module axi_ad9265 (
wire adc_rst;
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
@ -162,18 +162,14 @@ module axi_ad9265 (
wire up_status_pn_oos_s;
wire up_status_or_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [ 8:0] up_dld_s;
wire [44:0] up_dwdata_s;
wire [44:0] up_drdata_s;
wire delay_locked_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
@ -198,9 +194,9 @@ module axi_ad9265 (
up_status_pn_err <= up_status_pn_err_s;
up_status_pn_oos <= up_status_pn_oos_s;
up_status_or <= up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -247,16 +243,34 @@ module axi_ad9265 (
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
@ -267,21 +281,15 @@ module axi_ad9265 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
@ -293,7 +301,7 @@ module axi_ad9265 (
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),

83
library/axi_ad9265/axi_ad9265_if.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
@ -62,14 +60,12 @@ module axi_ad9265_if (
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
@ -96,14 +92,12 @@ module axi_ad9265_if (
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
@ -115,13 +109,9 @@ module axi_ad9265_if (
reg adc_or_n = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or = 'd0;
reg [ 8:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[8:0];
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
@ -136,49 +126,6 @@ module axi_ad9265_if (
adc_data <= { adc_data_p_s[7], adc_data_n_s[7], adc_data_p_s[6], adc_data_n_s[6], adc_data_p_s[5], adc_data_n_s[5], adc_data_p_s[4], adc_data_n_s[4], adc_data_p_s[3], adc_data_n_s[3], adc_data_p_s[2], adc_data_n_s[2], adc_data_p_s[1], adc_data_n_s[1], adc_data_p_s[0], adc_data_n_s[0]};
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h08: delay_ld <= 15'h0100;
8'h07: delay_ld <= 15'h0080;
8'h06: delay_ld <= 15'h0040;
8'h05: delay_ld <= 15'h0020;
8'h04: delay_ld <= 15'h0010;
8'h03: delay_ld <= 15'h0008;
8'h02: delay_ld <= 15'h0004;
8'h01: delay_ld <= 15'h0002;
8'h00: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h08: delay_rdata <= delay_rdata_s[8];
8'h07: delay_rdata <= delay_rdata_s[7];
8'h06: delay_rdata <= delay_rdata_s[6];
8'h05: delay_rdata <= delay_rdata_s[5];
8'h04: delay_rdata <= delay_rdata_s[4];
8'h03: delay_rdata <= delay_rdata_s[3];
8'h02: delay_rdata <= delay_rdata_s[2];
8'h01: delay_rdata <= delay_rdata_s[1];
8'h00: delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
@ -193,11 +140,12 @@ module axi_ad9265_if (
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
@ -214,11 +162,12 @@ module axi_ad9265_if (
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[8]),
.up_dwdata (up_dwdata[44:40]),
.up_drdata (up_drdata[44:40]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[8]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[8]),
.delay_locked (delay_locked));
// clock

1
library/axi_ad9361/Makefile
View File

@ -20,6 +20,7 @@ M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_addsub.v
M_DEPS += ../common/ad_tdd_control.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v

61
library/axi_ad9361/axi_ad9361.v
View File

@ -143,19 +143,16 @@ module axi_ad9361 (
// chipscope signals
dev_dbg_data,
dev_l_dbg_data,
tdd_dbg);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_DAC_IODELAY_ENABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// physical interface (receive)
@ -259,9 +256,6 @@ module axi_ad9361 (
// chipscope signals
output [111:0] dev_dbg_data;
output [ 61:0] dev_l_dbg_data;
output [34:0] tdd_dbg;
// internal registers
@ -285,12 +279,12 @@ module axi_ad9361 (
wire adc_status_s;
wire dac_valid_s;
wire [47:0] dac_data_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [ 6:0] up_adc_dld_s;
wire [34:0] up_adc_dwdata_s;
wire [34:0] up_adc_drdata_s;
wire [ 7:0] up_dac_dld_s;
wire [39:0] up_dac_dwdata_s;
wire [39:0] up_dac_drdata_s;
wire delay_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
@ -312,9 +306,7 @@ module axi_ad9361 (
wire tdd_tx_vco_en_s;
wire tdd_rx_rf_en_s;
wire tdd_tx_rf_en_s;
wire [ 7:0] ad9361_tdd_status_s;
wire enable;
wire txnrx;
wire [ 7:0] tdd_status_s;
wire dac_valid_i0_s;
wire dac_valid_q0_s;
@ -346,6 +338,7 @@ module axi_ad9361 (
axi_ad9361_dev_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_DAC_IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_dev_if (
.rx_clk_in_p (rx_clk_in_p),
@ -371,17 +364,16 @@ module axi_ad9361 (
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
.dac_r1_mode (dac_r1_mode),
.up_clk (up_clk),
.up_adc_dld (up_adc_dld_s),
.up_adc_dwdata (up_adc_dwdata_s),
.up_adc_drdata (up_adc_drdata_s),
.up_dac_dld (up_dac_dld_s),
.up_dac_dwdata (up_dac_dwdata_s),
.up_dac_drdata (up_dac_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.dev_dbg_data (dev_dbg_data),
.dev_l_dbg_data (dev_l_dbg_data));
.delay_locked (delay_locked_s));
// TDD interface
@ -394,7 +386,7 @@ module axi_ad9361 (
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.ad9361_txnrx(txnrx),
.ad9361_enable(enable),
.ad9361_tdd_status(ad9361_tdd_status_s)
.ad9361_tdd_status(tdd_status_s)
);
// TDD control
@ -408,7 +400,7 @@ module axi_ad9361 (
.tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s),
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.tdd_status(ad9361_tdd_status_s),
.tdd_status(tdd_status_s),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq_s),
@ -436,14 +428,11 @@ module axi_ad9361 (
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.dac_data (dac_data_s),
.up_dld (up_adc_dld_s),
.up_dwdata (up_adc_dwdata_s),
.up_drdata (up_adc_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.adc_enable_i0 (adc_enable_i0),
.adc_valid_i0 (adc_valid_i0),
@ -483,6 +472,12 @@ module axi_ad9361 (
.dac_data (dac_data_s),
.dac_r1_mode (dac_r1_mode),
.adc_data (adc_data_s),
.up_dld (up_dac_dld_s),
.up_dwdata (up_dac_dwdata_s),
.up_drdata (up_dac_drdata_s),
.delay_clk (delay_clk),
.delay_rst (),
.delay_locked (delay_locked_s),
.dac_sync_in (dac_sync_in),
.dac_sync_out (dac_sync_out),
.dac_enable_i0 (dac_enable_i0),

170
library/axi_ad9361/axi_ad9361_dev_if.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
@ -81,26 +79,23 @@ module axi_ad9361_dev_if (
dac_data,
dac_r1_mode,
// delay control signals
// delay interface
up_clk,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// chipscope signals
dev_dbg_data,
dev_l_dbg_data);
delay_locked);
// this parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_DAC_IODELAY_ENABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
localparam PCORE_7SERIES = 0;
localparam PCORE_VIRTEX6 = 1;
@ -143,23 +138,19 @@ module axi_ad9361_dev_if (
input [47:0] dac_data;
input dac_r1_mode;
// delay control signals
// delay interface
input up_clk;
input [ 6:0] up_adc_dld;
input [34:0] up_adc_dwdata;
output [34:0] up_adc_drdata;
input [ 7:0] up_dac_dld;
input [39:0] up_dac_dwdata;
output [39:0] up_dac_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// chipscope signals
output [111:0] dev_dbg_data;
output [ 61:0] dev_l_dbg_data;
// internal registers
reg [ 5:0] rx_data_p = 0;
@ -200,16 +191,12 @@ module axi_ad9361_dev_if (
reg tx_p_frame = 'd0;
reg [ 5:0] tx_p_data_p = 'd0;
reg [ 5:0] tx_p_data_n = 'd0;
reg [ 6:0] delay_ld = 'd0;
reg [ 4:0] delay_rdata = 'd0;
reg delay_ack_t = 'd0;
// internal signals
wire rx_align_s;
wire [ 3:0] rx_frame_s;
wire [ 3:0] tx_data_sel_s;
wire [ 4:0] delay_rdata_s[6:0];
wire [ 5:0] rx_data_p_s;
wire [ 5:0] rx_data_n_s;
wire rx_frame_p_s;
@ -217,32 +204,6 @@ module axi_ad9361_dev_if (
genvar l_inst;
// device debug signals
assign dev_dbg_data[ 5: 0] = tx_data_n;
assign dev_dbg_data[ 11: 6] = tx_data_p;
assign dev_dbg_data[ 23: 12] = dac_data[11: 0];
assign dev_dbg_data[ 35: 24] = dac_data[23:12];
assign dev_dbg_data[ 47: 36] = dac_data[35:24];
assign dev_dbg_data[ 59: 48] = dac_data[47:36];
assign dev_dbg_data[ 71: 60] = adc_data[11: 0];
assign dev_dbg_data[ 83: 72] = adc_data[23:12];
assign dev_dbg_data[ 95: 84] = adc_data[35:24];
assign dev_dbg_data[107: 96] = adc_data[47:36];
assign dev_dbg_data[108:108] = tx_frame;
assign dev_dbg_data[109:109] = dac_valid;
assign dev_dbg_data[110:110] = adc_status;
assign dev_dbg_data[111:111] = adc_valid;
assign dev_l_dbg_data[ 5: 0] = tx_p_data_n;
assign dev_l_dbg_data[ 11: 6] = tx_p_data_p;
assign dev_l_dbg_data[ 23: 12] = adc_p_data[11: 0];
assign dev_l_dbg_data[ 35: 24] = adc_p_data[23:12];
assign dev_l_dbg_data[ 47: 36] = adc_p_data[35:24];
assign dev_l_dbg_data[ 59: 48] = adc_p_data[47:36];
assign dev_l_dbg_data[ 60: 60] = tx_p_frame;
assign dev_l_dbg_data[ 61: 61] = adc_p_valid;
// receive data path interface
assign rx_align_s = rx_frame_n_s ^ rx_frame_p_s;
@ -411,45 +372,6 @@ module axi_ad9361_dev_if (
tx_p_data_n <= tx_n_data_n;
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h06: delay_ld <= 7'h40;
8'h05: delay_ld <= 7'h20;
8'h04: delay_ld <= 7'h10;
8'h03: delay_ld <= 7'h08;
8'h02: delay_ld <= 7'h04;
8'h01: delay_ld <= 7'h02;
8'h00: delay_ld <= 7'h01;
default: delay_ld <= 7'h00;
endcase
end else begin
delay_ld <= 7'h00;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h06: delay_rdata <= delay_rdata_s[6];
8'h05: delay_rdata <= delay_rdata_s[5];
8'h04: delay_rdata <= delay_rdata_s[4];
8'h03: delay_rdata <= delay_rdata_s[3];
8'h02: delay_rdata <= delay_rdata_s[2];
8'h01: delay_rdata <= delay_rdata_s[1];
8'h00: delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// receive data interface, ibuf -> idelay -> iddr
generate
@ -464,11 +386,12 @@ module axi_ad9361_dev_if (
.rx_data_in_n (rx_data_in_n[l_inst]),
.rx_data_p (rx_data_p_s[l_inst]),
.rx_data_n (rx_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
@ -485,11 +408,12 @@ module axi_ad9361_dev_if (
.rx_data_in_n (rx_frame_in_n),
.rx_data_p (rx_frame_p_s),
.rx_data_n (rx_frame_n_s),
.up_clk (up_clk),
.up_dld (up_adc_dld[6]),
.up_dwdata (up_adc_dwdata[34:30]),
.up_drdata (up_adc_drdata[34:30]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[6]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[6]),
.delay_locked (delay_locked));
// transmit data interface, oddr -> obuf
@ -497,37 +421,67 @@ module axi_ad9361_dev_if (
generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
ad_lvds_out #(
.BUFTYPE (PCORE_DEVICE_TYPE))
.BUFTYPE (PCORE_DEVICE_TYPE),
.IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]),
.tx_data_n (tx_p_data_n[l_inst]),
.tx_data_out_p (tx_data_out_p[l_inst]),
.tx_data_out_n (tx_data_out_n[l_inst]));
.tx_data_out_n (tx_data_out_n[l_inst]),
.up_clk (up_clk),
.up_dld (up_dac_dld[l_inst]),
.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// transmit frame interface, oddr -> obuf
ad_lvds_out #(
.BUFTYPE (PCORE_DEVICE_TYPE))
.BUFTYPE (PCORE_DEVICE_TYPE),
.IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_p_frame),
.tx_data_n (tx_p_frame),
.tx_data_out_p (tx_frame_out_p),
.tx_data_out_n (tx_frame_out_n));
.tx_data_out_n (tx_frame_out_n),
.up_clk (up_clk),
.up_dld (up_dac_dld[6]),
.up_dwdata (up_dac_dwdata[34:30]),
.up_drdata (up_dac_drdata[34:30]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// transmit clock interface, oddr -> obuf
ad_lvds_out #(
.BUFTYPE (PCORE_DEVICE_TYPE))
.BUFTYPE (PCORE_DEVICE_TYPE),
.IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (1'b0),
.tx_data_n (1'b1),
.tx_data_out_p (tx_clk_out_p),
.tx_data_out_n (tx_clk_out_n));
.tx_data_out_n (tx_clk_out_n),
.up_clk (up_clk),
.up_dld (up_dac_dld[7]),
.up_dwdata (up_dac_dwdata[39:35]),
.up_drdata (up_dac_drdata[39:35]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// device clock interface (receive clock)

49
library/axi_ad9361/axi_ad9361_dev_if_alt.v
View File

@ -81,26 +81,23 @@ module axi_ad9361_dev_if (
dac_data,
dac_r1_mode,
// delay control signals
// delay interface
up_clk,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// chipscope signals
dev_dbg_data,
dev_l_dbg_data);
delay_locked);
// this parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_DAC_IODELAY_ENABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
localparam PCORE_7SERIES = 0;
localparam PCORE_VIRTEX6 = 1;
@ -143,23 +140,19 @@ module axi_ad9361_dev_if (
input [47:0] dac_data;
input dac_r1_mode;
// delay control signals
// delay interface
input up_clk;
input [ 6:0] up_adc_dld;
input [34:0] up_adc_dwdata;
output [34:0] up_adc_drdata;
input [ 7:0] up_dac_dld;
input [39:0] up_dac_dwdata;
output [39:0] up_dac_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// chipscope signals
output [111:0] dev_dbg_data;
output [ 61:0] dev_l_dbg_data;
// internal registers
reg [ 3:0] rx_frame = 'd0;
@ -194,11 +187,9 @@ module axi_ad9361_dev_if (
// defaults
assign delay_rdata = 5'd0;
assign delay_ack_t = 1'd0;
assign up_drdata = 5'd0;
assign up_dack = up_dsel;
assign delay_locked = 1'd1;
assign dev_dbg_data = 112'd0;
assign dev_l_dbg_data = 62'd0;
// receive data path interface

66
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -55,14 +55,11 @@ module axi_ad9361_rx (
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// dma interface
@ -118,14 +115,11 @@ module axi_ad9361_rx (
// delay interface
output [ 6:0] up_dld;
output [34:0] up_dwdata;
input [34:0] up_drdata;
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// dma interface
@ -181,9 +175,9 @@ module axi_ad9361_rx (
wire [ 3:0] up_adc_pn_err_s;
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:4];
wire up_rack_s[0:4];
wire up_wack_s[0:4];
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
// processor read interface
@ -199,9 +193,12 @@ module axi_ad9361_rx (
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
end
end
@ -351,20 +348,11 @@ module axi_ad9361_rx (
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code(),
.adc_sync(),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
@ -389,6 +377,26 @@ module axi_ad9361_rx (
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(7), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[5]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5]));
endmodule
// ***************************************************************************

53
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -49,6 +49,15 @@ module axi_ad9361_tx (
dac_r1_mode,
adc_data,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
// master/slave
dac_sync_in,
@ -102,6 +111,15 @@ module axi_ad9361_tx (
output dac_r1_mode;
input [47:0] adc_data;
// delay interface
output [ 7:0] up_dld;
output [39:0] up_dwdata;
input [39:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
// master/slave
input dac_sync_in;
@ -165,9 +183,9 @@ module axi_ad9361_tx (
wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s;
wire [47:0] dac_data_int_s;
wire [31:0] up_rdata_s[0:4];
wire up_rack_s[0:4];
wire up_wack_s[0:4];
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
// master/slave
@ -205,9 +223,12 @@ module axi_ad9361_tx (
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
end
end
@ -368,6 +389,26 @@ module axi_ad9361_tx (
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// dac delay control
up_delay_cntrl #(.IO_WIDTH(8), .IO_BASEADDR(6'h12)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[5]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5]));
endmodule
// ***************************************************************************

41
library/axi_ad9434/axi_ad9434.v
View File

@ -89,7 +89,6 @@ module axi_ad9434 (
parameter PCORE_ID = 0;
parameter PCORE_DEVTYPE = SERIES7;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// physical interface
input adc_clk_in_p;
@ -153,15 +152,14 @@ module axi_ad9434 (
wire [ 1:0] up_status_or_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [12:0] up_dld_s;
wire [64:0] up_dwdata_s;
wire [64:0] up_drdata_s;
wire delay_clk_s;
wire delay_rst;
wire delay_locked_s;
wire drp_sel_s;
wire drp_rst_s;
wire drp_wr_s;
@ -197,15 +195,13 @@ module axi_ad9434 (
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_status(adc_status_s),
.delay_clk(delay_clk),
.delay_rst(delay_rst_s),
.delay_sel(delay_sel_s),
.delay_rwn(delay_rwn_s),
.delay_addr(delay_addr_s),
.delay_wdata(delay_wdata_s),
.delay_rdata(delay_rdata_s),
.delay_ack_t(delay_ack_t_s),
.delay_locked(delay_locked_s),
.up_clk (up_clk),
.up_adc_dld (up_dld_s),
.up_adc_dwdata (up_dwdata_s),
.up_adc_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.mmcm_rst(mmcm_rst),
.drp_clk(drp_clk),
.drp_rst(drp_rst_s),
@ -229,14 +225,11 @@ module axi_ad9434 (
.dma_dvalid (adc_valid),
.dma_data (adc_data),
.dma_dovf (adc_dovf),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.drp_clk (drp_clk),
.drp_rst (drp_rst_s),

67
library/axi_ad9434/axi_ad9434_core.v
View File

@ -68,14 +68,11 @@ module axi_ad9434_core (
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// processor interface
@ -122,14 +119,11 @@ module axi_ad9434_core (
input drp_locked;
// delay interface
output [12:0] up_dld;
output [64:0] up_dwdata;
input [64:0] up_drdata;
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// processor interface
@ -166,9 +160,9 @@ module axi_ad9434_core (
wire adc_pn_err_s;
wire adc_pn_oos_s;
wire up_wack_s[0:1];
wire [31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:2];
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
// instantiations
axi_ad9434_pnmon i_pnmon (
@ -203,9 +197,9 @@ module axi_ad9434_core (
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rdata_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_rdata_s[2];
end
end
@ -213,27 +207,24 @@ module axi_ad9434_core (
.PCORE_ID(PCORE_ID))
i_adc_common(
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status),
.adc_sync_status (1'd0),
.adc_status_ovf (dma_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd4),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
@ -243,10 +234,12 @@ module axi_ad9434_core (
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
@ -306,4 +299,24 @@ module axi_ad9434_core (
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(13), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
endmodule

93
library/axi_ad9434/axi_ad9434_if.v
View File

@ -60,14 +60,12 @@ module axi_ad9434_if (
adc_status,
// delay interface (for IDELAY macros)
up_clk,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// mmcm reset
@ -110,15 +108,14 @@ module axi_ad9434_if (
input adc_rst;
output adc_status;
// delay control signals
// delay interface
input up_clk;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// mmcm reset
@ -135,17 +132,12 @@ module axi_ad9434_if (
output drp_ready;
output drp_locked;
// output registers
reg [ 4:0] delay_rdata = 'b0;
reg delay_ack_t = 'b0;
// internal registers
reg [12:0] delay_ld = 'd0;
reg adc_status = 'd0;
reg adc_status_m1 = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[12:0];
wire [3:0] adc_or_s;
@ -157,55 +149,6 @@ module axi_ad9434_if (
// output assignment for adc clock (1:4 of the sampling clock)
assign adc_clk = adc_div_clk;
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'd12 : delay_ld <= 13'h1000;
8'd11 : delay_ld <= 13'h0800;
8'd10 : delay_ld <= 13'h0400;
8'd9 : delay_ld <= 13'h0200;
8'd8 : delay_ld <= 13'h0100;
8'd7 : delay_ld <= 13'h0080;
8'd6 : delay_ld <= 13'h0040;
8'd5 : delay_ld <= 13'h0020;
8'd4 : delay_ld <= 13'h0010;
8'd3 : delay_ld <= 13'h0008;
8'd2 : delay_ld <= 13'h0004;
8'd1 : delay_ld <= 13'h0002;
8'd0 : delay_ld <= 13'h0001;
default : delay_ld <= 13'h0000;
endcase
end else begin
delay_ld <= 13'h000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'd12 : delay_rdata <= delay_rdata_s[12];
8'd11 : delay_rdata <= delay_rdata_s[11];
8'd10 : delay_rdata <= delay_rdata_s[10];
8'd9 : delay_rdata <= delay_rdata_s[9];
8'd8 : delay_rdata <= delay_rdata_s[8];
8'd7 : delay_rdata <= delay_rdata_s[7];
8'd6 : delay_rdata <= delay_rdata_s[6];
8'd5 : delay_rdata <= delay_rdata_s[5];
8'd4 : delay_rdata <= delay_rdata_s[4];
8'd3 : delay_rdata <= delay_rdata_s[3];
8'd2 : delay_rdata <= delay_rdata_s[2];
8'd1 : delay_rdata <= delay_rdata_s[1];
8'd0 : delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
@ -229,11 +172,12 @@ module axi_ad9434_if (
.data_s7(),
.data_in_p(adc_data_in_p[l_inst]),
.data_in_n(adc_data_in_n[l_inst]),
.up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_ld(delay_ld[l_inst]),
.delay_wdata(delay_wdata),
.delay_rdata(delay_rdata_s[l_inst]),
.delay_locked());
end
endgenerate
@ -259,11 +203,12 @@ module axi_ad9434_if (
.data_s7(),
.data_in_p(adc_or_in_p),
.data_in_n(adc_or_in_n),
.up_clk (up_clk),
.up_dld (up_adc_dld[12]),
.up_dwdata (up_adc_dwdata[64:60]),
.up_drdata (up_adc_drdata[64:60]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_ld(delay_ld[12]),
.delay_wdata(delay_wdata),
.delay_rdata(delay_rdata_s[12]),
.delay_locked(delay_locked));
// clock input buffers and MMCM

68
library/axi_ad9467/axi_ad9467.v
View File

@ -90,7 +90,6 @@ module axi_ad9467(
parameter PCORE_ID = 0;
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// physical interface
@ -147,28 +146,25 @@ module axi_ad9467(
wire adc_rst;
wire up_clk;
wire up_rstn;
wire delay_rst;
// internal signals
wire [15:0] adc_data_s;
wire adc_or_s;
wire adc_ddr_edgesel_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [ 8:0] up_dld_s;
wire [44:0] up_dwdata_s;
wire [44:0] up_drdata_s;
wire delay_locked_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
@ -187,9 +183,9 @@ module axi_ad9467(
up_rack <= 1'd0;
up_wack <= 1'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -209,14 +205,12 @@ module axi_ad9467(
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// channel
@ -242,6 +236,26 @@ module axi_ad9467(
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
@ -252,21 +266,15 @@ module axi_ad9467(
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'b1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'b0),
.drp_rst (),
.drp_sel (),

81
library/axi_ad9467/axi_ad9467_if.v
View File

@ -64,14 +64,12 @@ module axi_ad9467_if (
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// buffer type based on the target device.
@ -100,14 +98,12 @@ module axi_ad9467_if (
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
@ -121,13 +117,9 @@ module axi_ad9467_if (
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or = 'd0;
reg [ 8:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[8:0];
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
@ -168,49 +160,6 @@ module axi_ad9467_if (
end
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'd8 : delay_ld <= 9'h100;
8'd7 : delay_ld <= 9'h080;
8'd6 : delay_ld <= 9'h040;
8'd5 : delay_ld <= 9'h020;
8'd4 : delay_ld <= 9'h010;
8'd3 : delay_ld <= 9'h008;
8'd2 : delay_ld <= 9'h004;
8'd1 : delay_ld <= 9'h002;
8'd0 : delay_ld <= 9'h001;
default: delay_ld <= 9'h000;
endcase
end else begin
delay_ld <= 9'h000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'd8 : delay_rdata <= delay_rdata_s[8];
8'd7 : delay_rdata <= delay_rdata_s[7];
8'd6 : delay_rdata <= delay_rdata_s[6];
8'd5 : delay_rdata <= delay_rdata_s[5];
8'd4 : delay_rdata <= delay_rdata_s[4];
8'd3 : delay_rdata <= delay_rdata_s[3];
8'd2 : delay_rdata <= delay_rdata_s[2];
8'd1 : delay_rdata <= delay_rdata_s[1];
8'd0 : delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
@ -225,11 +174,12 @@ module axi_ad9467_if (
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
@ -246,11 +196,12 @@ module axi_ad9467_if (
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[8]),
.up_dwdata (up_dwdata[44:40]),
.up_drdata (up_drdata[44:40]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[8]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[8]),
.delay_locked (delay_locked));
// clock

13
library/axi_ad9625/axi_ad9625.v
View File

@ -84,7 +84,6 @@ module axi_ad9625 (
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// rx_clk is (line-rate/40)
@ -223,21 +222,15 @@ module axi_ad9625 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_adc_pn_err_s),
.up_status_pn_oos (up_adc_pn_oos_s),
.up_status_or (up_adc_or_s),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

1
library/axi_ad9625/axi_ad9625_ip.tcl
View File

@ -14,7 +14,6 @@ adi_ip_files axi_ad9625 [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9625_pnmon.v" \

70
library/axi_ad9643/axi_ad9643.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -97,7 +95,6 @@ module axi_ad9643 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
@ -163,6 +160,7 @@ module axi_ad9643 (
wire adc_rst;
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
@ -180,17 +178,13 @@ module axi_ad9643 (
wire adc_ddr_edgesel_s;
wire adc_pin_mode_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [14:0] up_dld_s;
wire [74:0] up_dwdata_s;
wire [74:0] up_drdata_s;
wire delay_locked_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire [31:0] up_rdata_s[0:3];
wire up_rack_s[0:3];
wire up_wack_s[0:3];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
@ -221,9 +215,9 @@ module axi_ad9643 (
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
@ -305,14 +299,12 @@ module axi_ad9643 (
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// common processor control
@ -325,21 +317,15 @@ module axi_ad9643 (
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
@ -364,6 +350,26 @@ module axi_ad9643 (
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(15), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// up bus interface
up_axi i_up_axi (

93
library/axi_ad9643/axi_ad9643_if.v
View File

@ -69,14 +69,12 @@ module axi_ad9643_if (
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
@ -109,14 +107,12 @@ module axi_ad9643_if (
// delay control signals
input up_clk;
input [14:0] up_dld;
input [74:0] up_dwdata;
output [74:0] up_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
@ -136,13 +132,9 @@ module axi_ad9643_if (
reg [13:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
reg [14:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[14:0];
wire [13:0] adc_data_p_s;
wire [13:0] adc_data_n_s;
wire adc_or_p_s;
@ -204,61 +196,6 @@ module axi_ad9643_if (
end
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h0e: delay_ld <= 15'h4000;
8'h0d: delay_ld <= 15'h2000;
8'h0c: delay_ld <= 15'h1000;
8'h0b: delay_ld <= 15'h0800;
8'h0a: delay_ld <= 15'h0400;
8'h09: delay_ld <= 15'h0200;
8'h08: delay_ld <= 15'h0100;
8'h07: delay_ld <= 15'h0080;
8'h06: delay_ld <= 15'h0040;
8'h05: delay_ld <= 15'h0020;
8'h04: delay_ld <= 15'h0010;
8'h03: delay_ld <= 15'h0008;
8'h02: delay_ld <= 15'h0004;
8'h01: delay_ld <= 15'h0002;
8'h00: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h0e: delay_rdata <= delay_rdata_s[14];
8'h0d: delay_rdata <= delay_rdata_s[13];
8'h0c: delay_rdata <= delay_rdata_s[12];
8'h0b: delay_rdata <= delay_rdata_s[11];
8'h0a: delay_rdata <= delay_rdata_s[10];
8'h09: delay_rdata <= delay_rdata_s[ 9];
8'h08: delay_rdata <= delay_rdata_s[ 8];
8'h07: delay_rdata <= delay_rdata_s[ 7];
8'h06: delay_rdata <= delay_rdata_s[ 6];
8'h05: delay_rdata <= delay_rdata_s[ 5];
8'h04: delay_rdata <= delay_rdata_s[ 4];
8'h03: delay_rdata <= delay_rdata_s[ 3];
8'h02: delay_rdata <= delay_rdata_s[ 2];
8'h01: delay_rdata <= delay_rdata_s[ 1];
8'h00: delay_rdata <= delay_rdata_s[ 0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
@ -273,11 +210,12 @@ module axi_ad9643_if (
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
@ -294,11 +232,12 @@ module axi_ad9643_if (
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[14]),
.up_dwdata (up_dwdata[74:70]),
.up_drdata (up_drdata[74:70]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[14]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[14]),
.delay_locked (delay_locked));
// clock

70
library/axi_ad9652/axi_ad9652.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -96,7 +94,6 @@ module axi_ad9652 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
@ -161,6 +158,7 @@ module axi_ad9652 (
wire adc_rst;
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
@ -177,17 +175,13 @@ module axi_ad9652 (
wire [ 1:0] up_status_or_s;
wire adc_ddr_edgesel_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [16:0] up_dld_s;
wire [84:0] up_dwdata_s;
wire [84:0] up_drdata_s;
wire delay_locked_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire [31:0] up_rdata_s[0:3];
wire up_rack_s[0:3];
wire up_wack_s[0:3];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
@ -218,9 +212,9 @@ module axi_ad9652 (
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
@ -301,14 +295,12 @@ module axi_ad9652 (
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// common processor control
@ -321,21 +313,15 @@ module axi_ad9652 (
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
@ -360,6 +346,26 @@ module axi_ad9652 (
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(17), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// up bus interface
up_axi i_up_axi (

96
library/axi_ad9652/axi_ad9652_if.v
View File

@ -68,14 +68,12 @@ module axi_ad9652_if (
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
@ -107,14 +105,12 @@ module axi_ad9652_if (
// delay control signals
input up_clk;
input [16:0] up_dld;
input [84:0] up_dwdata;
output [84:0] up_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
@ -130,13 +126,9 @@ module axi_ad9652_if (
reg [15:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
reg [16:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[16:0];
wire [15:0] adc_data_p_s;
wire [15:0] adc_data_n_s;
wire adc_or_p_s;
@ -172,64 +164,6 @@ module axi_ad9652_if (
end
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h10: delay_ld <= 17'h10000;
8'h0f: delay_ld <= 17'h08000;
8'h0e: delay_ld <= 17'h04000;
8'h0d: delay_ld <= 17'h02000;
8'h0c: delay_ld <= 17'h01000;
8'h0b: delay_ld <= 17'h00800;
8'h0a: delay_ld <= 17'h00400;
8'h09: delay_ld <= 17'h00200;
8'h08: delay_ld <= 17'h00100;
8'h07: delay_ld <= 17'h00080;
8'h06: delay_ld <= 17'h00040;
8'h05: delay_ld <= 17'h00020;
8'h04: delay_ld <= 17'h00010;
8'h03: delay_ld <= 17'h00008;
8'h02: delay_ld <= 17'h00004;
8'h01: delay_ld <= 17'h00002;
8'h00: delay_ld <= 17'h00001;
default: delay_ld <= 17'h00000;
endcase
end else begin
delay_ld <= 15'h0000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h10: delay_rdata <= delay_rdata_s[16];
8'h0f: delay_rdata <= delay_rdata_s[15];
8'h0e: delay_rdata <= delay_rdata_s[14];
8'h0d: delay_rdata <= delay_rdata_s[13];
8'h0c: delay_rdata <= delay_rdata_s[12];
8'h0b: delay_rdata <= delay_rdata_s[11];
8'h0a: delay_rdata <= delay_rdata_s[10];
8'h09: delay_rdata <= delay_rdata_s[ 9];
8'h08: delay_rdata <= delay_rdata_s[ 8];
8'h07: delay_rdata <= delay_rdata_s[ 7];
8'h06: delay_rdata <= delay_rdata_s[ 6];
8'h05: delay_rdata <= delay_rdata_s[ 5];
8'h04: delay_rdata <= delay_rdata_s[ 4];
8'h03: delay_rdata <= delay_rdata_s[ 3];
8'h02: delay_rdata <= delay_rdata_s[ 2];
8'h01: delay_rdata <= delay_rdata_s[ 1];
8'h00: delay_rdata <= delay_rdata_s[ 0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
@ -245,11 +179,12 @@ module axi_ad9652_if (
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
@ -266,11 +201,12 @@ module axi_ad9652_if (
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[16]),
.up_dwdata (up_dwdata[84:80]),
.up_drdata (up_drdata[84:80]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[16]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[16]),
.delay_locked (delay_locked));
// clock

22
library/axi_ad9671/axi_ad9671.v
View File

@ -46,7 +46,7 @@ module axi_ad9671 (
rx_clk,
rx_data,
rx_data_sof,
rx_sof,
// dma interface
@ -89,14 +89,13 @@ module axi_ad9671 (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_4L_2L_N = 1;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
input rx_clk;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
input rx_data_sof;
input rx_sof;
// dma interface
@ -207,7 +206,7 @@ module axi_ad9671 (
) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.rx_data_sof (rx_data_sof),
.rx_sof (rx_sof),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid_s),
@ -277,25 +276,16 @@ module axi_ad9671 (
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_sync_status (adc_sync_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

11
library/axi_ad9671/axi_ad9671_if.v
View File

@ -36,7 +36,6 @@
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
@ -46,7 +45,7 @@ module axi_ad9671_if (
// rx_clk is (line-rate/40)
rx_clk,
rx_data_sof,
rx_sof,
rx_data,
// adc data output
@ -88,7 +87,7 @@ module axi_ad9671_if (
// rx_clk is (line-rate/40)
input rx_clk;
input rx_data_sof;
input rx_sof;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
// adc data output
@ -142,6 +141,7 @@ module axi_ad9671_if (
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_sync_status = 'd0;
reg rx_sof_d = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
@ -219,9 +219,10 @@ module axi_ad9671_if (
always @(posedge rx_clk) begin
if (PCORE_4L_2L_N == 1'b1) begin
int_valid <= 1'b1;
int_data <= rx_data;
int_data <= rx_data;
end else begin
int_valid <= !rx_data_sof;
rx_sof_d <= rx_sof;
int_valid <= rx_sof_d;
int_data[63:0] <= {rx_data[31:0], int_data[63:32]};
int_data[127:64] <= {rx_data[63:32], int_data[127:96]};
end

1
library/axi_ad9671/axi_ad9671_ip.tcl
View File

@ -13,7 +13,6 @@ adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \

18
library/axi_ad9680/axi_ad9680.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -65,6 +63,7 @@ module axi_ad9680 (
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
@ -75,6 +74,7 @@ module axi_ad9680 (
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
@ -109,6 +109,7 @@ module axi_ad9680 (
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
@ -119,6 +120,7 @@ module axi_ad9680 (
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
@ -258,21 +260,15 @@ module axi_ad9680 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd40),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

34
library/axi_ad9680/axi_ad9680_hw.tcl
View File

@ -2,6 +2,7 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9680
set_module_property DESCRIPTION "AXI AD9680 Interface"
@ -71,26 +72,23 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
add_interface xcvr_clk clock end
add_interface_port xcvr_clk rx_clk clk Input 1
add_interface if_rx_clk clock end
add_interface_port if_rx_clk rx_clk clk Input 1
add_interface xcvr_data conduit end
set_interface_property xcvr_data associatedClock xcvr_clk
add_interface_port xcvr_data rx_data data Input 128
add_interface if_rx_data avalon_streaming end
set_interface_property if_rx_data associatedClock if_rx_clk
set_interface_property if_rx_data dataBitsPerSymbol 128
add_interface_port if_rx_data rx_data data Input 128
# dma interface
add_interface adc_clock clock start
add_interface_port adc_clock adc_clk clk Output 1
add_interface adc_dma_if conduit start
set_interface_property adc_dma_if associatedClock adc_clock
add_interface_port adc_dma_if adc_valid_0 adc_valid_0 Output 1
add_interface_port adc_dma_if adc_enable_0 adc_enable_0 Output 1
add_interface_port adc_dma_if adc_data_0 adc_data_0 Input 64
add_interface_port adc_dma_if adc_valid_1 adc_valid_1 Output 1
add_interface_port adc_dma_if adc_enable_1 adc_enable_1 Output 1
add_interface_port adc_dma_if adc_data_1 adc_data_1 Input 64
add_interface_port adc_dma_if adc_dovf adc_dovf Input 1
add_interface_port adc_dma_if adc_dunf adc_dunf Input 1
ad_alt_intf clock adc_clock output 1
ad_alt_intf signal adc_valid_0 output 1
ad_alt_intf signal adc_enable_0 output 1
ad_alt_intf signal adc_data_0 output 64
ad_alt_intf signal adc_valid_1 output 1
ad_alt_intf signal adc_enable_1 output 1
ad_alt_intf signal adc_data_1 output 64
ad_alt_intf signal adc_dovf input 1
ad_alt_intf signal adc_dunf input 1

1
library/axi_ad9680/axi_ad9680_ip.tcl
View File

@ -13,7 +13,6 @@ adi_ip_files axi_ad9680 [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9680_pnmon.v" \

1
library/axi_ad9739a/axi_ad9739a.v
View File

@ -91,7 +91,6 @@ module axi_ad9739a (
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// dac interface

1
library/axi_clkgen/axi_clkgen.v
View File

@ -78,7 +78,6 @@ module axi_clkgen (
parameter PCORE_VCO_MUL = 49;
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// clocks

34
library/axi_dmac/axi_dmac_hw.tcl
View File

@ -2,6 +2,7 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_dmac
set_module_property DESCRIPTION "AXI DMA Controller"
@ -303,30 +304,21 @@ proc axi_dmac_elaborate {} {
# fifo destination/source
if {[get_parameter_value C_DMA_TYPE_DEST] == 2} {
add_interface fifo_rd_clock clock end
add_interface_port fifo_rd_clock fifo_rd_clk clk Input 1
add_interface fifo_rd_if conduit end
set_interface_property fifo_rd_if associatedClock fifo_rd_clock
add_interface_port fifo_rd_if fifo_rd_en rden Input 1
add_interface_port fifo_rd_if fifo_rd_valid valid Output 1
add_interface_port fifo_rd_if fifo_rd_dout data Output C_DMA_DATA_WIDTH_DEST
add_interface_port fifo_rd_if fifo_rd_underflow unf Output 1
ad_alt_intf clock fifo_rd_clk input 1 dac_clk
ad_alt_intf signal fifo_rd_en input 1 dac_valid
ad_alt_intf signal fifo_rd_valid output 1 dma_valid
ad_alt_intf signal fifo_rd_dout output C_DMA_DATA_WIDTH_DEST dac_data
ad_alt_intf signal fifo_rd_underflow output 1 dac_dunf
ad_alt_intf signal fifo_rd_xfer_req output 1 dma_xfer_req
}
if {[get_parameter_value C_DMA_TYPE_SRC] == 2} {
add_interface fifo_wr_clock clock end
add_interface_port fifo_wr_clock fifo_wr_clk clk Input 1
add_interface fifo_wr_if conduit end
set_interface_property fifo_wr_if associatedClock fifo_wr_clock
add_interface_port fifo_wr_if fifo_wr_overflow ovf Output 1
add_interface_port fifo_wr_if fifo_wr_en wren Input 1
add_interface_port fifo_wr_if fifo_wr_din data Input C_DMA_DATA_WIDTH_SRC
add_interface_port fifo_wr_if fifo_wr_sync sync Input 1
ad_alt_intf clock fifo_wr_clk input 1 adc_clk
ad_alt_intf signal fifo_wr_en input 1 adc_valid
ad_alt_intf signal fifo_wr_din input C_DMA_DATA_WIDTH_SRC adc_data
ad_alt_intf signal fifo_wr_overflow output 1 adc_dovf
ad_alt_intf signal fifo_wr_sync input 1 adc_sync
ad_alt_intf signal fifo_wr_xfer_req output 1 dma_xfer_req
}
}

16
library/axi_ad7175/Makefile → library/axi_generic_adc/Makefile
View File

@ -5,7 +5,7 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad7175_ip.tcl
M_DEPS := axi_generic_adc_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_rst.v
@ -16,12 +16,8 @@ M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += up_adc_common.v
M_DEPS += ad_datafmt.v
M_DEPS += ad7175_if.v
M_DEPS += axi_ad7175.v
M_DEPS += axi_ad7175_channel.v
M_DEPS += clk_div.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += axi_generic_adc.v
M_VIVADO := vivado -mode batch -source
@ -37,7 +33,7 @@ M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_ad7175.xpr
all: axi_generic_adc.xpr
clean:clean-all
@ -47,9 +43,9 @@ clean-all:
rm -rf $(M_FLIST)
axi_ad7175.xpr: $(M_DEPS)
axi_generic_adc.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad7175_ip.tcl >> axi_ad7175_ip.log 2>&1
$(M_VIVADO) axi_generic_adc_ip.tcl >> axi_generic_adc_ip.log 2>&1
####################################################################################
####################################################################################

205
library/axi_generic_adc/axi_generic_adc.v Normal file
View File

@ -0,0 +1,205 @@
module axi_generic_adc (
input adc_clk,
output [NUM_CHANNELS-1:0] adc_enable,
input adc_dovf,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
parameter NUM_CHANNELS = 2;
parameter PCORE_ID = 0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
wire adc_rst;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS];
wire up_rack_s[0:NUM_CHANNELS];
wire up_wack_s[0:NUM_CHANNELS];
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
integer j;
always @(*)
begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= NUM_CHANNELS; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
end
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_status_ovf (adc_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd1),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS]),
.up_rack (up_rack_s[NUM_CHANNELS]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i=i+1) begin
up_adc_channel #(.PCORE_ADC_CHID(i)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
end
endgenerate
endmodule

15
library/axi_ad7175/axi_ad7175_ip.tcl → library/axi_generic_adc/axi_generic_adc_ip.tcl
View File

@ -3,8 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad7175
adi_ip_files axi_ad7175 [list \
adi_ip_create axi_generic_adc
adi_ip_files axi_generic_adc [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
@ -13,14 +13,11 @@ adi_ip_files axi_ad7175 [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"up_adc_common.v" \
"ad_datafmt.v" \
"ad7175_if.v" \
"axi_ad7175.v" \
"axi_ad7175_channel.v" \
"clk_div.v" ]
"$ad_hdl_dir/library/common/up_adc_common.v" \
"axi_generic_adc.v" \
]
adi_ip_properties axi_ad7175
adi_ip_properties axi_generic_adc
ipx::save_core [ipx::current_core]

1
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -105,7 +105,6 @@ module axi_hdmi_tx (
parameter PCORE_Cr_Cb_N = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;

3
library/axi_hdmi_tx/axi_hdmi_tx_alt.v
View File

@ -217,8 +217,7 @@ module axi_hdmi_tx_alt (
.PCORE_ID (PCORE_ID),
.PCORE_Cr_Cb_N (PCORE_Cr_Cb_N),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC),
.C_S_AXI_MIN_SIZE (32'hffff))
.PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC))
i_hdmi_tx (
.hdmi_clk (hdmi_clk),
.hdmi_out_clk (hdmi_out_clk),

1
library/axi_i2s_adi/Makefile
View File

@ -20,7 +20,6 @@ M_DEPS += i2s_clkgen.vhd
M_DEPS += fifo_synchronizer.vhd
M_DEPS += axi_i2s_adi.vhd
M_DEPS += axi_i2s_adi_constr.xdc
M_DEPS +=
M_VIVADO := vivado -mode batch -source

1
library/axi_i2s_adi/axi_i2s_adi.vhd
View File

@ -28,7 +28,6 @@ entity axi_i2s_adi is
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_FAMILY : string := "virtex6";
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_DMA_TYPE : integer := 0;

13
library/axi_jesd_gt/axi_jesd_gt.v
View File

@ -63,7 +63,7 @@ module axi_jesd_gt (
rx_clk_g,
rx_clk,
rx_data,
rx_data_sof,
rx_sof,
rx_gt_charisk,
rx_gt_disperr,
rx_gt_notintable,
@ -173,7 +173,6 @@ module axi_jesd_gt (
parameter PCORE_TX_LANE_SEL_6 = 6;
parameter PCORE_TX_LANE_SEL_7 = 7;
parameter PCORE_TX_LANE_SEL_8 = 8;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
localparam PCORE_NUM_OF_LANES = (PCORE_NUM_OF_TX_LANES > PCORE_NUM_OF_RX_LANES) ?
PCORE_NUM_OF_TX_LANES : PCORE_NUM_OF_RX_LANES;
@ -202,7 +201,7 @@ module axi_jesd_gt (
output rx_clk_g;
input rx_clk;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data;
output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_sof;
output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_charisk;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_disperr;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_notintable;
@ -322,7 +321,7 @@ module axi_jesd_gt (
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_data_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_sof_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_sof_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable_s;
@ -453,7 +452,7 @@ module axi_jesd_gt (
// asymmetric widths -- receive
assign rx_data = rx_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0];
assign rx_data_sof = rx_data_sof_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0];
assign rx_sof = rx_sof_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0];
assign rx_gt_charisk = rx_gt_charisk_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_disperr = rx_gt_disperr_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_notintable = rx_gt_notintable_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
@ -612,9 +611,9 @@ module axi_jesd_gt (
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_sof (rx_ip_sof),
.rx_ip_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data_sof(rx_data_sof_s[n]),
.rx_sof (rx_sof_s[n]),
.rx_data (rx_data_s[n*32+31:n*32]));
ad_gt_channel_1 #(

18
library/axi_mc_controller/axi_mc_controller.v
View File

@ -38,9 +38,6 @@
`timescale 1ns/100ps
module axi_mc_controller
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
(
input ref_clk, // 100 MHz
input ctrl_data_clk,
@ -308,7 +305,7 @@ control_registers control_reg_inst(
.gpo_o(gpo_o),
.reference_speed_o(),
.oloop_matlab_o(foc_ctrl_s),
.err_i(),
.err_i(32'h0),
.calibrate_adcs_o(),
.pwm_open_o(pwm_open_s));
@ -691,23 +688,14 @@ up_adc_common i_up_adc_common(
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(),
.adc_status_unf(),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'd0),
.delay_ack_t(1'b0),
.delay_locked(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),

25
library/axi_mc_current_monitor/axi_mc_current_monitor.v
View File

@ -37,10 +37,7 @@
`timescale 1ns/100ps
module axi_mc_current_monitor #(
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
(
module axi_mc_current_monitor (
// physical interface
@ -259,6 +256,8 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -303,6 +302,8 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -347,6 +348,8 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_stub(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -389,8 +392,8 @@ up_adc_common i_up_adc_common(
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(),
.adc_status_unf(),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
@ -399,16 +402,6 @@ up_adc_common i_up_adc_common(
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'd0),
.delay_ack_t(1'b0),
.delay_locked(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),

16
library/axi_mc_speed/axi_mc_speed.v
View File

@ -38,9 +38,6 @@
`timescale 1ns/100ps
module axi_mc_speed
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
//----------- Ports Declarations -----------------------------------------------
(
// physical interface
@ -189,23 +186,14 @@ up_adc_common i_up_adc_common(
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(),
.adc_status_unf(),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'd0),
.delay_ack_t(1'b0),
.delay_locked(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),

42
library/cn0363/cn0363_dma_sequencer/Makefile Normal file
View File

@ -0,0 +1,42 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := cn0363_dma_sequencer_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += cn0363_dma_sequencer.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: cn0363_dma_sequencer.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
cn0363_dma_sequencer.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) cn0363_dma_sequencer_ip.tcl >> cn0363_dma_sequencer_ip.log 2>&1
####################################################################################
####################################################################################

160
library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v Normal file
View File

@ -0,0 +1,160 @@
module cn0363_dma_sequencer (
input clk,
input resetn,
input [31:0] phase,
input phase_valid,
output reg phase_ready,
input [23:0] data,
input data_valid,
output reg data_ready,
input [31:0] data_filtered,
input data_filtered_valid,
output reg data_filtered_ready,
input [31:0] i_q,
input i_q_valid,
output reg i_q_ready,
input [31:0] i_q_filtered,
input i_q_filtered_valid,
output reg i_q_filtered_ready,
output overflow,
output reg [31:0] dma_wr_data,
output reg dma_wr_en,
output reg dma_wr_sync,
input dma_wr_overflow,
input dma_wr_xfer_req,
input [13:0] channel_enable,
output processing_resetn
);
reg [3:0] count = 'h00;
assign overflow = dma_wr_overflow;
assign processing_resetn = dma_wr_xfer_req;
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
count <= 'h0;
end else begin
case (count)
'h0: if (phase_valid) count <= count + 1;
'h1: if (data_valid) count <= count + 1;
'h2: if (data_filtered_valid) count <= count + 1;
'h3: if (i_q_valid) count <= count + 1;
'h4: if (i_q_valid) count <= count + 1;
'h5: if (i_q_filtered_valid) count <= count + 1;
'h6: if (i_q_filtered_valid) count <= count + 1;
'h7: if (phase_valid) count <= count + 1;
'h8: if (data_valid) count <= count + 1;
'h9: if (data_filtered_valid) count <= count + 1;
'ha: if (i_q_valid) count <= count + 1;
'hb: if (i_q_valid) count <= count + 1;
'hc: if (i_q_filtered_valid) count <= count + 1;
'hd: if (i_q_filtered_valid) count <= 'h00;
endcase
end
end
always @(posedge clk) begin
case (count)
'h0: dma_wr_data <= phase;
'h1: dma_wr_data <= {8'h00,data[23:0]};
'h2: dma_wr_data <= data_filtered;
'h3: dma_wr_data <= i_q;
'h4: dma_wr_data <= i_q;
'h5: dma_wr_data <= i_q_filtered;
'h6: dma_wr_data <= i_q_filtered;
'h7: dma_wr_data <= phase;
'h8: dma_wr_data <= {8'h00,data[23:0]};
'h9: dma_wr_data <= data_filtered;
'ha: dma_wr_data <= i_q;
'hb: dma_wr_data <= i_q;
'hc: dma_wr_data <= i_q_filtered;
'hd: dma_wr_data <= i_q_filtered;
endcase
end
always @(posedge clk) begin
if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
dma_wr_en <= 1'b0;
end else begin
case (count)
'h0: dma_wr_en <= phase_valid;
'h1: dma_wr_en <= data_valid;
'h2: dma_wr_en <= data_filtered_valid;
'h3: dma_wr_en <= i_q_valid;
'h4: dma_wr_en <= i_q_valid;
'h5: dma_wr_en <= i_q_filtered_valid;
'h6: dma_wr_en <= i_q_filtered_valid;
'h7: dma_wr_en <= phase_valid;
'h8: dma_wr_en <= data_valid;
'h9: dma_wr_en <= data_filtered_valid;
'ha: dma_wr_en <= i_q_valid;
'hb: dma_wr_en <= i_q_valid;
'hc: dma_wr_en <= i_q_filtered_valid;
'hd: dma_wr_en <= i_q_filtered_valid;
endcase
end
end
always @(posedge clk) begin
if (count == 'h00) begin
dma_wr_sync <= 1'b1;
end else if (dma_wr_en == 1'b1) begin
dma_wr_sync = 1'b0;
end
end
always @(*) begin
case (count)
'h0: phase_ready <= 1'b1;
'h7: phase_ready <= 1'b1;
default: phase_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h1: data_ready <= 1'b1;
'h8: data_ready <= 1'b1;
default: data_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h2: data_filtered_ready <= 1'b1;
'h9: data_filtered_ready <= 1'b1;
default: data_filtered_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h3: i_q_ready <= 1'b1;
'h4: i_q_ready <= 1'b1;
'ha: i_q_ready <= 1'b1;
'hb: i_q_ready <= 1'b1;
default: i_q_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h5: i_q_filtered_ready <= 1'b1;
'h6: i_q_filtered_ready <= 1'b1;
'hc: i_q_filtered_ready <= 1'b1;
'hd: i_q_filtered_ready <= 1'b1;
default: i_q_filtered_ready <= 1'b0;
endcase
end
endmodule

72
library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl Normal file
View File

@ -0,0 +1,72 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create cn0363_dma_sequencer
adi_ip_files cn0363_dma_sequencer [list \
"cn0363_dma_sequencer.v"
]
adi_ip_properties_lite cn0363_dma_sequencer
adi_add_bus "phase" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"phase_valid" "TVALID"} \
{"phase_ready" "TREADY"} \
{"phase" "TDATA"} \
}
adi_add_bus "data" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"data_valid" "TVALID"} \
{"data_ready" "TREADY"} \
{"data" "TDATA"} \
}
adi_add_bus "data_filtered" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"data_filtered_valid" "TVALID"} \
{"data_filtered_ready" "TREADY"} \
{"data_filtered" "TDATA"} \
}
adi_add_bus "i_q" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"i_q_valid" "TVALID"} \
{"i_q_ready" "TREADY"} \
{"i_q" "TDATA"} \
}
adi_add_bus "i_q_filtered" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"i_q_filtered_valid" "TVALID"} \
{"i_q_filtered_ready" "TREADY"} \
{"i_q_filtered" "TDATA"} \
}
adi_add_bus "dma_wr" "master" \
"analog.com:interface:fifo_wr_rtl:1.0" \
"analog.com:interface:fifo_wr:1.0" \
{
{"dma_wr_en" "EN"} \
{"dma_wr_sync" "SYNC"} \
{"dma_wr_data" "DATA"} \
{"dma_wr_overflow" "OVERFLOW"} \
{"dma_wr_xfer_req" "XFER_REQ"} \
}
adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "resetn:processing_resetn"
ipx::save_core [ipx::current_core]

42
library/cn0363/cn0363_phase_data_sync/Makefile Normal file
View File

@ -0,0 +1,42 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := cn0363_phase_data_sync_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += cn0363_phase_data_sync.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: cn0363_phase_data_sync.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
cn0363_phase_data_sync.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) cn0363_phase_data_sync_ip.tcl >> cn0363_phase_data_sync_ip.log 2>&1
####################################################################################
####################################################################################

131
library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v Normal file
View File

@ -0,0 +1,131 @@
module cn0363_phase_data_sync (
input clk,
input resetn,
input processing_resetn,
output s_axis_sample_ready,
input s_axis_sample_valid,
input [7:0] s_axis_sample_data,
input sample_has_stat,
input conv_done,
input [31:0] phase,
output reg m_axis_sample_valid,
input m_axis_sample_ready,
output [23:0] m_axis_sample_data,
output reg m_axis_phase_valid,
input m_axis_phase_ready,
output [31:0] m_axis_phase_data,
output reg overflow
);
reg [1:0] data_counter = 'h00;
reg [31:0] phase_hold = 'h00;
reg [23:0] sample_hold = 'h00;
reg sample_hold_valid = 1'b0;
reg conv_done_d1 = 1'b0;
reg synced = 1'b0;
wire sync;
/* The ADC will do conversions regardless of whether the pipeline is ready or
not. So we'll always accept new samples and assert overflow if necessary if
the pipeline is not ready. */
assign s_axis_sample_ready = 1'b1;
// Conversion from offset binary to signed on data
assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]};
assign m_axis_phase_data = phase_hold;
always @(posedge clk) begin
if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
// Is the processing pipeline ready to accept data?
if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
overflow <= 1'b1;
end else begin
phase_hold <= phase;
overflow <= 1'b0;
end
end else begin
overflow <= 1'b0;
end
conv_done_d1 <= conv_done;
end
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
m_axis_phase_valid <= 1'b0;
m_axis_sample_valid <= 1'b0;
end else begin
/* Data and phase become valid once we have both */
if (sample_hold_valid == 1'b1) begin
m_axis_phase_valid <= 1'b1;
m_axis_sample_valid <= 1'b1;
end else begin
if (m_axis_phase_ready == 1'b1) begin
m_axis_phase_valid <= 1'b0;
end
if (m_axis_sample_ready == 1'b1) begin
m_axis_sample_valid <= 1'b0;
end
end
end
end
/* If the STAT register is included in the sample we get 4 bytes per sample and
* are able to detect channel swaps and synchronize the first output sample to
* the first channel. If the STAT register is not included we only get 3 bytes
* per sample and rely on that the first sample will always be from the first
* channel */
always @(posedge clk) begin
sample_hold_valid <= 1'b0;
if (sample_has_stat == 1'b0) begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
sample_hold_valid <= 1'b1;
end
end else begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
(sync == 1'b1 || synced == 1'b1)) begin
sample_hold_valid <= 1'b1;
end
end
end
always @(posedge clk) begin
if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
sample_hold <= {sample_hold[15:0],s_axis_sample_data};
end
end
always @(posedge clk) begin
if (s_axis_sample_valid == 1'b1) begin
if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
data_counter <= 2'h0;
end else begin
data_counter <= data_counter + 1'b1;
end
end
end
assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3;
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
synced <= ~sample_has_stat;
end else begin
if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
synced <= 1'b1;
end
end
end
endmodule

41
library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl Normal file
View File

@ -0,0 +1,41 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create cn0363_phase_data_sync
adi_ip_files cn0363_phase_data_sync [list \
"cn0363_phase_data_sync.v"
]
adi_ip_properties_lite cn0363_phase_data_sync
adi_add_bus "S_AXIS_SAMPLE" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"s_axis_sample_valid" "TVALID"} \
{"s_axis_sample_ready" "TREADY"} \
{"s_axis_sample_data" "TDATA"} \
}
adi_add_bus "M_AXIS_SAMPLE" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"m_axis_sample_valid" "TVALID"} \
{"m_axis_sample_ready" "TREADY"} \
{"m_axis_sample_data" "TDATA"} \
}
adi_add_bus "M_AXIS_PHASE" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"m_axis_phase_valid" "TVALID"} \
{"m_axis_phase_ready" "TREADY"} \
{"m_axis_phase_data" "TDATA"} \
}
adi_add_bus_clock "clk" "S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE" "resetn"
ipx::save_core [ipx::current_core]

23
library/common/ad_iobuf.v
View File

@ -41,26 +41,23 @@
module ad_iobuf (
dt,
di,
do,
dio);
dio_t,
dio_i,
dio_o,
dio_p);
parameter DATA_WIDTH = 1;
input [(DATA_WIDTH-1):0] dt;
input [(DATA_WIDTH-1):0] di;
output [(DATA_WIDTH-1):0] do;
inout [(DATA_WIDTH-1):0] dio;
input [(DATA_WIDTH-1):0] dio_t;
input [(DATA_WIDTH-1):0] dio_i;
output [(DATA_WIDTH-1):0] dio_o;
inout [(DATA_WIDTH-1):0] dio_p;
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
IOBUF i_iobuf (
.I (di[n]),
.O (do[n]),
.T (dt[n]),
.IO (dio[n]));
assign dio_o[n] = dio_p[n];
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
end
endgenerate

30
library/common/ad_jesd_align.v
View File

@ -42,45 +42,45 @@ module ad_jesd_align (
// jesd interface
rx_clk,
rx_sof,
rx_ip_sof,
rx_ip_data,
rx_data_sof,
rx_sof,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [ 3:0] rx_ip_sof;
input [31:0] rx_ip_data;
// aligned data
output rx_data_sof;
output rx_sof;
output [31:0] rx_data;
// internal registers
reg [31:0] rx_ip_data_d = 'd0;
reg [ 3:0] rx_sof_d = 'd0;
reg [ 3:0] rx_ip_sof_hold = 'd0;
reg rx_sof = 'd0;
reg rx_ip_sof_d = 'd0;
reg [31:0] rx_data = 'd0;
// dword may contain more than one frame per clock
assign rx_data_sof = |rx_sof;
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
if (rx_sof != 4'h0)
begin
rx_sof_d <= rx_sof;
rx_ip_sof_d <= rx_ip_sof;
if (rx_ip_sof != 4'h0) begin
rx_ip_sof_hold <= rx_ip_sof;
end
if (rx_sof_d[0] == 1'b1) begin
rx_sof <= |rx_ip_sof_d;
if (rx_ip_sof_hold[0] == 1'b1) begin
rx_data <= rx_ip_data;
end else if (rx_sof_d[1] == 1'b1) begin
end else if (rx_ip_sof_hold[1] == 1'b1) begin
rx_data <= {rx_ip_data[ 7:0], rx_ip_data_d[31: 8]};
end else if (rx_sof_d[2] == 1'b1) begin
end else if (rx_ip_sof_hold[2] == 1'b1) begin
rx_data <= {rx_ip_data[15:0], rx_ip_data_d[31:16]};
end else if (rx_sof_d[3] == 1'b1) begin
end else if (rx_ip_sof_hold[3] == 1'b1) begin
rx_data <= {rx_ip_data[23:0], rx_ip_data_d[31:24]};
end else begin
rx_data <= 32'd0;

40
library/common/ad_lvds_in.v
View File

@ -49,13 +49,17 @@ module ad_lvds_in (
rx_data_p,
rx_data_n,
// delay interface
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_ld,
delay_wdata,
delay_rdata,
delay_locked);
// parameters
@ -74,13 +78,17 @@ module ad_lvds_in (
output rx_data_p;
output rx_data_n;
// delay interface
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
input delay_ld;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_locked;
// internal registers
@ -134,12 +142,12 @@ module ad_lvds_in (
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (delay_ld),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata));
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
@ -158,12 +166,12 @@ module ad_lvds_in (
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (delay_ld),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata));
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
IDDR #(

81
library/common/ad_lvds_out.v
View File

@ -47,11 +47,27 @@ module ad_lvds_out (
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n);
tx_data_out_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter BUFTYPE = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
@ -63,11 +79,39 @@ module ad_lvds_out (
output tx_data_out_p;
output tx_data_out_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal signals
wire tx_data_oddr_s;
wire tx_data_odelay_s;
// transmit data interface, oddr -> obuf
// delay controller
generate
if ((IODELAY_ENABLE == 1) && (BUFTYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// transmit data interface, oddr -> odelay -> obuf
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
@ -82,8 +126,39 @@ module ad_lvds_out (
.D2 (tx_data_n),
.Q (tx_data_oddr_s));
generate
if ((IODELAY_ENABLE == 1) && (BUFTYPE == SERIES7)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
ODELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("ODATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.ODELAY_TYPE ("VAR_LOAD"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_tx_data_odelay (
.CE (1'b0),
.CLKIN (1'b0),
.INC (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.ODATAIN (tx_data_oddr_s),
.DATAOUT (tx_data_odelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end else begin
assign up_drdata = 5'd0;
assign tx_data_odelay_s = tx_data_oddr_s;
end
endgenerate
OBUFDS i_tx_data_obuf (
.I (tx_data_oddr_s),
.I (tx_data_odelay_s),
.O (tx_data_out_p),
.OB (tx_data_out_n));

39
library/common/ad_serdes_in.v
View File

@ -60,13 +60,17 @@ module ad_serdes_in (
data_in_p,
data_in_n,
// delay interface
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-control interface
delay_clk,
delay_rst,
delay_ld,
delay_wdata,
delay_rdata,
delay_locked);
// parameters
@ -103,13 +107,16 @@ module ad_serdes_in (
input data_in_p;
input data_in_n;
// delay interface
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-control interface
input delay_clk;
input delay_rst;
input delay_ld;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_locked;
// internal signals
@ -160,12 +167,12 @@ module ad_serdes_in (
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.C (up_clk),
.IDATAIN (data_in_ibuf_s),
.DATAOUT (data_in_idelay_s),
.LD (delay_ld),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata));
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
// Note: The first sample in time will be data_s7, the last data_s0!
if(IF_TYPE == SDR) begin
@ -290,12 +297,12 @@ module ad_serdes_in (
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.C (up_clk),
.IDATAIN (data_in_ibuf_s),
.DATAOUT (data_in_idelay_s),
.RST (delay_ld),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata));
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
ISERDESE1 #(
.DATA_RATE("DDR"),

32
library/common/altera/ad_jesd_align.v
View File

@ -42,57 +42,53 @@ module ad_jesd_align (
// jesd interface
rx_clk,
rx_sof,
rx_ip_sof,
rx_ip_data,
rx_data_sof,
rx_sof,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [ 3:0] rx_ip_sof;
input [31:0] rx_ip_data;
// aligned data
output rx_data_sof;
output rx_sof;
output [31:0] rx_data;
// internal registers
reg [ 3:0] rx_sof_hold = 'd0;
reg [31:0] rx_ip_data_d = 'd0;
reg [ 3:0] rx_ip_sof_hold = 'd0;
reg rx_sof = 'd0;
reg [31:0] rx_data = 'd0;
// internal signals
// dword may contain more than one frame per clock
assign rx_data_sof = |rx_sof;
always @(posedge rx_clk) begin
if (rx_sof != 4'd0) begin
rx_sof_hold <= rx_sof;
end
rx_ip_data_d <= rx_ip_data;
if (rx_sof_hold[3] == 1'b1) begin
if (rx_ip_sof != 4'd0) begin
rx_ip_sof_hold <= rx_ip_sof;
end
rx_sof <= |rx_ip_sof;
if (rx_ip_sof_hold[3] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[ 7: 0];
rx_data[23:16] <= rx_ip_data[15: 8];
rx_data[15: 8] <= rx_ip_data[23:16];
rx_data[ 7: 0] <= rx_ip_data[31:24];
end else if (rx_sof_hold[2] == 1'b1) begin
end else if (rx_ip_sof_hold[2] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[31:24];
rx_data[23:16] <= rx_ip_data_d[ 7: 0];
rx_data[15: 8] <= rx_ip_data_d[15: 8];
rx_data[ 7: 0] <= rx_ip_data_d[23:16];
end else if (rx_sof_hold[1] == 1'b1) begin
end else if (rx_ip_sof_hold[1] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[23:16];
rx_data[23:16] <= rx_ip_data[31:24];
rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
end else if (rx_sof_hold[0] == 1'b1) begin
end else if (rx_ip_sof_hold[0] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[15: 8];
rx_data[23:16] <= rx_ip_data[23:16];
rx_data[15: 8] <= rx_ip_data[31:24];

66
library/common/up_adc_common.v
View File

@ -66,18 +66,6 @@ module up_adc_common (
up_status_pn_oos,
up_status_or,
// delay interface
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// drp interface
drp_clk,
@ -140,18 +128,6 @@ module up_adc_common (
input up_status_pn_oos;
input up_status_or;
// delay interface
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// drp interface
input drp_clk;
@ -193,10 +169,6 @@ module up_adc_common (
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_delay_sel = 'd0;
reg up_delay_rwn = 'd0;
reg [ 7:0] up_delay_addr = 'd0;
reg [ 4:0] up_delay_wdata = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
@ -222,9 +194,6 @@ module up_adc_common (
wire up_status_unf_s;
wire up_cntrl_xfer_done;
wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_status_s;
wire up_delay_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire up_drp_locked_s;
@ -247,10 +216,6 @@ module up_adc_common (
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_delay_sel <= 'd0;
up_delay_rwn <= 'd0;
up_delay_addr <= 'd0;
up_delay_wdata <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
@ -281,12 +246,6 @@ module up_adc_common (
up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
up_delay_sel <= up_wdata[17];
up_delay_rwn <= up_wdata[16];
up_delay_addr <= up_wdata[15:8];
up_delay_wdata <= up_wdata[4:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_rwn <= up_wdata[28];
@ -333,8 +292,6 @@ module up_adc_common (
8'h15: up_rdata <= up_adc_clk_count_s;
8'h16: up_rdata <= adc_clk_ratio;
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata};
8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s};
8'h1a: up_rdata <= {31'd0, up_sync_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
@ -356,7 +313,6 @@ module up_adc_common (
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
ad_rst i_delay_rst_reg (.preset(up_preset_s), .clk(delay_clk), .rst(delay_rst));
ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
// adc control & status
@ -408,28 +364,6 @@ module up_adc_common (
.d_rst (adc_rst),
.d_clk (adc_clk));
// delay control & status
up_delay_cntrl i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.up_delay_rdata (up_delay_rdata_s),
.up_delay_status (up_delay_status_s),
.up_delay_locked (up_delay_locked_s));
// drp control & status
up_drp_cntrl i_drp_cntrl (

218
library/common/up_delay_cntrl.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -45,128 +43,158 @@ module up_delay_cntrl (
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// io interface
up_dld,
up_dwdata,
up_drdata,
// processor interface
up_rstn,
up_clk,
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
up_delay_rdata,
up_delay_status,
up_delay_locked);
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IO_WIDTH = 8;
parameter IO_BASEADDR = 6'h02;
// delay interface
input delay_clk;
input delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
input delay_clk;
output delay_rst;
input delay_locked;
// io interface
output [(IO_WIDTH-1):0] up_dld;
output [((IO_WIDTH*5)-1):0] up_dwdata;
input [((IO_WIDTH*5)-1):0] up_drdata;
// processor interface
input up_rstn;
input up_clk;
input up_delay_sel;
input up_delay_rwn;
input [ 7:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
output [ 4:0] up_delay_rdata;
output up_delay_status;
output up_delay_locked;
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg delay_sel_m1 = 'd0;
reg delay_sel_m2 = 'd0;
reg delay_sel_m3 = 'd0;
reg delay_sel = 'd0;
reg delay_rwn = 'd0;
reg [ 7:0] delay_addr = 'd0;
reg [ 4:0] delay_wdata = 'd0;
reg up_delay_locked_m1 = 'd0;
reg up_delay_locked = 'd0;
reg up_delay_ack_t_m1 = 'd0;
reg up_delay_ack_t_m2 = 'd0;
reg up_delay_ack_t_m3 = 'd0;
reg up_delay_sel_d = 'd0;
reg up_delay_status = 'd0;
reg [ 4:0] up_delay_rdata = 'd0;
reg up_preset = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_dlocked_m1 = 'd0;
reg up_dlocked = 'd0;
reg [(IO_WIDTH-1):0] up_dld = 'd0;
reg [((IO_WIDTH*5)-1):0] up_dwdata = 'd0;
// internal signals
wire up_delay_ack_t_s;
wire up_delay_sel_s;
wire up_wreq_s;
wire up_rreq_s;
wire [ 4:0] up_rdata_s;
wire [(IO_WIDTH-1):0] up_drdata4_s;
wire [(IO_WIDTH-1):0] up_drdata3_s;
wire [(IO_WIDTH-1):0] up_drdata2_s;
wire [(IO_WIDTH-1):0] up_drdata1_s;
wire [(IO_WIDTH-1):0] up_drdata0_s;
// delay control transfer
// variables
always @(posedge delay_clk) begin
if (delay_rst == 1'b1) begin
delay_sel_m1 <= 'd0;
delay_sel_m2 <= 'd0;
delay_sel_m3 <= 'd0;
end else begin
delay_sel_m1 <= up_delay_sel;
delay_sel_m2 <= delay_sel_m1;
delay_sel_m3 <= delay_sel_m2;
end
genvar n;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == IO_BASEADDR) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == IO_BASEADDR) ? up_rreq : 1'b0;
assign up_rdata_s[4] = | up_drdata4_s;
assign up_rdata_s[3] = | up_drdata3_s;
assign up_rdata_s[2] = | up_drdata2_s;
assign up_rdata_s[1] = | up_drdata1_s;
assign up_rdata_s[0] = | up_drdata0_s;
generate
for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_drd
assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
end
endgenerate
always @(posedge delay_clk) begin
delay_sel <= delay_sel_m2 & ~delay_sel_m3;
if ((delay_sel_m2 == 1'b1) && (delay_sel_m3 == 1'b0)) begin
delay_rwn <= up_delay_rwn;
delay_addr <= up_delay_addr;
delay_wdata <= up_delay_wdata;
end
end
// delay status transfer
assign up_delay_ack_t_s = up_delay_ack_t_m3 ^ up_delay_ack_t_m2;
assign up_delay_sel_s = up_delay_sel & ~up_delay_sel_d;
// processor interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_delay_locked_m1 <= 'd0;
up_delay_locked <= 'd0;
up_delay_ack_t_m1 <= 'd0;
up_delay_ack_t_m2 <= 'd0;
up_delay_ack_t_m3 <= 'd0;
up_delay_sel_d <= 'd0;
up_delay_status <= 'd0;
up_delay_rdata <= 'd0;
up_preset <= 1'd1;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
up_dlocked_m1 <= 'd0;
up_dlocked <= 'd0;
end else begin
up_delay_locked_m1 <= delay_locked;
up_delay_locked <= up_delay_locked_m1;
up_delay_ack_t_m1 <= delay_ack_t;
up_delay_ack_t_m2 <= up_delay_ack_t_m1;
up_delay_ack_t_m3 <= up_delay_ack_t_m2;
up_delay_sel_d <= up_delay_sel;
if (up_delay_ack_t_s == 1'b1) begin
up_delay_status <= 1'b0;
end else if (up_delay_sel_s == 1'b1) begin
up_delay_status <= 1'b1;
up_preset <= 1'd0;
up_wack <= up_wreq_s;
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
if (up_dlocked == 1'b0) begin
up_rdata <= 32'hffffffff;
end else begin
up_rdata <= {27'd0, up_rdata_s};
end
end else begin
up_rdata <= 32'd0;
end
if (up_delay_ack_t_s == 1'b1) begin
up_delay_rdata <= delay_rdata;
up_dlocked_m1 <= delay_locked;
up_dlocked <= up_dlocked_m1;
end
end
// write does not hold- read back what goes into effect.
generate
for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_dwr
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dld[n] <= 'd0;
up_dwdata[((n*5)+4):(n*5)] <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
up_dld[n] <= 1'd1;
up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
end else begin
up_dld[n] <= 1'd0;
up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
end
end
end
end
endgenerate
// resets
ad_rst i_delay_rst_reg (
.preset (up_preset),
.clk (delay_clk),
.rst (delay_rst));
endmodule

42
library/cordic_demod/Makefile Normal file
View File

@ -0,0 +1,42 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := cordic_demod_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += cordic_demod.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: cordic_demod.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
cordic_demod.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) cordic_demod_ip.tcl >> cordic_demod_ip.log 2>&1
####################################################################################
####################################################################################

168
library/cordic_demod/cordic_demod.v Normal file
View File

@ -0,0 +1,168 @@
module cordic_demod (
input clk,
input resetn,
input s_axis_valid,
output s_axis_ready,
input [63:0] s_axis_data,
output m_axis_valid,
input m_axis_ready,
output [63:0] m_axis_data
);
reg [4:0] step_counter;
reg [4:0] shift_counter;
reg [30:0] phase;
reg [2:0] state;
reg [32:0] i;
reg [32:0] q;
reg [32:0] i_shift;
reg [32:0] q_shift;
assign s_axis_ready = state == STATE_IDLE;
assign m_axis_data = {q[32:1],i[32:1]};
assign m_axis_valid = state == STATE_DONE;
localparam STATE_IDLE = 0;
localparam STATE_SHIFT_LOAD = 1;
localparam STATE_SHIFT = 2;
localparam STATE_ADD = 3;
localparam STATE_DONE = 4;
reg [31:0] angle[0:30];
initial begin
angle[0] = 32'h20000000;
angle[1] = 32'h12e4051e;
angle[2] = 32'h09fb385b;
angle[3] = 32'h051111d4;
angle[4] = 32'h028b0d43;
angle[5] = 32'h0145d7e1;
angle[6] = 32'h00a2f61e;
angle[7] = 32'h00517c55;
angle[8] = 32'h0028be53;
angle[9] = 32'h00145f2f;
angle[10] = 32'h000a2f98;
angle[11] = 32'h000517cc;
angle[12] = 32'h00028be6;
angle[13] = 32'h000145f3;
angle[14] = 32'h0000a2fa;
angle[15] = 32'h0000517d;
angle[16] = 32'h000028be;
angle[17] = 32'h0000145f;
angle[18] = 32'h00000a30;
angle[19] = 32'h00000518;
angle[20] = 32'h0000028c;
angle[21] = 32'h00000146;
angle[22] = 32'h000000a3;
angle[23] = 32'h00000051;
angle[24] = 32'h00000029;
angle[25] = 32'h00000014;
angle[26] = 32'h0000000a;
angle[27] = 32'h00000005;
angle[28] = 32'h00000003;
angle[29] = 32'h00000001;
angle[30] = 32'h00000001;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
state <= STATE_IDLE;
end else begin
case (state)
STATE_IDLE: begin
if (s_axis_valid == 1'b1) begin
state <= STATE_SHIFT_LOAD;
end
end
STATE_SHIFT_LOAD: begin
if (step_counter == 'h00) begin
state <= STATE_ADD;
end else begin
state <= STATE_SHIFT;
end
end
STATE_SHIFT: begin
if (shift_counter == 'h01) begin
state <= STATE_ADD;
end
end
STATE_ADD: begin
if (step_counter == 'd30) begin
state <= STATE_DONE;
end else begin
state <= STATE_SHIFT_LOAD;
end
end
STATE_DONE: begin
if (m_axis_ready == 1'b1)
state <= STATE_IDLE;
end
endcase
end
end
always @(posedge clk) begin
case(state)
STATE_SHIFT_LOAD: begin
shift_counter <= step_counter;
end
STATE_SHIFT: begin
shift_counter <= shift_counter - 1'b1;
end
endcase
end
always @(posedge clk)
begin
case(state)
STATE_IDLE:
if (s_axis_valid == 1'b1) begin
step_counter <= 'h00;
phase <= {1'b0,s_axis_data[61:32]};
step_counter <= 'h00;
case (s_axis_data[63:62])
2'b00: begin
i <= {s_axis_data[31],s_axis_data[31:0]};
q <= 'h00;
end
2'b01: begin
i <= 'h00;
q <= ~{s_axis_data[31],s_axis_data[31:0]};
end
2'b10: begin
i <= ~{s_axis_data[31],s_axis_data[31:0]};
q <= 'h00;
end
2'b11: begin
i <= 'h00;
q <= {s_axis_data[31],s_axis_data[31:0]};
end
endcase
end
STATE_SHIFT_LOAD: begin
i_shift <= i;
q_shift <= q;
end
STATE_SHIFT: begin
i_shift <= {i_shift[32],i_shift[32:1]};
q_shift <= {q_shift[32],q_shift[32:1]};
end
STATE_ADD: begin
if (phase[30] == 1'b0) begin
i <= i + q_shift;
q <= q - i_shift;
phase <= phase - angle[step_counter];
end else begin
i <= i - q_shift;
q <= q + i_shift;
phase <= phase + angle[step_counter];
end
step_counter <= step_counter + 1'b1;
end
endcase
end
endmodule

32
library/cordic_demod/cordic_demod_ip.tcl Normal file
View File

@ -0,0 +1,32 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create cordic_demod
adi_ip_files cordic_demod [list \
"cordic_demod.v" \
]
adi_ip_properties_lite cordic_demod
adi_add_bus "S_AXIS" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"s_axis_valid" "TVALID"} \
{"s_axis_ready" "TREADY"} \
{"s_axis_data" "TDATA"} \
}
adi_add_bus "M_AXIS" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{
{"m_axis_valid" "TVALID"} \
{"m_axis_ready" "TREADY"} \
{"m_axis_data" "TDATA"} \
}
adi_add_bus_clock "clk" "S_AXIS:M_AXIS" "resetn"
ipx::save_core [ipx::current_core]

3
library/scripts/adi_ip.tcl
View File

@ -150,7 +150,7 @@ proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
}
}
proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""}} {
proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
@ -172,6 +172,7 @@ proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""}} {
set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
set_property display_name $reset_inf_name $reset_inf
set_property interface_mode $reset_signal_mode $reset_inf
set reset_map [ipx::add_port_map "RST" $reset_inf]
set_property physical_name $reset_signal_name $reset_map

28
library/scripts/adi_ip_alt.tcl Normal file
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@ -0,0 +1,28 @@
# keep interface-mess out of the way - keeping it pretty is a waste of time
proc ad_alt_intf {type name dir width {remap ""}} {
if {(($type eq "clock") && ($dir eq "input"))} {
add_interface if_${name} clock sink
add_interface_port if_${name} ${name} clk ${dir} ${width}
return
}
if {(($type eq "clock") && ($dir eq "output"))} {
add_interface if_${name} clock source
add_interface_port if_${name} ${name} clk ${dir} ${width}
return
}
if {$remap eq ""} {
set remap $name
}
if {$type eq "signal"} {
add_interface if_${name} conduit end
add_interface_port if_${name} ${name} ${remap} ${dir} ${width}
return
}
}

49
library/spi_engine/axi_spi_engine/Makefile Normal file
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@ -0,0 +1,49 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := axi_spi_engine_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += axi_spi_engine.v
M_DEPS += ../../common/sync_bits.v
M_DEPS += ../../common/sync_gray.v
M_DEPS += ../../common/up_axi.v
M_DEPS += ../../common/ad_rst.v
M_DEPS += ../../util_axis_fifo/util_axis_fifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all dep clean clean-all
all: dep axi_spi_engine.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_spi_engine.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) axi_spi_engine_ip.tcl >> axi_spi_engine_ip.log 2>&1
dep:
make -C ../../util_axis_fifo
####################################################################################
####################################################################################

335
library/spi_engine/axi_spi_engine/axi_spi_engine.v Normal file
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@ -0,0 +1,335 @@
module axi_spi_engine (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
output reg irq,
// SPI signals
input spi_clk,
output spi_resetn,
input cmd_ready,
output cmd_valid,
output [15:0] cmd_data,
input sdo_data_ready,
output sdo_data_valid,
output [7:0] sdo_data,
output sdi_data_ready,
input sdi_data_valid,
input [7:0] sdi_data,
output sync_ready,
input sync_valid,
input [7:0] sync_data,
// Offload ctrl signals
output offload0_cmd_wr_en,
output [15:0] offload0_cmd_wr_data,
output offload0_sdo_wr_en,
output [7:0] offload0_sdo_wr_data,
output reg offload0_mem_reset,
output reg offload0_enable,
input offload0_enabled
);
parameter CMD_FIFO_ADDRESS_WIDTH = 4;
parameter SDO_FIFO_ADDRESS_WIDTH = 5;
parameter SDI_FIFO_ADDRESS_WIDTH = 5;
parameter ASYNC_SPI_CLK = 0;
parameter NUM_OFFLOAD = 0;
parameter OFFLOAD0_CMD_MEM_ADDR_WIDTH = 4;
parameter OFFLOAD0_SDO_MEM_ADDR_WIDTH = 4;
parameter PCORE_ID = 'h00;
localparam PCORE_VERSION = 'h010061;
wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
wire cmd_fifo_almost_empty;
wire [15:0] cmd_fifo_in_data;
wire cmd_fifo_in_ready;
wire cmd_fifo_in_valid;
wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
wire sdo_fifo_almost_empty;
wire [7:0] sdo_fifo_in_data;
wire sdo_fifo_in_ready;
wire sdo_fifo_in_valid;
wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
wire sdi_fifo_almost_full;
wire [7:0] sdi_fifo_out_data;
wire sdi_fifo_out_ready;
wire sdi_fifo_out_valid;
reg up_reset = 1'b1;
wire up_resetn = ~up_reset;
reg [31:0] up_rdata = 'd0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
wire up_wreq;
wire up_rreq;
wire [31:0] up_wdata;
wire [ 7:0] up_waddr;
wire [ 7:0] up_raddr;
// Scratch register
reg [31:0] up_scratch = 'h00;
reg [7:0] sync_id = 'h00;
reg sync_id_pending = 1'b0;
up_axi #(
.PCORE_ADDR_WIDTH (8)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack)
);
// IRQ handling
reg [3:0] up_irq_mask = 'h0;
wire [3:0] up_irq_source;
wire [3:0] up_irq_pending;
assign up_irq_source = {
sync_id_pending,
sdi_fifo_almost_full,
sdo_fifo_almost_empty,
cmd_fifo_almost_empty
};
assign up_irq_pending = up_irq_mask & up_irq_source;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
up_wack <= 1'b0;
up_scratch <= 'h00;
up_reset <= 1'b1;
up_irq_mask <= 'h00;
offload0_enable <= 1'b0;
offload0_mem_reset <= 1'b0;
end else begin
up_wack <= up_wreq;
offload0_mem_reset <= 1'b0;
if (up_wreq) begin
case (up_waddr)
8'h02: up_scratch <= up_wdata;
8'h10: up_reset <= up_wdata;
8'h20: up_irq_mask <= up_wdata;
8'h40: offload0_enable <= up_wdata[0];
8'h42: offload0_mem_reset <= up_wdata[0];
endcase
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
up_rack <= 'd0;
end else begin
up_rack <= up_rreq;
end
end
always @(posedge s_axi_aclk) begin
case (up_raddr)
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= up_reset;
8'h20: up_rdata <= up_irq_mask;
8'h21: up_rdata <= up_irq_pending;
8'h22: up_rdata <= up_irq_source;
8'h30: up_rdata <= sync_id;
8'h34: up_rdata <= cmd_fifo_room;
8'h35: up_rdata <= sdo_fifo_room;
8'h36: up_rdata <= sdi_fifo_level;
8'h3a: up_rdata <= sdi_fifo_out_data;
8'h3c: up_rdata <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata <= {offload0_enable};
8'h41: up_rdata <= {offload0_enabled};
default: up_rdata <= 'h00;
endcase
end
always @(posedge s_axi_aclk) begin
if (up_resetn == 1'b0) begin
sync_id <= 'h00;
sync_id_pending <= 1'b0;
end else begin
if (sync_valid == 1'b1) begin
sync_id <= sync_data;
sync_id_pending <= 1'b1;
end else if (up_wreq == 1'b1 && up_waddr == 8'h21 && up_wdata[3] == 1'b1) begin
sync_id_pending <= 1'b0;
end
end
end
assign sync_ready = 1'b1;
generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
ad_rst i_spi_resetn (
.preset(up_reset),
.clk(spi_clk),
.rst(spi_reset)
);
assign spi_resetn = ~spi_reset;
end else begin
assign spi_resetn = ~up_reset;
end
endgenerate
/* Evaluates to true if FIFO level/room is 3/4 or above */
`define axi_spi_engine_check_watermark(x, n) \
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
assign cmd_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h38;
assign cmd_fifo_in_data = up_wdata[15:0];
assign cmd_fifo_almost_empty =
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.C_DATA_WIDTH(16),
.C_CLKS_ASYNC(ASYNC_SPI_CLK),
.C_ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
.C_S_AXIS_REGISTERED(0)
) i_cmd_fifo (
.s_axis_aclk(s_axi_aclk),
.s_axis_aresetn(up_resetn),
.s_axis_ready(cmd_fifo_in_ready),
.s_axis_valid(cmd_fifo_in_valid),
.s_axis_data(cmd_fifo_in_data),
.s_axis_room(cmd_fifo_room),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(cmd_ready),
.m_axis_valid(cmd_valid),
.m_axis_data(cmd_data)
);
assign sdo_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h39;
assign sdo_fifo_in_data = up_wdata[7:0];
assign sdo_fifo_almost_empty =
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.C_DATA_WIDTH(8),
.C_CLKS_ASYNC(ASYNC_SPI_CLK),
.C_ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
.C_S_AXIS_REGISTERED(0)
) i_sdo_fifo (
.s_axis_aclk(s_axi_aclk),
.s_axis_aresetn(up_resetn),
.s_axis_ready(sdo_fifo_in_ready),
.s_axis_valid(sdo_fifo_in_valid),
.s_axis_data(sdo_fifo_in_data),
.s_axis_room(sdo_fifo_room),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(sdo_data_ready),
.m_axis_valid(sdo_data_valid),
.m_axis_data(sdo_data)
);
assign sdi_fifo_out_ready = up_rreq == 1'b1 && up_raddr == 8'h3a;
assign sdi_fifo_almost_full =
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.C_DATA_WIDTH(8),
.C_CLKS_ASYNC(ASYNC_SPI_CLK),
.C_ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
.C_S_AXIS_REGISTERED(0)
) i_sdi_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sdi_data_ready),
.s_axis_valid(sdi_data_valid),
.s_axis_data(sdi_data),
.m_axis_aclk(s_axi_aclk),
.m_axis_aresetn(up_resetn),
.m_axis_ready(sdi_fifo_out_ready),
.m_axis_valid(sdi_fifo_out_valid),
.m_axis_data(sdi_fifo_out_data),
.m_axis_level(sdi_fifo_level)
);
assign offload0_cmd_wr_en = up_wreq == 1'b1 && up_waddr == 8'h44;
assign offload0_cmd_wr_data = up_wdata[15:0];
assign offload0_sdo_wr_en = up_wreq == 1'b1 && up_waddr == 8'h45;
assign offload0_sdo_wr_data = up_wdata[7:0];
endmodule

62
library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl Normal file
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@ -0,0 +1,62 @@
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_spi_engine
adi_ip_files axi_spi_engine [list \
"axi_spi_engine.v" \
"$ad_hdl_dir/library/common/sync_bits.v" \
"$ad_hdl_dir/library/common/sync_gray.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
]
adi_ip_properties axi_spi_engine
# Remove auto inferred interfaces
ipx::remove_bus_interface offload0_mem_signal_reset [ipx::current_core]
ipx::remove_bus_interface spi_signal_clock [ipx::current_core]
ipx::remove_bus_interface spi_signal_reset [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \
}
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd_data" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
}
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
adi_add_bus "spi_engine_offload_ctrl0" "master" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
{ "offload0_enable" "ENABLE"} \
{ "offload0_enabled" "ENABLED"} \
{ "offload0_mem_reset" "MEM_RESET"} \
}
adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
ipx::save_core [ipx::current_core]

13
library/spi_engine/interfaces/spi_engine_ctrl.xml Normal file
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@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>

189
library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml Normal file
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@ -0,0 +1,189 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com"
spirit:library="interface"
spirit:name="spi_engine_ctrl"
spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>CMD_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>

13
library/spi_engine/interfaces/spi_engine_offload_ctrl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_offload_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>

113
library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com"
spirit:library="interface"
spirit:name="spi_engine_offload_ctrl"
spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>CMD_WR_EN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_WR_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_WR_EN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_WR_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ENABLE</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>MEM_RESET</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ENABLED</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>

13
library/spi_engine/interfaces/spi_master.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_master</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>

85
library/spi_engine/interfaces/spi_master_rtl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_master_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com"
spirit:library="interface"
spirit:name="spi_master"
spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>SCLK</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_T</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>THREE_WIRE</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CS</spirit:logicalName>
<spirit:wire>
<spirit:onSlave>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>

42
library/spi_engine/spi_engine_execution/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := spi_engine_execution_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += spi_engine_execution.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: spi_engine_execution.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
spi_engine_execution.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) spi_engine_execution_ip.tcl >> spi_engine_execution_ip.log 2>&1
####################################################################################
####################################################################################

313
library/spi_engine/spi_engine_execution/spi_engine_execution.v Normal file
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module spi_engine_execution (
input clk,
input resetn,
output reg active,
output cmd_ready,
input cmd_valid,
input [15:0] cmd,
input sdo_data_valid,
output reg sdo_data_ready,
input [7:0] sdo_data,
input sdi_data_ready,
output reg sdi_data_valid,
output [7:0] sdi_data,
input sync_ready,
output reg sync_valid,
output [7:0] sync,
output reg sclk,
output sdo,
output reg sdo_t,
input sdi,
output reg [NUM_CS-1:0] cs,
output reg three_wire
);
parameter NUM_CS = 1;
parameter DEFAULT_SPI_CFG = 0;
parameter DEFAULT_CLK_DIV = 0;
localparam CMD_TRANSFER = 2'b00;
localparam CMD_CHIPSELECT = 2'b01;
localparam CMD_WRITE = 2'b10;
localparam CMD_MISC = 2'b11;
localparam MISC_SYNC = 1'b0;
localparam MISC_SLEEP = 1'b1;
localparam REG_CLK_DIV = 1'b0;
localparam REG_CONFIG = 1'b1;
reg idle;
reg [7:0] clk_div_counter = 'h00;
reg [7:0] clk_div_counter_next = 'h00;
reg clk_div_last;
reg [11:0] counter = 'h00;
wire [7:0] sleep_counter = counter[11:4];
wire [1:0] cs_sleep_counter = counter[5:4];
wire [2:0] cs_sleep_counter2 = counter[6:4];
wire [2:0] bit_counter = counter[3:1];
wire [7:0] transfer_counter = counter[11:4];
wire ntx_rx = counter[0];
reg trigger = 1'b0;
reg trigger_next = 1'b0;
reg wait_for_io = 1'b0;
reg transfer_active = 1'b0;
wire last_bit;
wire first_bit;
reg last_transfer;
wire end_of_word;
assign first_bit = bit_counter == 'h0;
assign last_bit = bit_counter == 'h7;
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
reg [15:0] cmd_d1;
reg cpha = DEFAULT_SPI_CFG[0];
reg cpol = DEFAULT_SPI_CFG[1];
reg [7:0] clk_div = DEFAULT_CLK_DIV;
wire sdo_enabled = cmd_d1[8];
wire sdi_enabled = cmd_d1[9];
reg [8:0] data_shift = 'h0;
wire [1:0] inst = cmd[13:12];
wire [1:0] inst_d1 = cmd_d1[13:12];
wire exec_cmd = cmd_ready && cmd_valid;
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
assign cmd_ready = idle;
always @(posedge clk) begin
if (cmd_ready)
cmd_d1 <= cmd;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
active <= 1'b0;
end else begin
if (exec_cmd == 1'b1)
active <= 1'b1;
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
active <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cpha <= DEFAULT_SPI_CFG[0];
cpol <= DEFAULT_SPI_CFG[1];
three_wire <= DEFAULT_SPI_CFG[2];
clk_div <= DEFAULT_CLK_DIV;
end else if (exec_write_cmd == 1'b1) begin
if (cmd[8] == REG_CONFIG) begin
cpha <= cmd[0];
cpol <= cmd[1];
three_wire <= cmd[2];
end else if (cmd[8] == REG_CLK_DIV) begin
clk_div <= cmd[7:0];
end
end
end
always @(posedge clk) begin
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
clk_div_counter == 'h01) || clk_div == 'h00)
clk_div_last <= 1'b1;
else
clk_div_last <= 1'b0;
end
always @(posedge clk) begin
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
clk_div_counter <= clk_div;
trigger <= 1'b1;
end else begin
clk_div_counter <= clk_div_counter - 1'b1;
trigger <= 1'b0;
end
end
wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
wire trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
wire sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
always @(posedge clk) begin
if (idle == 1'b1)
counter <= 'h00;
else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
counter <= counter + (transfer_active ? 'h1 : 'h10);
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle <= 1'b1;
end else begin
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
idle <= 1'b0;
end else begin
case (inst_d1)
CMD_TRANSFER: begin
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
idle <= 1'b1;
end
CMD_CHIPSELECT: begin
if (cs_sleep_counter_compare2)
idle <= 1'b1;
end
CMD_MISC: begin
case (cmd_d1[8])
MISC_SLEEP: begin
if (sleep_counter_compare)
idle <= 1'b1;
end
MISC_SYNC: begin
if (sync_ready)
idle <= 1'b1;
end
endcase
end
endcase
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cs <= 'hff;
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
cs <= cmd_d1[NUM_CS-1:0];
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
sync_valid <= 1'b0;
end else begin
if (exec_sync_cmd == 1'b1) begin
sync_valid <= 1'b1;
end else if (sync_ready == 1'b1) begin
sync_valid <= 1'b0;
end
end
end
assign sync = cmd_d1[7:0];
always @(posedge clk) begin
if (resetn == 1'b0)
sdo_data_ready <= 1'b0;
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
transfer_active == 1'b1)
sdo_data_ready <= 1'b1;
else if (sdo_data_valid == 1'b1)
sdo_data_ready <= 1'b0;
end
always @(posedge clk) begin
if (resetn == 1'b0)
sdi_data_valid <= 1'b0;
else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
transfer_active == 1'b1)
sdi_data_valid <= 1'b1;
else if (sdi_data_ready == 1'b1)
sdi_data_valid <= 1'b0;
end
wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
always @(posedge clk) begin
if (idle == 1'b1) begin
last_transfer <= 1'b0;
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
if (transfer_counter == cmd_d1[7:0])
last_transfer <= 1'b1;
else
last_transfer <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
transfer_active <= 1'b0;
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
if (io_ready2 == 1'b0)
wait_for_io <= 1'b1;
end
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
begin
sdo_t <= ~sdo_enabled;
end else begin
sdo_t <= 1'b1;
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
if (first_bit == 1'b1)
data_shift[8:1] <= sdo_data;
else
data_shift[8:1] <= data_shift[7:0];
end
end
assign sdo = data_shift[8];
assign sdi_data = data_shift[7:0];
always @(posedge clk) begin
if (trigger_rx == 1'b1) begin
data_shift[0] <= sdi;
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1) begin
sclk <= cpol ^ cpha ^ ntx_rx;
end else begin
sclk <= cpol;
end
end
endmodule

46
library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create spi_engine_execution
adi_ip_files spi_engine_execution [list \
"spi_engine_execution.v" \
]
adi_ip_properties_lite spi_engine_execution
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]
adi_add_bus "ctrl" "slave" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync" "SYNC_DATA"} \
}
adi_add_bus_clock "clk" "ctrl" "resetn"
adi_add_bus "spi" "master" \
"analog.com:interface:spi_master_rtl:1.0" \
"analog.com:interface:spi_master:1.0" \
{
{"sclk" "SCLK"} \
{"sdi" "SDI"} \
{"sdo" "SDO"} \
{"sdo_t" "SDO_T"} \
{"three_wire" "THREE_WIRE"} \
{"cs" "CS"} \
}
adi_add_bus_clock "clk" "spi" "resetn"
ipx::save_core [ipx::current_core]

42
library/spi_engine/spi_engine_interconnect/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := spi_engine_interconnect_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += spi_engine_interconnect.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: spi_engine_interconnect.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
spi_engine_interconnect.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) spi_engine_interconnect_ip.tcl >> spi_engine_interconnect_ip.log 2>&1
####################################################################################
####################################################################################

107
library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v Normal file
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module spi_engine_interconnect (
input clk,
input resetn,
output m_cmd_valid,
input m_cmd_ready,
output [15:0] m_cmd_data,
output m_sdo_valid,
input m_sdo_ready,
output [7:0] m_sdo_data,
input m_sdi_valid,
output m_sdi_ready,
input [7:0] m_sdi_data,
input m_sync_valid,
output m_sync_ready,
input [7:0] m_sync,
input s0_cmd_valid,
output s0_cmd_ready,
input [15:0] s0_cmd_data,
input s0_sdo_valid,
output s0_sdo_ready,
input [7:0] s0_sdo_data,
output s0_sdi_valid,
input s0_sdi_ready,
output [7:0] s0_sdi_data,
output s0_sync_valid,
input s0_sync_ready,
output [7:0] s0_sync,
input s1_cmd_valid,
output s1_cmd_ready,
input [15:0] s1_cmd_data,
input s1_sdo_valid,
output s1_sdo_ready,
input [7:0] s1_sdo_data,
output s1_sdi_valid,
input s1_sdi_ready,
output [7:0] s1_sdi_data,
output s1_sync_valid,
input s1_sync_ready,
output [7:0] s1_sync
);
reg s_active = 1'b0;
reg idle = 1'b1;
`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
assign s0_sdi_data = m_sdi_data;
assign s1_sdi_data = m_sdi_data;
assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
assign s0_sync = m_sync;
assign s1_sync = m_sync;
assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
always @(posedge clk) begin
if (idle == 1'b1) begin
if (s0_cmd_valid)
s_active <= 1'b0;
else if (s1_cmd_valid)
s_active <= 1'b1;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle = 1'b1;
end else begin
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
idle <= 1'b1;
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
idle <= 1'b0;
end
end
end
endmodule

54
library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl Normal file
View File

@ -0,0 +1,54 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create spi_engine_interconnect
adi_ip_files spi_engine_interconnect [list \
"spi_engine_interconnect.v" \
]
adi_ip_properties_lite spi_engine_interconnect
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]
adi_add_bus "m_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{ \
{"m_cmd_ready" "CMD_READY"} \
{"m_cmd_valid" "CMD_VALID"} \
{"m_cmd_data" "CMD_DATA"} \
{"m_sdo_ready" "SDO_READY"} \
{"m_sdo_valid" "SDO_VALID"} \
{"m_sdo_data" "SDO_DATA"} \
{"m_sdi_ready" "SDI_READY"} \
{"m_sdi_valid" "SDI_VALID"} \
{"m_sdi_data" "SDI_DATA"} \
{"m_sync_ready" "SYNC_READY"} \
{"m_sync_valid" "SYNC_VALID"} \
{"m_sync" "SYNC_DATA"} \
}
adi_add_bus_clock "clk" "m_ctrl" "resetn"
foreach prefix [list "s0" "s1"] {
adi_add_bus [format "%s_ctrl" $prefix] "slave" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
[list \
[list [format "%s_cmd_ready" $prefix] "CMD_READY"] \
[list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \
[list [format "%s_cmd_data" $prefix] "CMD_DATA"] \
[list [format "%s_sdo_ready" $prefix] "SDO_READY"] \
[list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \
[list [format "%s_sdo_data" $prefix] "SDO_DATA"] \
[list [format "%s_sdi_ready" $prefix] "SDI_READY"] \
[list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \
[list [format "%s_sdi_data" $prefix] "SDI_DATA"] \
[list [format "%s_sync_ready" $prefix] "SYNC_READY"] \
[list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \
[list [format "%s_sync" $prefix] "SYNC_DATA"] \
]
adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn"
}
ipx::save_core [ipx::current_core]

42
library/spi_engine/spi_engine_offload/Makefile Normal file
View File

@ -0,0 +1,42 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := spi_engine_offload_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += spi_engine_offload.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: spi_engine_offload.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
spi_engine_offload.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) spi_engine_offload_ip.tcl >> spi_engine_offload_ip.log 2>&1
####################################################################################
####################################################################################

178
library/spi_engine/spi_engine_offload/spi_engine_offload.v Normal file
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@ -0,0 +1,178 @@
module spi_engine_offload (
input ctrl_clk,
input ctrl_cmd_wr_en,
input [15:0] ctrl_cmd_wr_data,
input ctrl_sdo_wr_en,
input [7:0] ctrl_sdo_wr_data,
input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset,
input spi_clk,
input spi_resetn,
input trigger,
output cmd_valid,
input cmd_ready,
output [15:0] cmd,
output sdo_data_valid,
input sdo_data_ready,
output [7:0] sdo_data,
input sdi_data_valid,
output sdi_data_ready,
input [7:0] sdi_data,
input sync_valid,
output sync_ready,
input [7:0] sync_data,
output offload_sdi_valid,
input offload_sdi_ready,
output [7:0] offload_sdi_data
);
parameter SPI_CLK_ASYNC = 0;
parameter CMD_MEM_ADDR_WIDTH = 4;
parameter SDO_MEM_ADDR_WIDTH = 4;
reg spi_active = 1'b0;
reg [CMD_MEM_ADDR_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
reg [CMD_MEM_ADDR_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
reg [SDO_MEM_ADDR_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
reg [SDO_MEM_ADDR_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDR_WIDTH-1];
reg [7:0] sdo_mem[0:2**SDO_MEM_ADDR_WIDTH-1];
wire [CMD_MEM_ADDR_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
assign cmd_valid = spi_active;
assign sdo_data_valid = spi_active;
assign sync_ready = 1'b1;
assign offload_sdi_valid = sdi_data_valid;
assign sdi_data_ready = offload_sdi_ready;
assign offload_sdi_data = sdi_data;
assign cmd = cmd_mem[spi_cmd_rd_addr];
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
generate if (SPI_CLK_ASYNC) begin
/*
* The synchronization circuit takes care that there are no glitches on the
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
* asserted, but only deasserted once the signal has been synchronized back from
* the SPI domain. This makes sure that we can't end up in a state where the
* enable signal in the SPI domain is asserted, but neither enable nor enabled
* is asserted in the control domain.
*/
reg ctrl_do_enable = 1'b0;
wire ctrl_is_enabled;
reg spi_enabled = 1'b0;
always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin
ctrl_do_enable <= 1'b0;
end
end
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
always @(posedge spi_clk) begin
spi_enabled <= spi_enable | spi_active;
end
sync_bits # (
.NUM_BITS(1),
.CLK_ASYNC(1)
) i_sync_enable (
.in(ctrl_do_enable),
.out_clk(spi_clk),
.out_resetn(1'b1),
.out(spi_enable)
);
sync_bits # (
.NUM_BITS(1),
.CLK_ASYNC(1)
) i_sync_enabled (
.in(spi_enabled),
.out_clk(ctrl_clk),
.out_resetn(1'b1),
.out(ctrl_is_enabled)
);
end else begin
assign spi_enable = ctrl_enable;
assign ctrl_enabled = spi_enable | spi_active;
end endgenerate
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
spi_active <= 1'b0;
end else begin
if (spi_active == 1'b0) begin
if (trigger == 1'b1 && spi_enable == 1'b1)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
spi_active <= 1'b0;
end
end
end
always @(posedge spi_clk) begin
if (cmd_valid == 1'b0) begin
spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end
end
always @(posedge spi_clk) begin
if (spi_active == 1'b0) begin
spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_cmd_wr_en == 1'b1)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_sdo_wr_en == 1'b1)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
end
endmodule

56
library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl Normal file
View File

@ -0,0 +1,56 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create spi_engine_offload
adi_ip_files spi_engine_offload [list \
"spi_engine_offload.v" \
]
adi_ip_properties_lite spi_engine_offload
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]
adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
}
adi_add_bus "spi_engine_offload_ctrl" "slave" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
{ "ctrl_sdo_wr_en" "SDO_WR_EN"} \
{ "ctrl_sdo_wr_data" "SDO_WR_DATA"} \
{ "ctrl_enable" "ENABLE"} \
{ "ctrl_enabled" "ENABLED"} \
{ "ctrl_mem_reset" "MEM_RESET"} \
}
adi_add_bus "offload_sdi" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
{"offload_sdi_valid" "TVALID"} \
{"offload_sdi_ready" "TREADY"} \
{"offload_sdi_data" "TDATA"} \
}
adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn"
adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
ipx::save_core [ipx::current_core]

1
library/util_axis_fifo/Makefile
View File

@ -14,7 +14,6 @@ M_DEPS += address_gray.v
M_DEPS += address_gray_pipelined.v
M_DEPS += address_sync.v
M_DEPS += util_axis_fifo.v
M_DEPS +=
M_VIVADO := vivado -mode batch -source

1
library/util_axis_resize/Makefile
View File

@ -9,7 +9,6 @@ M_DEPS := util_axis_resize_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_axis_resize.v
M_DEPS +=
M_VIVADO := vivado -mode batch -source

3
library/util_axis_resize/util_axis_resize_ip.tcl
View File

@ -3,7 +3,8 @@ source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_axis_resize
adi_ip_files util_axis_resize [list "util_axis_resize.v"]
adi_ip_files util_axis_resize [list \
"util_axis_resize.v" ]
adi_ip_properties_lite util_axis_resize

87
library/util_cpack/util_cpack_hw.tcl Executable file
View File

@ -0,0 +1,87 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME util_cpack
set_module_property DESCRIPTION "Channel Pack Utility"
set_module_property VERSION 1.0
set_module_property DISPLAY_NAME util_cpack
set_module_property ELABORATION_CALLBACK p_util_cpack
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_cpack
add_fileset_file util_cpack_mux.v VERILOG PATH util_cpack_mux.v
add_fileset_file util_cpack_dsf.v VERILOG PATH util_cpack_dsf.v
add_fileset_file util_cpack.v VERILOG PATH util_cpack.v TOP_LEVEL_FILE
# parameters
add_parameter CH_DW INTEGER 0
set_parameter_property CH_DW DEFAULT_VALUE 32
set_parameter_property CH_DW DISPLAY_NAME CH_DW
set_parameter_property CH_DW TYPE INTEGER
set_parameter_property CH_DW UNITS None
set_parameter_property CH_DW HDL_PARAMETER true
add_parameter CH_CNT INTEGER 0
set_parameter_property CH_CNT DEFAULT_VALUE 8
set_parameter_property CH_CNT DISPLAY_NAME CH_CNT
set_parameter_property CH_CNT TYPE INTEGER
set_parameter_property CH_CNT UNITS None
set_parameter_property CH_CNT HDL_PARAMETER true
# defaults
ad_alt_intf clock adc_clk input 1
ad_alt_intf signal adc_rst input 1
ad_alt_intf signal adc_valid output 1
ad_alt_intf signal adc_sync output 1
ad_alt_intf signal adc_data output CH_CNT*CH_DW
ad_alt_intf signal adc_valid_0 input 1
ad_alt_intf signal adc_enable_0 input 1
ad_alt_intf signal adc_data_0 input CH_DW
proc p_util_cpack {} {
if {[get_parameter_value CH_CNT] > 1} {
ad_alt_intf signal adc_valid_1 input 1
ad_alt_intf signal adc_enable_1 input 1
ad_alt_intf signal adc_data_1 input CH_DW
}
if {[get_parameter_value CH_CNT] > 2} {
ad_alt_intf signal adc_valid_2 input 1
ad_alt_intf signal adc_enable_2 input 1
ad_alt_intf signal adc_data_2 input CH_DW
}
if {[get_parameter_value CH_CNT] > 3} {
ad_alt_intf signal adc_valid_3 input 1
ad_alt_intf signal adc_enable_3 input 1
ad_alt_intf signal adc_data_3 input CH_DW
}
if {[get_parameter_value CH_CNT] > 4} {
ad_alt_intf signal adc_valid_4 input 1
ad_alt_intf signal adc_enable_4 input 1
ad_alt_intf signal adc_data_4 input CH_DW
}
if {[get_parameter_value CH_CNT] > 5} {
ad_alt_intf signal adc_valid_5 input 1
ad_alt_intf signal adc_enable_5 input 1
ad_alt_intf signal adc_data_5 input CH_DW
}
if {[get_parameter_value CH_CNT] > 6} {
ad_alt_intf signal adc_valid_6 input 1
ad_alt_intf signal adc_enable_6 input 1
ad_alt_intf signal adc_data_6 input CH_DW
}
if {[get_parameter_value CH_CNT] > 7} {
ad_alt_intf signal adc_valid_7 input 1
ad_alt_intf signal adc_enable_7 input 1
ad_alt_intf signal adc_data_7 input CH_DW
}
}

196
library/axi_ad7175/ad_datafmt.v → library/util_jesd_align/util_jesd_align.v
View File

@ -1,117 +1,79 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// data format (offset binary or 2's complement only)
`timescale 1ps/1ps
module ad_datafmt (
// data path
clk,
valid,
data,
valid_out,
data_out,
// control signals
dfmt_enable,
dfmt_type,
dfmt_se);
// delayed data bus width
parameter DATA_WIDTH = 16;
parameter DATA_WIDTH_OUT = 16;
localparam DW = DATA_WIDTH - 1;
localparam DW1 = DATA_WIDTH_OUT - 1;
// data path
input clk;
input valid;
input [ DW:0] data;
output valid_out;
output [DW1:0] data_out;
// control signals
input dfmt_enable;
input dfmt_type;
input dfmt_se;
// internal registers
reg valid_out = 'd0;
reg [DW1:0] data_out = 'd0;
// internal signals
wire type_s;
wire signext_s;
wire [ DW:0] data_s;
wire [DW1:0] sign_s;
wire [DW1:0] data_out_s;
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
assign signext_s = dfmt_enable & dfmt_se;
assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data;
assign sign_s = (signext_s == 1'b1) ? {{DW1{data_s[DW]}}} : 0;
generate
if (DW == DW1) begin
assign data_out_s = data_s;
end else begin
assign data_out_s = {sign_s[DW1:(DW+1)], data_s};
end
endgenerate
always @(posedge clk) begin
valid_out <= valid;
data_out <= valid ? data_out_s[DW1:0] : data_out;
end
endmodule
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_jesd_align (
// xcvr interface
rx_clk,
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data);
// parameters
parameter NUM_OF_LANES = 2;
// xcvr interface
input rx_clk;
input [ 3:0] rx_ip_sof;
input [((NUM_OF_LANES*32)-1):0] rx_ip_data;
output [((NUM_OF_LANES* 1)-1):0] rx_sof;
output [((NUM_OF_LANES*32)-1):0] rx_data;
// only for altera, xcvr+jesd do not frame align
genvar n;
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data[n*32+31:n*32]),
.rx_sof (rx_sof[n]),
.rx_data (rx_data[n*32+31:n*32]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

0
library/util_jesd_align/util_jesd_align_constr.xdc Normal file
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library/util_jesd_align/util_jesd_align_hw.tcl Normal file
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package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME util_jesd_align
set_module_property DESCRIPTION "JESD Align Utility"
set_module_property VERSION 1.0
set_module_property DISPLAY_NAME util_jesd_align
set_module_property ELABORATION_CALLBACK p_util_jesd_align
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_jesd_align
add_fileset_file ad_jesd_align.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_jesd_align.v
add_fileset_file util_jesd_align.v VERILOG PATH util_jesd_align.v TOP_LEVEL_FILE
# parameters
add_parameter NUM_OF_LANES INTEGER 0
set_parameter_property NUM_OF_LANES DEFAULT_VALUE 2
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
# transceiver interface
add_interface if_rx_clk clock end
add_interface_port if_rx_clk rx_clk clk Input 1
add_interface if_rx_ip_data avalon_streaming end
add_interface_port if_rx_ip_data rx_ip_data data Input 32*NUM_OF_LANES
add_interface if_rx_data avalon_streaming start
add_interface_port if_rx_data rx_data data Output 32*NUM_OF_LANES
ad_alt_intf signal rx_ip_sof input 4 export
ad_alt_intf signal rx_sof output NUM_OF_LANES export
proc p_util_jesd_align {} {
set p_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set_interface_property if_rx_ip_data associatedClock if_rx_clk
set_interface_property if_rx_ip_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
set_interface_property if_rx_data associatedClock if_rx_clk
set_interface_property if_rx_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
}

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