daq3/kcu105: copy
Rejeesh Kutty
parent
b0fef1122e
commit
614babc18e
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/daq2_spi.v
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M_DEPS += ../common/daq2_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
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M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
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M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
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M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
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M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += .Xil
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.PHONY: all lib clean clean-all
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all: lib daq2_kcu105.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_ad9144 clean
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make -C ../../../library/axi_ad9680 clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_jesd_gt clean
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make -C ../../../library/util_adcfifo clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_dacfifo clean
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make -C ../../../library/util_jesd_gt clean
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make -C ../../../library/util_upack clean
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daq2_kcu105.sdk/system_top.hdf: $(M_DEPS)
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rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_ad9144
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make -C ../../../library/axi_ad9680
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_jesd_gt
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make -C ../../../library/util_adcfifo
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make -C ../../../library/util_cpack
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make -C ../../../library/util_dacfifo
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make -C ../../../library/util_jesd_gt
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make -C ../../../library/util_upack
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####################################################################################
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####################################################################################
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@ -0,0 +1,14 @@
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
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p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
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source ../common/daq2_bd.tcl
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set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq2_gt
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set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq2_gt
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set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq2_gt
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@ -0,0 +1,69 @@
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# daq2
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set_property -dict {PACKAGE_PIN H6} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
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set_property -dict {PACKAGE_PIN H5} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
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set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
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set_property -dict {PACKAGE_PIN K6} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
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set_property -dict {PACKAGE_PIN K5} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
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set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
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set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
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set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
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set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
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set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P
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set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N
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set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P
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set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N
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set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N
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set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P
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set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P
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set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N
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set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
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set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
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set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
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# clocks
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create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK]
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# gt pin assignments below are for reference only and are ignored by the tool!
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## set_property -dict {PACKAGE_PIN A4} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
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## set_property -dict {PACKAGE_PIN A3} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
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## set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
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## set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
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## set_property -dict {PACKAGE_PIN B2} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
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## set_property -dict {PACKAGE_PIN B1} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
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## set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
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## set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
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## set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0])
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## set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0])
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## set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
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## set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3])
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## set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1])
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## set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1])
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## set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2])
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## set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2])
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set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}]
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set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}]
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set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}]
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set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_create daq2_kcu105
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adi_project_files daq2_kcu105 [list \
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"../common/daq2_spi.v" \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run daq2_kcu105
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr4_act_n,
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ddr4_addr,
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ddr4_ba,
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ddr4_bg,
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ddr4_ck_p,
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ddr4_ck_n,
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ddr4_cke,
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ddr4_cs_n,
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ddr4_dm_n,
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ddr4_dq,
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ddr4_dqs_p,
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ddr4_dqs_n,
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ddr4_odt,
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ddr4_reset_n,
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mdio_mdc,
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mdio_mdio,
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phy_clk_p,
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phy_clk_n,
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phy_rst_n,
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phy_rx_p,
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phy_rx_n,
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phy_tx_p,
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phy_tx_n,
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fan_pwm,
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gpio_bd,
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iic_scl,
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iic_sda,
|
||||||
|
|
||||||
|
rx_ref_clk_p,
|
||||||
|
rx_ref_clk_n,
|
||||||
|
rx_sysref_p,
|
||||||
|
rx_sysref_n,
|
||||||
|
rx_sync_p,
|
||||||
|
rx_sync_n,
|
||||||
|
rx_data_p,
|
||||||
|
rx_data_n,
|
||||||
|
|
||||||
|
tx_ref_clk_p,
|
||||||
|
tx_ref_clk_n,
|
||||||
|
tx_sysref_p,
|
||||||
|
tx_sysref_n,
|
||||||
|
tx_sync_p,
|
||||||
|
tx_sync_n,
|
||||||
|
tx_data_p,
|
||||||
|
tx_data_n,
|
||||||
|
|
||||||
|
trig_p,
|
||||||
|
trig_n,
|
||||||
|
|
||||||
|
adc_fdb,
|
||||||
|
adc_fda,
|
||||||
|
dac_irq,
|
||||||
|
clkd_status,
|
||||||
|
|
||||||
|
adc_pd,
|
||||||
|
dac_txen,
|
||||||
|
dac_reset,
|
||||||
|
clkd_sync,
|
||||||
|
|
||||||
|
spi_csn_clk,
|
||||||
|
spi_csn_dac,
|
||||||
|
spi_csn_adc,
|
||||||
|
spi_clk,
|
||||||
|
spi_sdio,
|
||||||
|
spi_dir);
|
||||||
|
|
||||||
|
input sys_rst;
|
||||||
|
input sys_clk_p;
|
||||||
|
input sys_clk_n;
|
||||||
|
|
||||||
|
input uart_sin;
|
||||||
|
output uart_sout;
|
||||||
|
|
||||||
|
output ddr4_act_n;
|
||||||
|
output [16:0] ddr4_addr;
|
||||||
|
output [ 1:0] ddr4_ba;
|
||||||
|
output [ 0:0] ddr4_bg;
|
||||||
|
output ddr4_ck_p;
|
||||||
|
output ddr4_ck_n;
|
||||||
|
output [ 0:0] ddr4_cke;
|
||||||
|
output [ 0:0] ddr4_cs_n;
|
||||||
|
inout [ 7:0] ddr4_dm_n;
|
||||||
|
inout [63:0] ddr4_dq;
|
||||||
|
inout [ 7:0] ddr4_dqs_p;
|
||||||
|
inout [ 7:0] ddr4_dqs_n;
|
||||||
|
output [ 0:0] ddr4_odt;
|
||||||
|
output ddr4_reset_n;
|
||||||
|
|
||||||
|
output mdio_mdc;
|
||||||
|
inout mdio_mdio;
|
||||||
|
input phy_clk_p;
|
||||||
|
input phy_clk_n;
|
||||||
|
output phy_rst_n;
|
||||||
|
input phy_rx_p;
|
||||||
|
input phy_rx_n;
|
||||||
|
output phy_tx_p;
|
||||||
|
output phy_tx_n;
|
||||||
|
|
||||||
|
output fan_pwm;
|
||||||
|
|
||||||
|
inout [16:0] gpio_bd;
|
||||||
|
|
||||||
|
inout iic_scl;
|
||||||
|
inout iic_sda;
|
||||||
|
|
||||||
|
input rx_ref_clk_p;
|
||||||
|
input rx_ref_clk_n;
|
||||||
|
input rx_sysref_p;
|
||||||
|
input rx_sysref_n;
|
||||||
|
output rx_sync_p;
|
||||||
|
output rx_sync_n;
|
||||||
|
input [ 3:0] rx_data_p;
|
||||||
|
input [ 3:0] rx_data_n;
|
||||||
|
|
||||||
|
input tx_ref_clk_p;
|
||||||
|
input tx_ref_clk_n;
|
||||||
|
input tx_sysref_p;
|
||||||
|
input tx_sysref_n;
|
||||||
|
input tx_sync_p;
|
||||||
|
input tx_sync_n;
|
||||||
|
output [ 3:0] tx_data_p;
|
||||||
|
output [ 3:0] tx_data_n;
|
||||||
|
|
||||||
|
input trig_p;
|
||||||
|
input trig_n;
|
||||||
|
|
||||||
|
inout adc_fdb;
|
||||||
|
inout adc_fda;
|
||||||
|
inout dac_irq;
|
||||||
|
inout [ 1:0] clkd_status;
|
||||||
|
|
||||||
|
inout adc_pd;
|
||||||
|
inout dac_txen;
|
||||||
|
inout dac_reset;
|
||||||
|
inout clkd_sync;
|
||||||
|
|
||||||
|
output spi_csn_clk;
|
||||||
|
output spi_csn_dac;
|
||||||
|
output spi_csn_adc;
|
||||||
|
output spi_clk;
|
||||||
|
inout spi_sdio;
|
||||||
|
output spi_dir;
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire [63:0] gpio_i;
|
||||||
|
wire [63:0] gpio_o;
|
||||||
|
wire [63:0] gpio_t;
|
||||||
|
wire [ 7:0] spi_csn;
|
||||||
|
wire spi_mosi;
|
||||||
|
wire spi_miso;
|
||||||
|
wire trig;
|
||||||
|
wire rx_ref_clk;
|
||||||
|
wire rx_sysref;
|
||||||
|
wire rx_sync;
|
||||||
|
wire tx_ref_clk;
|
||||||
|
wire tx_sysref;
|
||||||
|
wire tx_sync;
|
||||||
|
|
||||||
|
// spi
|
||||||
|
|
||||||
|
assign spi_csn_adc = spi_csn[2];
|
||||||
|
assign spi_csn_dac = spi_csn[1];
|
||||||
|
assign spi_csn_clk = spi_csn[0];
|
||||||
|
|
||||||
|
// default logic
|
||||||
|
|
||||||
|
assign fan_pwm = 1'b1;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
IBUFDS_GTE3 i_ibufds_rx_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (rx_ref_clk_p),
|
||||||
|
.IB (rx_ref_clk_n),
|
||||||
|
.O (rx_ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_rx_sysref (
|
||||||
|
.I (rx_sysref_p),
|
||||||
|
.IB (rx_sysref_n),
|
||||||
|
.O (rx_sysref));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync (
|
||||||
|
.I (rx_sync),
|
||||||
|
.O (rx_sync_p),
|
||||||
|
.OB (rx_sync_n));
|
||||||
|
|
||||||
|
IBUFDS_GTE3 i_ibufds_tx_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (tx_ref_clk_p),
|
||||||
|
.IB (tx_ref_clk_n),
|
||||||
|
.O (tx_ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_sysref (
|
||||||
|
.I (tx_sysref_p),
|
||||||
|
.IB (tx_sysref_n),
|
||||||
|
.O (tx_sysref));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_sync (
|
||||||
|
.I (tx_sync_p),
|
||||||
|
.IB (tx_sync_n),
|
||||||
|
.O (tx_sync));
|
||||||
|
|
||||||
|
daq2_spi i_spi (
|
||||||
|
.spi_csn (spi_csn[2:0]),
|
||||||
|
.spi_clk (spi_clk),
|
||||||
|
.spi_mosi (spi_mosi),
|
||||||
|
.spi_miso (spi_miso),
|
||||||
|
.spi_sdio (spi_sdio),
|
||||||
|
.spi_dir (spi_dir));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_trig (
|
||||||
|
.I (trig_p),
|
||||||
|
.IB (trig_n),
|
||||||
|
.O (trig));
|
||||||
|
|
||||||
|
assign gpio_i[43] = trig;
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
|
||||||
|
.dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
|
||||||
|
.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
|
||||||
|
.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
|
||||||
|
.dio_p ({ adc_pd, // 42
|
||||||
|
dac_txen, // 41
|
||||||
|
dac_reset, // 40
|
||||||
|
clkd_sync, // 38
|
||||||
|
adc_fdb, // 36
|
||||||
|
adc_fda, // 35
|
||||||
|
dac_irq, // 34
|
||||||
|
clkd_status})); // 32
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
|
||||||
|
.dio_t (gpio_t[16:0]),
|
||||||
|
.dio_i (gpio_o[16:0]),
|
||||||
|
.dio_o (gpio_i[16:0]),
|
||||||
|
.dio_p (gpio_bd));
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.c0_ddr4_act_n (ddr4_act_n),
|
||||||
|
.c0_ddr4_adr (ddr4_addr),
|
||||||
|
.c0_ddr4_ba (ddr4_ba),
|
||||||
|
.c0_ddr4_bg (ddr4_bg),
|
||||||
|
.c0_ddr4_ck_c (ddr4_ck_n),
|
||||||
|
.c0_ddr4_ck_t (ddr4_ck_p),
|
||||||
|
.c0_ddr4_cke (ddr4_cke),
|
||||||
|
.c0_ddr4_cs_n (ddr4_cs_n),
|
||||||
|
.c0_ddr4_dm_n (ddr4_dm_n),
|
||||||
|
.c0_ddr4_dq (ddr4_dq),
|
||||||
|
.c0_ddr4_dqs_c (ddr4_dqs_n),
|
||||||
|
.c0_ddr4_dqs_t (ddr4_dqs_p),
|
||||||
|
.c0_ddr4_odt (ddr4_odt),
|
||||||
|
.c0_ddr4_reset_n (ddr4_reset_n),
|
||||||
|
.gpio0_i (gpio_i[31:0]),
|
||||||
|
.gpio0_o (gpio_o[31:0]),
|
||||||
|
.gpio0_t (gpio_t[31:0]),
|
||||||
|
.gpio1_i (gpio_i[63:32]),
|
||||||
|
.gpio1_o (gpio_o[63:32]),
|
||||||
|
.gpio1_t (gpio_t[63:32]),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.mb_intr_05 (1'b0),
|
||||||
|
.mb_intr_06 (1'b0),
|
||||||
|
.mb_intr_07 (1'b0),
|
||||||
|
.mb_intr_08 (1'b0),
|
||||||
|
.mb_intr_14 (1'b0),
|
||||||
|
.mb_intr_15 (1'b0),
|
||||||
|
.mdio_mdc (mdio_mdc),
|
||||||
|
.mdio_mdio_io (mdio_mdio),
|
||||||
|
.phy_clk_clk_n (phy_clk_n),
|
||||||
|
.phy_clk_clk_p (phy_clk_p),
|
||||||
|
.phy_rst_n (phy_rst_n),
|
||||||
|
.phy_sd (1'b1),
|
||||||
|
.rx_data_n (rx_data_n),
|
||||||
|
.rx_data_p (rx_data_p),
|
||||||
|
.rx_ref_clk (rx_ref_clk),
|
||||||
|
.rx_sync (rx_sync),
|
||||||
|
.rx_sysref (rx_sysref),
|
||||||
|
.sgmii_rxn (phy_rx_n),
|
||||||
|
.sgmii_rxp (phy_rx_p),
|
||||||
|
.sgmii_txn (phy_tx_n),
|
||||||
|
.sgmii_txp (phy_tx_p),
|
||||||
|
.spi_clk_i (spi_clk),
|
||||||
|
.spi_clk_o (spi_clk),
|
||||||
|
.spi_csn_i (spi_csn),
|
||||||
|
.spi_csn_o (spi_csn),
|
||||||
|
.spi_sdi_i (spi_miso),
|
||||||
|
.spi_sdo_i (spi_mosi),
|
||||||
|
.spi_sdo_o (spi_mosi),
|
||||||
|
.sys_clk_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.tx_data_n (tx_data_n),
|
||||||
|
.tx_data_p (tx_data_p),
|
||||||
|
.tx_ref_clk (tx_ref_clk),
|
||||||
|
.tx_sync (tx_sync),
|
||||||
|
.tx_sysref (tx_sysref),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue