diff --git a/library/Makefile b/library/Makefile index 597716b23..9b37b36a3 100644 --- a/library/Makefile +++ b/library/Makefile @@ -28,6 +28,7 @@ clean: $(MAKE) -C axi_ad9739a clean $(MAKE) -C axi_ad9783 clean $(MAKE) -C axi_ad9963 clean + $(MAKE) -C axi_adaq8092 clean $(MAKE) -C axi_adc_decimate clean $(MAKE) -C axi_adc_trigger clean $(MAKE) -C axi_adrv9001 clean @@ -145,6 +146,7 @@ lib: $(MAKE) -C axi_ad9739a $(MAKE) -C axi_ad9783 $(MAKE) -C axi_ad9963 + $(MAKE) -C axi_adaq8092 $(MAKE) -C axi_adc_decimate $(MAKE) -C axi_adc_trigger $(MAKE) -C axi_adrv9001 diff --git a/library/axi_adaq8092/Makefile b/library/axi_adaq8092/Makefile new file mode 100644 index 000000000..09576a9dd --- /dev/null +++ b/library/axi_adaq8092/Makefile @@ -0,0 +1,33 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adaq8092 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_adaq8092.v +GENERIC_DEPS += axi_adaq8092_apb_decode.v +GENERIC_DEPS += axi_adaq8092_channel.v +GENERIC_DEPS += axi_adaq8092_if.v +GENERIC_DEPS += axi_adaq8092_rand_decode.v + +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_adaq8092_ip.tcl + +include ../scripts/library.mk diff --git a/library/axi_adaq8092/axi_adaq8092.v b/library/axi_adaq8092/axi_adaq8092.v new file mode 100644 index 000000000..cf57fa84e --- /dev/null +++ b/library/axi_adaq8092/axi_adaq8092.v @@ -0,0 +1,380 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adaq8092 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter OUTPUT_MODE = 0, + parameter [27:0] POLARITY_MASK ='hfffffff) ( + + // adc interface (clk, data, over-range) + + input adc_clk_in_p, + input adc_clk_in_n, + input [ 6:0] lvds_adc_data_in1_p, + input [ 6:0] lvds_adc_data_in1_n, + input [ 6:0] lvds_adc_data_in2_p, + input [ 6:0] lvds_adc_data_in2_n, + input lvds_adc_or_in_p, + input lvds_adc_or_in_n, + input [13:0] cmos_adc_data_in1, + input [13:0] cmos_adc_data_in2, + input cmos_adc_or_in_1, + input cmos_adc_or_in_2, + + // delay interface + + input delay_clk, + + // dma interface + + output adc_clk, + output adc_rst, + output adc_valid, + output adc_enable_1, + output adc_enable_2, + output [15:0] adc_data_channel1, + output [15:0] adc_data_channel2, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); + + // configuration settings + + localparam CONFIG = (OUTPUT_MODE * 128); + + // internal registers + + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + + // internal clocks & resets + + wire up_rstn; + wire up_clk; + wire delay_rst; + + // internal signals + + wire adc_or_s; + wire [27:0] adc_data_s; + wire [1:0] up_status_or_s; + wire adc_status_s; + wire [29:0] up_dld_s; + wire [149:0] up_dwdata_s; + wire [149:0] up_drdata_s; + wire delay_locked_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:3]; + wire [3:0] up_rack_s ; + wire [3:0] up_wack_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [13:0] adc_decoded_data_s_1; + wire [13:0] adc_decoded_data_s_2; + wire [27:0] adc_part_decoded_data_s; + wire [7:0] adc_custom_control_s; + wire sdr_or_ddr_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_or <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_or <= up_status_or_s[0] | up_status_or_s[1]; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // ADC channel 1 + + axi_adaq8092_channel #( + .CHANNEL_ID(0), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE) + ) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_decoded_data_s_1), + .adc_or (adc_or_s), + .adc_dcfilter_data_out (adc_data_channel1), + .adc_enable (adc_enable_1), + .adc_valid (), + .up_adc_or (up_status_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // ADC channel 2 + + axi_adaq8092_channel #( + .CHANNEL_ID(1), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE) + ) i_channel_2 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_decoded_data_s_2), + .adc_or (adc_or_s), + .adc_dcfilter_data_out (adc_data_channel2), + .adc_enable (adc_enable_2), + .adc_valid (), + .up_adc_or (up_status_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // ADC interface + + axi_adaq8092_rand_decode i_rand ( + .adc_data(adc_data_s), + .adc_clk(adc_clk), + .adc_rand_enb(adc_custom_control_s[0]), + .adc_data_decoded(adc_part_decoded_data_s)); + + axi_adaq8092_apb_decode i_apb ( + .adc_data(adc_part_decoded_data_s), + .adc_clk(adc_clk), + .adc_abp_enb(adc_custom_control_s[1]), + .adc_data_decoded({adc_decoded_data_s_2,adc_decoded_data_s_1})); + + axi_adaq8092_if #( + .OUTPUT_MODE(OUTPUT_MODE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .POLARITY_MASK(POLARITY_MASK) + ) i_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .lvds_adc_data_p({lvds_adc_data_in2_p,lvds_adc_data_in1_p}), + .lvds_adc_data_n({lvds_adc_data_in2_n,lvds_adc_data_in1_n}), + .lvds_adc_or_p(lvds_adc_or_in_p), + .lvds_adc_or_n(lvds_adc_or_in_n), + .cmos_adc_data({cmos_adc_data_in2,cmos_adc_data_in1}), + .cmos_adc_data_or_1(cmos_adc_or_in_1), + .cmos_adc_data_or_2(cmos_adc_or_in_2), + .sdr_or_ddr(sdr_or_ddr_s), + .adc_clk (adc_clk), + .adc_data(adc_data_s), + .adc_or(adc_or_s), + .adc_status (adc_status_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // adc delay control + + up_delay_cntrl #( + .DATA_WIDTH(30), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (CONFIG), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0), + .START_CODE_DISABLE(0) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_custom_control(adc_custom_control_s), + .adc_sdr_ddr_n(sdr_or_ddr_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_num_lanes(), + .adc_symb_op(), + .adc_symb_8_16b(), + + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_adc_ce (), + .up_status_pn_err (), + .up_status_pn_oos (), + .up_status_or (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd0), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_adc_r1_mode(), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/library/axi_adaq8092/axi_adaq8092_apb_decode.v b/library/axi_adaq8092/axi_adaq8092_apb_decode.v new file mode 100644 index 000000000..30a77dc1d --- /dev/null +++ b/library/axi_adaq8092/axi_adaq8092_apb_decode.v @@ -0,0 +1,63 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC ALTERNATE BIT POLARITY DECODE + +`timescale 1ns/100ps + +module axi_adaq8092_apb_decode ( + + input [27:0] adc_data, + input adc_clk, + input adc_abp_enb, + output [27:0] adc_data_decoded); + + // internal registers + + reg [27:0] adc_data_decoded_s; + + // internal variable + + integer i; + + assign adc_data_decoded = adc_abp_enb ? adc_data_decoded_s : adc_data ; + + always @(posedge adc_clk) begin + for (i = 0; i <= 13; i = i + 1) begin + adc_data_decoded_s[2*i+1] = ~adc_data[2*i+1]; + adc_data_decoded_s[2*i] = adc_data[2*i]; + end + end + +endmodule diff --git a/library/axi_adaq8092/axi_adaq8092_channel.v b/library/axi_adaq8092/axi_adaq8092_channel.v new file mode 100644 index 000000000..f38446353 --- /dev/null +++ b/library/axi_adaq8092/axi_adaq8092_channel.v @@ -0,0 +1,168 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_adaq8092_channel #( + + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( + + // adc interface + + input adc_clk, + input adc_rst, + input [13:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + output adc_valid, + output adc_enable, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal signals + + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dfmt_data_s = {2'b0 , adc_data}; + end else begin + ad_datafmt #( + .DATA_WIDTH(14) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data), + .valid_out (), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dcfilter_data_out = adc_dfmt_data_s; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_dfmt_data_s), + .valid_out (adc_valid), + .data_out (adc_dcfilter_data_out), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + up_adc_channel #( + .COMMON_ID (6'h01), + .CHANNEL_ID(CHANNEL_ID), + .USERPORTS_DISABLE (0), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (0), + .IQCORRECTION_DISABLE (0) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (), + .adc_pn_oos (), + .adc_or (adc_or), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd14), + .adc_usr_datatype_bits (8'd14), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/library/axi_adaq8092/axi_adaq8092_if.v b/library/axi_adaq8092/axi_adaq8092_if.v new file mode 100644 index 000000000..608af9081 --- /dev/null +++ b/library/axi_adaq8092/axi_adaq8092_if.v @@ -0,0 +1,297 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface, note that overrange is independent of data path, +// software will not be able to relate overrange to a specific sample! + +`timescale 1ns/100ps + +module axi_adaq8092_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter [27:0] POLARITY_MASK ='hfffffff, + parameter OUTPUT_MODE = 0) ( + + // adc interface (clk, data, over-range) + // nominal clock 80 MHz, up to 105 MHz + + input adc_clk_in_p, + input adc_clk_in_n, + + input [13:0] lvds_adc_data_p, + input [13:0] lvds_adc_data_n, + input lvds_adc_or_p, + input lvds_adc_or_n, + + input [27:0] cmos_adc_data, + input cmos_adc_data_or_1, + input cmos_adc_data_or_2, + + // up control SDR or DDR + + input sdr_or_ddr, + + // interface outputs + + output adc_clk, + output reg [27:0] adc_data, + output reg adc_or, + output reg adc_status, + + // delay control signals + + input up_clk, + input [29:0] up_dld, + input [149:0] up_dwdata, + output [149:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked); + + // internal registers + + reg [27:0] adc_data_s='b0; + + // internal signals + + wire [13:0] lvds_adc_data_p_s; + wire [13:0] lvds_adc_data_n_s; + wire [27:0] cmos_adc_data_p_s; + wire [27:0] cmos_adc_data_n_s; + wire adc_or_s_1; + wire adc_or_s_2; + wire adc_or_s_1_p; + wire adc_or_s_1_n; + wire adc_or_s_2_p; + wire adc_or_s_2_n; + wire [27:0] adc_data_if_out; + + genvar l_inst; + + // LOCAL parameters + + localparam LVDS = 0; + localparam CMOS = 1; + + always @(posedge adc_clk) begin + + adc_status <= 1'b1; + + if (OUTPUT_MODE == LVDS) begin + + adc_or <= adc_or_s_1 | adc_or_s_2; + adc_data <= POLARITY_MASK ^ adc_data_s; + adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13], + lvds_adc_data_n_s[12], lvds_adc_data_p_s[12], + lvds_adc_data_n_s[11], lvds_adc_data_p_s[11], + lvds_adc_data_n_s[10], lvds_adc_data_p_s[10], + lvds_adc_data_n_s[9], lvds_adc_data_p_s[9], + lvds_adc_data_n_s[8], lvds_adc_data_p_s[8], + lvds_adc_data_n_s[7], lvds_adc_data_p_s[7], + lvds_adc_data_n_s[6], lvds_adc_data_p_s[6], + lvds_adc_data_n_s[5], lvds_adc_data_p_s[5], + lvds_adc_data_n_s[4], lvds_adc_data_p_s[4], + lvds_adc_data_n_s[3], lvds_adc_data_p_s[3], + lvds_adc_data_n_s[2], lvds_adc_data_p_s[2], + lvds_adc_data_n_s[1], lvds_adc_data_p_s[1], + lvds_adc_data_n_s[0], lvds_adc_data_p_s[0]}; + + end else if (OUTPUT_MODE == CMOS) begin + adc_data <= adc_data_s; + if (sdr_or_ddr == 0) begin //DDR_CMOS + adc_or <= adc_or_s_1_p | adc_or_s_1_n; + adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27], + cmos_adc_data_n_s[25], cmos_adc_data_p_s[25], + cmos_adc_data_n_s[23], cmos_adc_data_p_s[23], + cmos_adc_data_n_s[21], cmos_adc_data_p_s[21], + cmos_adc_data_n_s[19], cmos_adc_data_p_s[19], + cmos_adc_data_n_s[17], cmos_adc_data_p_s[17], + cmos_adc_data_n_s[15], cmos_adc_data_p_s[15], + cmos_adc_data_n_s[13], cmos_adc_data_p_s[13], + cmos_adc_data_n_s[11], cmos_adc_data_p_s[11], + cmos_adc_data_n_s[9], cmos_adc_data_p_s[9], + cmos_adc_data_n_s[7], cmos_adc_data_p_s[7], + cmos_adc_data_n_s[5], cmos_adc_data_p_s[5], + cmos_adc_data_n_s[3], cmos_adc_data_p_s[3], + cmos_adc_data_n_s[1], cmos_adc_data_p_s[1]}; + end else if (sdr_or_ddr == 1) begin //SDR_CMOS + adc_or <= adc_or_s_1_p | adc_or_s_2_p; + adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26], + cmos_adc_data_p_s[25], cmos_adc_data_p_s[24], + cmos_adc_data_p_s[23], cmos_adc_data_p_s[22], + cmos_adc_data_p_s[21], cmos_adc_data_p_s[20], + cmos_adc_data_p_s[19], cmos_adc_data_p_s[18], + cmos_adc_data_p_s[17], cmos_adc_data_p_s[16], + cmos_adc_data_p_s[15], cmos_adc_data_p_s[14], + cmos_adc_data_p_s[13], cmos_adc_data_p_s[12], + cmos_adc_data_p_s[11], cmos_adc_data_p_s[10], + cmos_adc_data_p_s[9], cmos_adc_data_p_s[8], + cmos_adc_data_p_s[7], cmos_adc_data_p_s[6], + cmos_adc_data_p_s[5], cmos_adc_data_p_s[4], + cmos_adc_data_p_s[3], cmos_adc_data_p_s[2], + cmos_adc_data_p_s[1], cmos_adc_data_p_s[0]}; + end + end + end + + // data interface + + generate + if (OUTPUT_MODE == LVDS) begin + for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if // DDR LVDS INTERFACE + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (lvds_adc_data_p[l_inst]), + .rx_data_in_n (lvds_adc_data_n[l_inst]), + .rx_data_p (lvds_adc_data_p_s[l_inst]), + .rx_data_n (lvds_adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + end else if (OUTPUT_MODE == CMOS) begin + + for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if // CMOS INTERFACE + ad_data_in #( + .SINGLE_ENDED(1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (cmos_adc_data[l_inst]), + .rx_data_in_n (), + .rx_data_p (cmos_adc_data_p_s[l_inst]), + .rx_data_n (cmos_adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + end + endgenerate + + // over-range interface + + if (OUTPUT_MODE == LVDS) begin + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_or_lvds ( + .rx_clk (adc_clk), + .rx_data_in_p (lvds_adc_or_p), + .rx_data_in_n (lvds_adc_or_n), + .rx_data_p (adc_or_s_1), + .rx_data_n (adc_or_s_2), + .up_clk (up_clk), + .up_dld (up_dld[14]), + .up_dwdata (up_dwdata[74:70]), + .up_drdata (up_drdata[74:70]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + end else if (OUTPUT_MODE == CMOS) begin + ad_data_in #( + .SINGLE_ENDED(1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_or_cmos_1 ( + .rx_clk (adc_clk), + .rx_data_in_p (cmos_adc_data_or_1), + .rx_data_in_n (), + .rx_data_p (adc_or_s_1_p), + .rx_data_n (adc_or_s_1_n), + .up_clk (up_clk), + .up_dld (up_dld[28]), + .up_dwdata (up_dwdata[144:140]), + .up_drdata (up_drdata[144:140]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + ad_data_in #( + .SINGLE_ENDED(1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_or_cmos_2 ( + .rx_clk (adc_clk), + .rx_data_in_p (cmos_adc_data_or_2), + .rx_data_in_n (), + .rx_data_p (adc_or_s_2_p), + .rx_data_n (adc_or_s_2_n), + .up_clk (up_clk), + .up_dld (up_dld[29]), + .up_dwdata (up_dwdata[149:145]), + .up_drdata (up_drdata[149:145]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + + // clock + + ad_data_clk i_adc_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk)); + +endmodule diff --git a/library/axi_adaq8092/axi_adaq8092_ip.tcl b/library/axi_adaq8092/axi_adaq8092_ip.tcl new file mode 100644 index 000000000..0abda5162 --- /dev/null +++ b/library/axi_adaq8092/axi_adaq8092_ip.tcl @@ -0,0 +1,65 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_adaq8092 + +adi_ip_files axi_adaq8092 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_adaq8092_if.v" \ + "axi_adaq8092_channel.v" \ + "axi_adaq8092_apb_decode.v"\ + "axi_adaq8092_rand_decode.v"\ + "axi_adaq8092.v" ] + +adi_ip_properties axi_adaq8092 + +adi_init_bd_tcl +adi_ip_bd axi_adaq8092 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/adaq8092} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *adc* -of_objects [ipx::current_core]] + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {LVDS 0 CMOS 1 } \ +] [ipx::get_user_parameters OUTPUT_MODE -of_objects [ipx::current_core]] + +set_property enablement_dependency { $OUTPUT_MODE == 0 } \ + [ipx::get_ports *lvds* -of_objects [ipx::current_core]] +set_property enablement_dependency { $OUTPUT_MODE == 1 } \ + [ipx::get_ports *cmos* -of_objects [ipx::current_core]] + +set_property enablement_tcl_expr {$OUTPUT_MODE == 0} \ + [ipx::get_user_parameters POLARITY_MASK -of_objects [ipx::current_core]] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +set reset_intf [ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] +set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] +set_property value "ACTIVE_HIGH" $reset_polarity + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/library/axi_adaq8092/axi_adaq8092_rand_decode.v b/library/axi_adaq8092/axi_adaq8092_rand_decode.v new file mode 100644 index 000000000..2431fb1b9 --- /dev/null +++ b/library/axi_adaq8092/axi_adaq8092_rand_decode.v @@ -0,0 +1,70 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC DIGITAL OUTPUT RANDOMIZE DECODE + +`timescale 1ns/100ps + +module axi_adaq8092_rand_decode ( + + // data interface + + input [27:0] adc_data, + input adc_clk, + input adc_rand_enb, + output [27:0] adc_data_decoded); + + // internal register + + reg [27:0] adc_data_decoded_s; + + integer i; + + assign adc_data_decoded = adc_rand_enb ? adc_data_decoded_s : adc_data ; + + // DATA DECODING + + always @(posedge adc_clk) begin + for (i = 1; i <= 13; i = i + 1) begin + adc_data_decoded_s[i] = adc_data[i] ^ adc_data[0]; + end + for (i = 15; i <= 27; i = i + 1) begin + adc_data_decoded_s[i] = adc_data[i] ^ adc_data[14]; + end + + adc_data_decoded_s[0] = adc_data[0]; + adc_data_decoded_s[14] = adc_data[14]; + end + +endmodule diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 2f75b9d26..dfdb2510b 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -73,6 +73,7 @@ module up_adc_common #( output adc_ext_sync_disarm, output adc_ext_sync_manual_req, output [4:0] adc_num_lanes, + output [7:0] adc_custom_control, output adc_sdr_ddr_n, output adc_symb_op, output adc_symb_8_16b, @@ -150,6 +151,7 @@ module up_adc_common #( reg [31:0] up_timer = 'd0; reg up_rack_int = 'd0; reg [31:0] up_rdata_int = 'd0; + reg [ 7:0] up_adc_custom_control = 'd0; // internal signals @@ -200,6 +202,7 @@ module up_adc_common #( up_adc_ddr_edgesel <= 'd0; up_adc_pin_mode <= 'd0; up_pps_irq_mask <= 1'b1; + up_adc_custom_control <= 'd0; end else begin up_adc_clk_enb_int <= ~up_adc_clk_enb; up_core_preset <= ~up_resetn; @@ -243,6 +246,8 @@ module up_adc_common #( end end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin up_adc_ext_sync_manual_req <= up_wdata[8]; + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h13)) begin + up_adc_custom_control <= up_wdata[7:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin up_adc_sdr_ddr_n <= up_wdata[16]; @@ -437,6 +442,7 @@ module up_adc_common #( 3'b0, up_adc_ext_sync_manual_req, 4'b0, 1'b0, up_adc_ext_sync_disarm, up_adc_ext_sync_arm, 1'b0}; + 7'h13: up_rdata_int <= {24'd0, up_adc_custom_control}; 7'h15: up_rdata_int <= up_adc_clk_count_s; 7'h16: up_rdata_int <= adc_clk_ratio; 7'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; @@ -469,13 +475,16 @@ module up_adc_common #( // adc control & status - up_xfer_cntrl #(.DATA_WIDTH(49)) i_xfer_cntrl ( + up_xfer_cntrl #( + .DATA_WIDTH(57) + ) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_adc_sdr_ddr_n, up_adc_symb_op, up_adc_symb_8_16b, up_adc_num_lanes, + up_adc_custom_control, up_adc_sref_sync, up_adc_ext_sync_arm, up_adc_ext_sync_disarm, @@ -493,6 +502,7 @@ module up_adc_common #( adc_symb_op, adc_symb_8_16b, adc_num_lanes, + adc_custom_control, adc_sref_sync, adc_ext_sync_arm, adc_ext_sync_disarm, @@ -507,9 +517,12 @@ module up_adc_common #( // De-assert adc_rst together with an updated control set. // This allows writing the control registers before releasing the reset. // This is important at start-up when stable set of controls is required. + assign adc_rst = ~adc_rst_n; - up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status ( + up_xfer_status #( + .DATA_WIDTH(3) + ) i_xfer_status ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_status ({up_sync_status_s, diff --git a/projects/adaq8092_fmc/Makefile b/projects/adaq8092_fmc/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/adaq8092_fmc/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/adaq8092_fmc/Readme.md b/projects/adaq8092_fmc/Readme.md new file mode 100644 index 000000000..60d18ac19 --- /dev/null +++ b/projects/adaq8092_fmc/Readme.md @@ -0,0 +1,8 @@ +# ADAQ8092_FMC HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/adaq8092) + * Parts : [2 Channels, 14-Bit, 105 MSPS, Analog-to-Digital Converter](https://www.analog.com/adaq8092) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/adaq8092 + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/adaq8092 + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl diff --git a/projects/adaq8092_fmc/common/adaq8092_bd.tcl b/projects/adaq8092_fmc/common/adaq8092_bd.tcl new file mode 100644 index 000000000..32f714051 --- /dev/null +++ b/projects/adaq8092_fmc/common/adaq8092_bd.tcl @@ -0,0 +1,81 @@ +#adaq8092 + +create_bd_port -dir I adc_clk_in_p +create_bd_port -dir I adc_clk_in_n + +#interface port create + +create_bd_port -dir I adc_data_or_p +create_bd_port -dir I adc_data_or_n +create_bd_port -dir I -from 6 -to 0 adc_data_in1_p +create_bd_port -dir I -from 6 -to 0 adc_data_in1_n +create_bd_port -dir I -from 6 -to 0 adc_data_in2_p +create_bd_port -dir I -from 6 -to 0 adc_data_in2_n + + # adc peripheral + +ad_ip_instance util_cpack2 axi_adaq8092_cpack [list \ + NUM_OF_CHANNELS 2 \ + SAMPLES_PER_CHANNEL 1 \ + SAMPLE_DATA_WIDTH 16 \ +] + + +ad_ip_instance axi_dmac axi_adaq8092_dma +ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_adaq8092_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_adaq8092_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adaq8092_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_adaq8092_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_DATA_WIDTH_SRC 32 +ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_ip_parameter axi_adaq8092_dma CONFIG.AXI_SLICE_DEST 1 + + # connections + + #adaq8092_core + +ad_ip_instance axi_adaq8092 axi_adaq8092 +ad_ip_parameter axi_adaq8092 CONFIG.POLARITY_MASK 28'hfffffff +ad_ip_parameter axi_adaq8092 CONFIG.OUTPUT_MODE 0 + +ad_connect adc_clk_in_p axi_adaq8092/adc_clk_in_p +ad_connect adc_clk_in_n axi_adaq8092/adc_clk_in_n +ad_connect adc_data_in1_p axi_adaq8092/lvds_adc_data_in1_p +ad_connect adc_data_in1_n axi_adaq8092/lvds_adc_data_in1_n +ad_connect adc_data_in2_p axi_adaq8092/lvds_adc_data_in2_p +ad_connect adc_data_in2_n axi_adaq8092/lvds_adc_data_in2_n +ad_connect adc_data_or_p axi_adaq8092/lvds_adc_or_in_p +ad_connect adc_data_or_n axi_adaq8092/lvds_adc_or_in_n +ad_connect adaq8092_clk axi_adaq8092/adc_clk +ad_connect $sys_iodelay_clk axi_adaq8092/delay_clk + +#adaq8092_cpack + +ad_connect axi_adaq8092/adc_enable_1 axi_adaq8092_cpack/enable_0 +ad_connect axi_adaq8092/adc_data_channel1 axi_adaq8092_cpack/fifo_wr_data_0 +ad_connect axi_adaq8092/adc_enable_2 axi_adaq8092_cpack/enable_1 +ad_connect axi_adaq8092/adc_data_channel2 axi_adaq8092_cpack/fifo_wr_data_1 +ad_connect axi_adaq8092_dma/fifo_wr axi_adaq8092_cpack/packed_fifo_wr +ad_connect axi_adaq8092/adc_valid axi_adaq8092_cpack/fifo_wr_en +ad_connect axi_adaq8092/adc_dovf axi_adaq8092_cpack/fifo_wr_overflow +ad_connect axi_adaq8092/adc_clk axi_adaq8092_cpack/clk +ad_connect axi_adaq8092/adc_clk axi_adaq8092_dma/fifo_wr_clk +ad_connect axi_adaq8092/adc_rst axi_adaq8092_cpack/reset + +# address mapping + +ad_cpu_interconnect 0x44A00000 axi_adaq8092 +ad_cpu_interconnect 0x44A30000 axi_adaq8092_dma + +# interconnect (adc) + +ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect $sys_cpu_clk axi_adaq8092_dma/m_dest_axi +ad_connect $sys_cpu_resetn axi_adaq8092_dma/m_dest_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_adaq8092_dma/irq diff --git a/projects/adaq8092_fmc/zed/Makefile b/projects/adaq8092_fmc/zed/Makefile new file mode 100644 index 000000000..9b75192b1 --- /dev/null +++ b/projects/adaq8092_fmc/zed/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adaq8092_fmc_zed + +M_DEPS += ../common/adaq8092_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_adaq8092 +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer +LIB_DEPS += util_pack/util_cpack2 + +include ../../scripts/project-xilinx.mk diff --git a/projects/adaq8092_fmc/zed/system_bd.tcl b/projects/adaq8092_fmc/zed/system_bd.tcl new file mode 100644 index 000000000..fc1f33a78 --- /dev/null +++ b/projects/adaq8092_fmc/zed/system_bd.tcl @@ -0,0 +1,10 @@ +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source ../common/adaq8092_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file diff --git a/projects/adaq8092_fmc/zed/system_constr.xdc b/projects/adaq8092_fmc/zed/system_constr.xdc new file mode 100644 index 000000000..2eabca57a --- /dev/null +++ b/projects/adaq8092_fmc/zed/system_constr.xdc @@ -0,0 +1,90 @@ +# adaq8092 + +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; #G06 FMC_LPC_LA00_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; #G07 FMC_LPC_LA00_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[0]] ; #H07 FMC_LPC_LA02_P D1_0 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[0]] ; #H08 FMC_LPC_LA02_N D1_1 +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[1]] ; #G09 FMC_LPC_LA03_P D1_2 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[1]] ; #G10 FMC_LPC_LA03_N D1_3 +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[2]] ; #H10 FMC_LPC_LA04_P D1_4 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[2]] ; #H11 FMC_LPC_LA04_N D1_5 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[3]] ; #D11 FMC_LPC_LA05_P D1_6 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[3]] ; #D12 FMC_LPC_LA05_N D1_7 +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[4]] ; #C10 FMC_LPC_LA06_P D1_8 +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[4]] ; #C11 FMC_LPC_LA06_N D1_9 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[5]] ; #H13 FMC_LPC_LA07_P D1_10 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[5]] ; #H14 FMC_LPC_LA07_N D1_11 +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[6]] ; #G12 FMC_LPC_LA08_P D1_12 +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_n[6]] ; #G13 FMC_LPC_LA08_N D1_13 + +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[0]] ; #D14 FMC_LPC_LA09_P D2_0 +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[0]] ; #D15 FMC_LPC_LA09_N D2_1 +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[1]] ; #C14 FMC_LPC_LA10_P D2_2 +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[1]] ; #C15 FMC_LPC_LA10_N D2_3 +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[2]] ; #H16 FMC_LPC_LA11_P D2_4 +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[2]] ; #H17 FMC_LPC_LA11_N D2_5 +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[3]] ; #G15 FMC_LPC_LA12_P D2_6 +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[3]] ; #G16 FMC_LPC_LA12_N D2_7 +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[4]] ; #D17 FMC_LPC_LA13_P D2_8 +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[4]] ; #D18 FMC_LPC_LA13_N D2_9 +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[5]] ; #C18 FMC_LPC_LA14_P D2_10 +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[5]] ; #C19 FMC_LPC_LA14_N D2_11 +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_p[6]] ; #H19 FMC_LPC_LA15_P D2_12 +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in2_n[6]] ; #H20 FMC_LPC_LA15_N D2_13 + +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p] ; #G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n] ; #G19 FMC_LPC_LA16_N + +# spi + +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; #D21 FMC_LPC_LA17_N +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; #C22 FMC_LPC_LA18_P +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; #D20 FMC_LPC_LA17_P +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; #C23 FMC_LPC_LA18_N + +# other + +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports adc_par_ser] ; #G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports en_1p8] ; #H23 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports adc_pd1] ; #H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports adc_pd2] ; #H23 FMC_LPC_LA19_N + +# clocks + +create_clock -name adc_clk_adaq -period 9.523 [get_ports adc_clk_in_p] + +# Input Delay Constraint + +set rise_min 4.761; # period/2 - skew_bre(=0) +set rise_max 5.361; # period/2 + skew_are(=0.6) +set fall_min 4.761; # period/2 - skew_bfe(=0) +set fall_max 5.361; # period/2 - skew_are(=0.6) + +#channel 1 + +set_input_delay -clock adc_clk_adaq -max $rise_max [get_ports adc_data_in1_p[*]]; +set_input_delay -clock adc_clk_adaq -min $rise_min [get_ports adc_data_in1_p[*]]; +set_input_delay -clock adc_clk_adaq -max $fall_max [get_ports adc_data_in1_p[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk_adaq -min $fall_min [get_ports adc_data_in1_p[*]] -clock_fall -add_delay; + +set_input_delay -clock adc_clk_adaq -max $rise_max [get_ports adc_data_in1_n[*]]; +set_input_delay -clock adc_clk_adaq -min $rise_min [get_ports adc_data_in1_n[*]]; +set_input_delay -clock adc_clk_adaq -max $fall_max [get_ports adc_data_in1_n[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk_adaq -min $fall_min [get_ports adc_data_in1_n[*]] -clock_fall -add_delay; + +#channel 2 + +set_input_delay -clock adc_clk_adaq -max $rise_max [get_ports adc_data_in2_p[*]]; +set_input_delay -clock adc_clk_adaq -min $rise_min [get_ports adc_data_in2_p[*]]; +set_input_delay -clock adc_clk_adaq -max $fall_max [get_ports adc_data_in2_p[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk_adaq -min $fall_min [get_ports adc_data_in2_p[*]] -clock_fall -add_delay; + +set_input_delay -clock adc_clk_adaq -max $rise_max [get_ports adc_data_in2_n[*]]; +set_input_delay -clock adc_clk_adaq -min $rise_min [get_ports adc_data_in2_n[*]]; +set_input_delay -clock adc_clk_adaq -max $fall_max [get_ports adc_data_in2_n[*]] -clock_fall -add_delay; +set_input_delay -clock adc_clk_adaq -min $fall_min [get_ports adc_data_in2_n[*]] -clock_fall -add_delay; + +set_input_delay -clock adc_clk_adaq -max $rise_max [get_ports adc_data_or_*]; +set_input_delay -clock adc_clk_adaq -min $rise_min [get_ports adc_data_or_*]; +set_input_delay -clock adc_clk_adaq -max $fall_max [get_ports adc_data_or_*] -clock_fall -add_delay; +set_input_delay -clock adc_clk_adaq -min $fall_min [get_ports adc_data_or_*] -clock_fall -add_delay; diff --git a/projects/adaq8092_fmc/zed/system_project.tcl b/projects/adaq8092_fmc/zed/system_project.tcl new file mode 100644 index 000000000..589260900 --- /dev/null +++ b/projects/adaq8092_fmc/zed/system_project.tcl @@ -0,0 +1,13 @@ +# load script +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project adaq8092_fmc_zed +adi_project_files adaq8092_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "system_top.v" \ + "system_constr.xdc"] + +adi_project_run adaq8092_fmc_zed diff --git a/projects/adaq8092_fmc/zed/system_top.v b/projects/adaq8092_fmc/zed/system_top.v new file mode 100644 index 000000000..cf54e9e8a --- /dev/null +++ b/projects/adaq8092_fmc/zed/system_top.v @@ -0,0 +1,242 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // adc interface + + input adc_clk_in_n, + input adc_clk_in_p, + input [6:0] adc_data_in1_p, + input [6:0] adc_data_in1_n, + input [6:0] adc_data_in2_p, + input [6:0] adc_data_in2_n, + input adc_data_or_p, + input adc_data_or_n, + input adc_par_ser, + output adc_pd1, + output adc_pd2, + output en_1p8, + + // spi interface + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; + + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + // instantiations + + assign spi_csn = spi0_csn[0]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + assign gpio_i[32] = adc_par_ser; + assign adc_pd1 = gpio_o[33]; + assign adc_pd2 = gpio_o[34]; + assign en_1p8 = gpio_o[35]; + + ad_iobuf #( + .DATA_WIDTH(15) + ) iobuf_gpio_bd ( + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_t (gpio_t[14:0]), + .dio_p (gpio_bd[14:0])); + + assign gpio_i[63:33] = gpio_o[63:33]; + assign gpio_i[31:15] = gpio_o[31:15]; + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .adc_clk_in_n(adc_clk_in_n), + .adc_clk_in_p(adc_clk_in_p), + .adc_data_in1_p(adc_data_in1_p), + .adc_data_in1_n(adc_data_in1_n), + .adc_data_in2_p(adc_data_in2_p), + .adc_data_in2_n(adc_data_in2_n), + .adc_data_or_p(adc_data_or_p), + .adc_data_or_n(adc_data_or_n), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (spi1_clk), + .spi1_clk_o (spi1_clk), + .spi1_csn_0_o (spi1_csn[0]), + .spi1_csn_1_o (spi1_csn[1]), + .spi1_csn_2_o (spi1_csn[2]), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b1), + .spi1_sdo_i (spi1_mosi), + .spi1_sdo_o (spi1_mosi), + .spdif (spdif)); + + endmodule