diff --git a/library/util_adc_pack/util_adc_pack.v b/library/util_adc_pack/util_adc_pack.v
index 750cca89c..633a20727 100644
--- a/library/util_adc_pack/util_adc_pack.v
+++ b/library/util_adc_pack/util_adc_pack.v
@@ -138,7 +138,6 @@ module util_adc_pack (
   reg  [7:0]      en4 = 0;
   reg             dvalid = 0;
   reg             chan_valid = 0;
-  reg             chan_valid_d1 = 0;
 
   reg  [(DATA_WIDTH*CHANNELS-1):0]  ddata = 0;
   reg  [(DATA_WIDTH-1):0]           chan_data_0_r;
diff --git a/library/util_adc_pack/util_adc_pack_hw.tcl b/library/util_adc_pack/util_adc_pack_hw.tcl
old mode 100755
new mode 100644
index fadf1dd02..1f07803d0
--- a/library/util_adc_pack/util_adc_pack_hw.tcl
+++ b/library/util_adc_pack/util_adc_pack_hw.tcl
@@ -1,5 +1,4 @@
 
-
 package require -exact qsys 13.0
 source ../scripts/adi_env.tcl
 
@@ -56,34 +55,31 @@ add_interface_port channels_data chan_enable_3 chan_enable_3 Input 1
 add_interface_port channels_data chan_valid_3 chan_valid_3 Input 1
 add_interface_port channels_data chan_data_3 chan_data_3 Input DATA_WIDTH
 
-
-
-
 proc util_adc_pack_elaborate {} {
 
-set DW [ get_parameter_value DATA_WIDTH ]
-set CHAN [ get_parameter_value CHANNELS ]
-add_interface_port channels_data dvalid dvalid Output 1
-add_interface_port channels_data dsync dsync Output 1
-add_interface_port channels_data ddata ddata Output [expr {$DW * $CHAN}]
+  set DW [ get_parameter_value DATA_WIDTH ]
+  set CHAN [ get_parameter_value CHANNELS ]
+  add_interface_port channels_data dvalid dvalid Output 1
+  add_interface_port channels_data dsync dsync Output 1
+  add_interface_port channels_data ddata ddata Output [expr {$DW * $CHAN}]
 
-if {[get_parameter_value CHANNELS] == 8} {
+  if {[get_parameter_value CHANNELS] == 8} {
 
-add_interface_port channels_data chan_enable_4 chan_enable_4 Input 1
-add_interface_port channels_data chan_valid_4 chan_valid_4 Input 1
-add_interface_port channels_data chan_data_4 chan_data_4 Input DATA_WIDTH
+    add_interface_port channels_data chan_enable_4 chan_enable_4 Input 1
+    add_interface_port channels_data chan_valid_4 chan_valid_4 Input 1
+    add_interface_port channels_data chan_data_4 chan_data_4 Input DATA_WIDTH
 
-add_interface_port channels_data chan_enable_5 chan_enable_5 Input 1
-add_interface_port channels_data chan_valid_5 chan_valid_5 Input 1
-add_interface_port channels_data chan_data_5 chan_data_5 Input DATA_WIDTH
+    add_interface_port channels_data chan_enable_5 chan_enable_5 Input 1
+    add_interface_port channels_data chan_valid_5 chan_valid_5 Input 1
+    add_interface_port channels_data chan_data_5 chan_data_5 Input DATA_WIDTH
 
-add_interface_port channels_data chan_enable_6 chan_enable_6 Input 1
-add_interface_port channels_data chan_valid_6 chan_valid_6 Input 1
-add_interface_port channels_data chan_data_6 chan_data_6 Input DATA_WIDTH
+    add_interface_port channels_data chan_enable_6 chan_enable_6 Input 1
+    add_interface_port channels_data chan_valid_6 chan_valid_6 Input 1
+    add_interface_port channels_data chan_data_6 chan_data_6 Input DATA_WIDTH
 
-add_interface_port channels_data chan_enable_7 chan_enable_7 Input 1
-add_interface_port channels_data chan_valid_7 chan_valid_7 Input 1
-add_interface_port channels_data chan_data_7 chan_data_7 Input DATA_WIDTH
+    add_interface_port channels_data chan_enable_7 chan_enable_7 Input 1
+    add_interface_port channels_data chan_valid_7 chan_valid_7 Input 1
+    add_interface_port channels_data chan_data_7 chan_data_7 Input DATA_WIDTH
 }
 
 }
diff --git a/library/util_adc_pack/util_adc_pack_ip.tcl b/library/util_adc_pack/util_adc_pack_ip.tcl
old mode 100755
new mode 100644
diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v
index a27f1abde..17c005ae3 100644
--- a/library/util_dac_unpack/util_dac_unpack.v
+++ b/library/util_dac_unpack/util_dac_unpack.v
@@ -141,7 +141,6 @@ module util_dac_unpack (
   reg [ 15:0] dac_data_07 = 16'h0;
   reg [127:0] buffer_r = 128'h0;
   reg         dma_rd = 1'b0;
-  reg         start = 1'b0;
 
   assign enable_cnt = dac_enable_07 + dac_enable_06 + dac_enable_05 + dac_enable_04 + dac_enable_03 + dac_enable_02 + dac_enable_01 + dac_enable_00;
 
diff --git a/library/util_dac_unpack/util_dac_unpack_hw.tcl b/library/util_dac_unpack/util_dac_unpack_hw.tcl
new file mode 100644
index 000000000..50bbb5f2e
--- /dev/null
+++ b/library/util_dac_unpack/util_dac_unpack_hw.tcl
@@ -0,0 +1,56 @@
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+
+set_module_property NAME util_dac_unpack
+set_module_property DESCRIPTION "Util DAC data unpacker"
+set_module_property VERSION 1.0
+set_module_property DISPLAY_NAME util_dac_unpack
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL util_dac_unpack
+add_fileset_file util_dac_unpack.v   VERILOG PATH util_dac_unpack.v
+
+add_interface data_clock clock end
+add_interface_port data_clock clk clk Input 1
+
+add_interface channels_data conduit end
+set_interface_property channels_data associatedClock data_clock
+add_interface_port channels_data dac_enable_00 dac_enable_00 Input 1
+add_interface_port channels_data dac_valid_00 dac_valid_00 Input 1
+add_interface_port channels_data dac_data_00 dac_data_00 Output 16
+
+add_interface_port channels_data dac_enable_01 dac_enable_01 Input 1
+add_interface_port channels_data dac_valid_01  dac_valid_01 Input 1
+add_interface_port channels_data dac_data_01   dac_data_01 Output 16
+
+add_interface_port channels_data dac_enable_02 dac_enable_02 Input 1
+add_interface_port channels_data dac_valid_02 dac_valid_02 Input 1
+add_interface_port channels_data dac_data_02 dac_data_02 Input 16
+
+add_interface_port channels_data dac_enable_03 dac_enable_03 Input 1
+add_interface_port channels_data dac_valid_03 dac_valid_03 Input 1
+add_interface_port channels_data dac_data_03 dac_data_03 Input 16
+
+add_interface_port channels_data dac_enable_04 dac_enable_04 Input 1
+add_interface_port channels_data dac_valid_04 dac_valid_04 Input 1
+add_interface_port channels_data dac_data_04 dac_data_04 Input 16
+
+add_interface_port channels_data dac_enable_05 dac_enable_05 Input 1
+add_interface_port channels_data dac_valid_05 dac_valid_05 Input 1
+add_interface_port channels_data dac_data_05 dac_data_05 Input 16
+
+add_interface_port channels_data dac_enable_06 dac_enable_06 Input 1
+add_interface_port channels_data dac_valid_06 dac_valid_06 Input 1
+add_interface_port channels_data dac_data_06 dac_data_06 Input 16
+
+add_interface_port channels_data dac_enable_07 dac_enable_07 Input 1
+add_interface_port channels_data dac_valid_07 dac_valid_07 Input 1
+add_interface_port channels_data dac_data_07 dac_data_07 Input 16
+
+add_interface_port channels_data fifo_valid fifo_valid Input 1
+add_interface_port channels_data dma_rd dma_rd Output 1
+add_interface_port channels_data dma_data dma_data Input 128
+
diff --git a/library/util_dac_unpack/util_dac_unpack_ip.tcl b/library/util_dac_unpack/util_dac_unpack_ip.tcl
old mode 100755
new mode 100644
diff --git a/projects/fmcomms2/c5soc/system_bd.qsys b/projects/fmcomms2/c5soc/system_bd.qsys
index f6fb4d5ab..44b4c4419 100644
--- a/projects/fmcomms2/c5soc/system_bd.qsys
+++ b/projects/fmcomms2/c5soc/system_bd.qsys
@@ -16,7 +16,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "8";
          type = "int";
       }
    }
@@ -40,7 +40,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "9";
          type = "int";
       }
    }
@@ -81,6 +81,14 @@
          type = "String";
       }
    }
+   element sys_int_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
    element sys_gpio.s1
    {
       datum _lockedAddress
@@ -94,19 +102,11 @@
          type = "String";
       }
    }
-   element sys_int_mem.s1
+   element axi_ad9361.s_axi
    {
       datum baseAddress
       {
-         value = "0";
-         type = "String";
-      }
-   }
-   element axi_dmac_adc.s_axi
-   {
-      datum baseAddress
-      {
-         value = "0";
+         value = "131072";
          type = "String";
       }
    }
@@ -118,11 +118,11 @@
          type = "String";
       }
    }
-   element axi_ad9361.s_axi
+   element axi_dmac_adc.s_axi
    {
       datum baseAddress
       {
-         value = "131072";
+         value = "0";
          type = "String";
       }
    }
@@ -130,7 +130,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "10";
          type = "int";
       }
    }
@@ -182,11 +182,19 @@
          type = "int";
       }
    }
+   element util_dac_unpack
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
    element vga_clock_video_output
    {
       datum _sortIndex
       {
-         value = "13";
+         value = "14";
          type = "int";
       }
    }
@@ -194,7 +202,7 @@
    {
       datum _sortIndex
       {
-         value = "12";
+         value = "13";
          type = "int";
       }
    }
@@ -202,7 +210,7 @@
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "12";
          type = "int";
       }
    }
@@ -210,7 +218,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "11";
          type = "int";
       }
    }
@@ -349,6 +357,16 @@
    internal="adc_pack.channels_data"
    type="conduit"
    dir="end" />
+ <interface
+   name="util_dac_unpack_data_clock"
+   internal="util_dac_unpack.data_clock"
+   type="clock"
+   dir="end" />
+ <interface
+   name="util_dac_unpack_channels_data"
+   internal="util_dac_unpack.channels_data"
+   type="conduit"
+   dir="end" />
  <module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="clockFrequencyKnown" value="true" />
@@ -926,17 +944,14 @@
  <module kind="axi_ad9361" version="1.0" enabled="1" name="axi_ad9361">
   <parameter name="PCORE_ID" value="0" />
   <parameter name="PCORE_DEVICE_TYPE" value="0" />
-  <parameter name="PCORE_AXI_ID_WIDTH" value="12" />
   <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
   <parameter name="AUTO_DEVICE_CLOCK_CLOCK_RATE" value="0" />
   <parameter name="AUTO_DELAY_CLOCK_CLOCK_RATE" value="50000000" />
  </module>
  <module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_dac">
   <parameter name="PCORE_ID" value="0" />
-  <parameter name="PCORE_AXI_ID_WIDTH" value="12" />
-  <parameter name="PCORE_AXIM_ID_WIDTH" value="3" />
   <parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="C_DMA_DATA_WIDTH_DEST" value="128" />
   <parameter name="C_DMA_LENGTH_WIDTH" value="24" />
   <parameter name="C_2D_TRANSFER" value="0" />
   <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
@@ -952,8 +967,6 @@
  </module>
  <module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_adc">
   <parameter name="PCORE_ID" value="0" />
-  <parameter name="PCORE_AXI_ID_WIDTH" value="12" />
-  <parameter name="PCORE_AXIM_ID_WIDTH" value="3" />
   <parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
   <parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
   <parameter name="C_DMA_LENGTH_WIDTH" value="24" />
@@ -1259,6 +1272,13 @@
   <parameter name="DATA_WIDTH" value="16" />
   <parameter name="AUTO_DATA_CLOCK_CLOCK_RATE" value="0" />
  </module>
+ <module
+   kind="util_dac_unpack"
+   version="1.0"
+   enabled="1"
+   name="util_dac_unpack">
+  <parameter name="AUTO_DATA_CLOCK_CLOCK_RATE" value="0" />
+ </module>
  <connection
    kind="avalon"
    version="14.0"
diff --git a/projects/fmcomms2/c5soc/system_top.v b/projects/fmcomms2/c5soc/system_top.v
index ef389d30c..737bd8c7b 100644
--- a/projects/fmcomms2/c5soc/system_top.v
+++ b/projects/fmcomms2/c5soc/system_top.v
@@ -271,11 +271,22 @@ module system_top (
   wire    [ 15:0]   adc_chan_q1;
   wire    [ 63:0]   adc_ddata;
   wire              adc_dovf;
-  wire              dac_enable;
-  wire              dac_valid;
-  wire              adc_drd;
-  wire    [ 63:0]   dac_ddata;
-  wire              dac_dunf;
+  wire              dac_enable_i0;
+  wire              dac_enable_q0;
+  wire              dac_enable_i1;
+  wire              dac_enable_q1;
+  wire              dac_valid_i0;
+  wire              dac_valid_q0;
+  wire              dac_valid_i1;
+  wire              dac_valid_q1;
+  wire    [ 15:0]   dac_data_i0;
+  wire    [ 15:0]   dac_data_q0;
+  wire    [ 15:0]   dac_data_i1;
+  wire    [ 15:0]   dac_data_q1;
+  wire    [127:0]   dac_ddata;
+  wire              dac_dunf;
+  wire              dac_rd_en;
+  wire              dac_fifo_valid;  
   wire    [111:0]   dev_dbg_data;
   wire    [ 61:0]   dev_l_dbg_data;
   wire              vga_pixel_clock;
@@ -284,8 +295,6 @@ module system_top (
   wire    [7:0]     vid_r,vid_g,vid_b;
 
   // defaults
-
-  assign adc_drd = dac_enable & dac_valid;
   
   assign vga_clk = vga_pixel_clock;
   assign vga_blank_n = 1'b1;
@@ -319,7 +328,7 @@ module system_top (
   i_ila_adc (
     .acq_clk (clk),
     .acq_data_in (adc_ddata),
-    .acq_trigger_in (adc_valid));
+    .acq_trigger_in (adc_valid_i0));
 
   system_bd i_system_bd (
     .clk_clk (sys_clk),
@@ -426,25 +435,25 @@ module system_top (
 		.axi_ad9361_dma_if_adc_data_q1 (adc_chan_q1),
 		.axi_ad9361_dma_if_adc_dovf (adc_dovf),
 		.axi_ad9361_dma_if_adc_dunf (),
-		.axi_ad9361_dma_if_dac_enable_i0 (dac_enable),
-		.axi_ad9361_dma_if_dac_valid_i0 (dac_valid),
-		.axi_ad9361_dma_if_dac_data_i0 (dac_ddata[15:0]),
-		.axi_ad9361_dma_if_dac_enable_q0 (),
-		.axi_ad9361_dma_if_dac_valid_q0 (),
-		.axi_ad9361_dma_if_dac_data_q0 (dac_ddata[31:16]),
-		.axi_ad9361_dma_if_dac_enable_i1 (),
-		.axi_ad9361_dma_if_dac_valid_i1 (),
-		.axi_ad9361_dma_if_dac_data_i1 (dac_ddata[47:32]),
-		.axi_ad9361_dma_if_dac_enable_q1 (),
-		.axi_ad9361_dma_if_dac_valid_q1 (),
-		.axi_ad9361_dma_if_dac_data_q1 (dac_ddata[63:48]),
+		.axi_ad9361_dma_if_dac_enable_i0 (dac_enable_i0),
+		.axi_ad9361_dma_if_dac_valid_i0 (dac_valid_i0),
+		.axi_ad9361_dma_if_dac_data_i0 (dac_data_i0),
+		.axi_ad9361_dma_if_dac_enable_q0 (dac_enable_q0),
+		.axi_ad9361_dma_if_dac_valid_q0 (dac_valid_q0),
+		.axi_ad9361_dma_if_dac_data_q0 (dac_data_q0),
+		.axi_ad9361_dma_if_dac_enable_i1 (dac_enable_i1),
+		.axi_ad9361_dma_if_dac_valid_i1 (dac_valid_i1),
+		.axi_ad9361_dma_if_dac_data_i1 (dac_data_i1),
+		.axi_ad9361_dma_if_dac_enable_q1 (dac_enable_q1),
+		.axi_ad9361_dma_if_dac_valid_q1 (dac_valid_q1),
+		.axi_ad9361_dma_if_dac_data_q1 (dac_data_q1),
 		.axi_ad9361_dma_if_dac_dovf (),
 		.axi_ad9361_dma_if_dac_dunf (dac_dunf),
 		.axi_ad9361_debug_if_dev_dbg_data (dev_dbg_data),
 		.axi_ad9361_debug_if_dev_l_dbg_data (dev_l_dbg_data),
 		.axi_dmac_dac_fifo_rd_clock_clk (clk),
-		.axi_dmac_dac_fifo_rd_if_rden (adc_drd),
-		.axi_dmac_dac_fifo_rd_if_valid (),
+		.axi_dmac_dac_fifo_rd_if_rden (dac_rd_en),
+		.axi_dmac_dac_fifo_rd_if_valid (dac_fifo_valid),
 		.axi_dmac_dac_fifo_rd_if_data (dac_ddata),
 		.axi_dmac_dac_fifo_rd_if_unf (dac_dunf),
 		.axi_dmac_adc_fifo_wr_clock_clk (clk),
@@ -481,7 +490,36 @@ module system_top (
 		.adc_pack_channels_data_chan_data_3 (adc_chan_q1),
 		.adc_pack_channels_data_dvalid (adc_dwr),
 		.adc_pack_channels_data_dsync (adc_dsync),
-		.adc_pack_channels_data_ddata (adc_ddata));
+		.adc_pack_channels_data_ddata (adc_ddata),
+		.util_dac_unpack_data_clock_clk                     (clk),
+      .util_dac_unpack_channels_data_dac_enable_00        (dac_enable_i0), 
+      .util_dac_unpack_channels_data_dac_valid_00         (dac_valid_i0),
+      .util_dac_unpack_channels_data_dac_data_00          (dac_data_i0),
+      .util_dac_unpack_channels_data_dac_enable_01        (dac_enable_q0), 
+      .util_dac_unpack_channels_data_dac_valid_01         (dac_valid_q0),
+      .util_dac_unpack_channels_data_dac_data_01          (dac_data_q0),
+      .util_dac_unpack_channels_data_dac_enable_02        (dac_enable_i1),
+      .util_dac_unpack_channels_data_dac_valid_02         (dac_valid_i1),
+      .util_dac_unpack_channels_data_dac_data_02          (dac_data_i1),
+      .util_dac_unpack_channels_data_dac_enable_03        (dac_enable_q1),
+      .util_dac_unpack_channels_data_dac_valid_03         (dac_valid_q1),
+      .util_dac_unpack_channels_data_dac_data_03          (dac_data_q1),
+      .util_dac_unpack_channels_data_dac_enable_04        (1'b0),
+      .util_dac_unpack_channels_data_dac_valid_04         (1'b0),
+      .util_dac_unpack_channels_data_dac_data_04          (),
+      .util_dac_unpack_channels_data_dac_enable_05        (1'b0),
+      .util_dac_unpack_channels_data_dac_valid_05         (1'b0),
+      .util_dac_unpack_channels_data_dac_data_05          (),
+      .util_dac_unpack_channels_data_dac_enable_06        (1'b0),
+      .util_dac_unpack_channels_data_dac_valid_06         (1'b0),
+      .util_dac_unpack_channels_data_dac_data_06          (),
+      .util_dac_unpack_channels_data_dac_enable_07        (1'b0),
+      .util_dac_unpack_channels_data_dac_valid_07         (1'b0),
+      .util_dac_unpack_channels_data_dac_data_07          (),
+      .util_dac_unpack_channels_data_fifo_valid           (dac_fifo_valid),
+      .util_dac_unpack_channels_data_dma_rd               (dac_rd_en),
+      .util_dac_unpack_channels_data_dma_data             (dac_ddata)
+    );
 
 endmodule