fmcomms2: Updated vc707 project

- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
main
Adrian Costina 2014-11-26 11:25:19 +02:00
parent 2f77daf71d
commit 6227bc82c0
3 changed files with 84 additions and 75 deletions

View File

@ -60,8 +60,5 @@ set_property -dict {PACKAGE_PIN H31 IOSTANDARD LVCMOS18} [get_ports spi_miso]
# clocks # clocks
create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p] create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
set_clock_groups -asynchronous -group {ad9361_clk}

View File

@ -8,6 +8,7 @@ adi_project_create fmcomms2_vc707
adi_project_files fmcomms2_vc707 [list \ adi_project_files fmcomms2_vc707 [list \
"system_top.v" \ "system_top.v" \
"system_constr.xdc"\ "system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
adi_project_run fmcomms2_vc707 adi_project_run fmcomms2_vc707

View File

@ -1,9 +1,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2011(c) Analog Devices, Inc.
// //
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without modification, // Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met: // are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright // - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software. // patent holders to use this software.
// - Use of the software either in source or binary form, must be run // - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component. // on or directly connected to an Analog Devices Inc. component.
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. // PARTICULAR PURPOSE ARE DISCLAIMED.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
@ -63,6 +63,13 @@ module system_top (
ddr3_reset_n, ddr3_reset_n,
ddr3_we_n, ddr3_we_n,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_oen,
linear_flash_wen,
linear_flash_dq_io,
sgmii_rxp, sgmii_rxp,
sgmii_rxn, sgmii_rxn,
sgmii_txp, sgmii_txp,
@ -91,21 +98,21 @@ module system_top (
hdmi_data, hdmi_data,
spdif, spdif,
rx_clk_in_p, rx_clk_in_p,
rx_clk_in_n, rx_clk_in_n,
rx_frame_in_p, rx_frame_in_p,
rx_frame_in_n, rx_frame_in_n,
rx_data_in_p, rx_data_in_p,
rx_data_in_n, rx_data_in_n,
tx_clk_out_p, tx_clk_out_p,
tx_clk_out_n, tx_clk_out_n,
tx_frame_out_p, tx_frame_out_p,
tx_frame_out_n, tx_frame_out_n,
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, gpio_txnrx,
gpio_enable, gpio_enable,
gpio_resetb, gpio_resetb,
@ -117,7 +124,7 @@ module system_top (
spi_csn, spi_csn,
spi_clk, spi_clk,
spi_mosi, spi_mosi,
spi_miso spi_miso
); );
input sys_rst; input sys_rst;
@ -143,6 +150,7 @@ module system_top (
output ddr3_reset_n; output ddr3_reset_n;
output ddr3_we_n; output ddr3_we_n;
input sgmii_rxp; input sgmii_rxp;
input sgmii_rxn; input sgmii_rxn;
output sgmii_txp; output sgmii_txp;
@ -156,6 +164,13 @@ module system_top (
output fan_pwm; output fan_pwm;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
output linear_flash_oen;
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
output [ 6:0] gpio_lcd; output [ 6:0] gpio_lcd;
output [ 7:0] gpio_led; output [ 7:0] gpio_led;
input [12:0] gpio_sw; input [12:0] gpio_sw;
@ -171,14 +186,14 @@ module system_top (
output [35:0] hdmi_data; output [35:0] hdmi_data;
output spdif; output spdif;
input rx_clk_in_p; input rx_clk_in_p;
input rx_clk_in_n; input rx_clk_in_n;
input rx_frame_in_p; input rx_frame_in_p;
input rx_frame_in_n; input rx_frame_in_n;
input [ 5:0] rx_data_in_p; input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n; input [ 5:0] rx_data_in_n;
output tx_clk_out_p; output tx_clk_out_p;
output tx_clk_out_n; output tx_clk_out_n;
output tx_frame_out_p; output tx_frame_out_p;
@ -193,67 +208,33 @@ module system_top (
inout gpio_en_agc; inout gpio_en_agc;
inout [ 3:0] gpio_ctl; inout [ 3:0] gpio_ctl;
inout [ 7:0] gpio_status; inout [ 7:0] gpio_status;
output spi_csn; output spi_csn;
output spi_clk; output spi_clk;
output spi_mosi; output spi_mosi;
input spi_miso; input spi_miso;
// internal signals // internal signals
wire [16:0] gpio_i; wire [16:0] gpio_i;
wire [16:0] gpio_o; wire [16:0] gpio_o;
wire [16:0] gpio_t; wire [16:0] gpio_t;
wire [31:0] mb_intrs;
assign fan_pwm = 1'b1;
// instantiations // instantiations
IOBUF i_iobuf_gpio_txnrx (
.I (gpio_o[16]),
.O (gpio_i[16]),
.T (gpio_t[16]),
.IO (gpio_txnrx));
IOBUF i_iobuf_gpio_enable ( ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.I (gpio_o[15]), .dt (gpio_t[16:0]),
.O (gpio_i[15]), .di (gpio_o[16:0]),
.T (gpio_t[15]), .do (gpio_i[16:0]),
.IO (gpio_enable)); .dio({ gpio_txnrx,
gpio_enable,
IOBUF i_iobuf_gpio_resetb ( gpio_resetb,
.I (gpio_o[14]), gpio_sync,
.O (gpio_i[14]), gpio_en_agc,
.T (gpio_t[14]), gpio_ctl,
.IO (gpio_resetb)); gpio_status}));
IOBUF i_iobuf_gpio_sync (
.I (gpio_o[13]),
.O (gpio_i[13]),
.T (gpio_t[13]),
.IO (gpio_sync));
IOBUF i_iobuf_gpio_en_agc (
.I (gpio_o[12]),
.O (gpio_i[12]),
.T (gpio_t[12]),
.IO (gpio_en_agc));
genvar n;
generate
for (n = 0; n <= 3; n = n + 1) begin: g_iobuf_gpio_ctl
IOBUF i_iobuf_gpio_ctl (
.I (gpio_o[8+n]),
.O (gpio_i[8+n]),
.T (gpio_t[8+n]),
.IO (gpio_ctl[n]));
end
for (n = 0; n <= 7; n = n + 1) begin: g_iobuf_gpio_status
IOBUF i_iobuf_gpio_status (
.I (gpio_o[0+n]),
.O (gpio_i[0+n]),
.T (gpio_t[0+n]),
.IO (gpio_status[n]));
end
endgenerate
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr), .ddr3_addr (ddr3_addr),
@ -271,7 +252,12 @@ module system_top (
.ddr3_ras_n (ddr3_ras_n), .ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n), .ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n), .ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm), .linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.linear_flash_dq_io(linear_flash_dq_io),
.gpio_lcd_tri_o (gpio_lcd), .gpio_lcd_tri_o (gpio_lcd),
.gpio_led_tri_o (gpio_led), .gpio_led_tri_o (gpio_led),
.gpio_sw_tri_i (gpio_sw), .gpio_sw_tri_i (gpio_sw),
@ -286,6 +272,32 @@ module system_top (
.iic_main_scl_io (iic_scl), .iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda), .iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn), .iic_rstn (iic_rstn),
.mb_intr_10 (mb_intrs[10]),
.mb_intr_11 (mb_intrs[11]),
.mb_intr_12 (mb_intrs[12]),
.mb_intr_13 (mb_intrs[13]),
.mb_intr_14 (mb_intrs[14]),
.mb_intr_15 (mb_intrs[15]),
.mb_intr_16 (mb_intrs[16]),
.mb_intr_17 (mb_intrs[17]),
.mb_intr_18 (mb_intrs[18]),
.mb_intr_19 (mb_intrs[19]),
.mb_intr_20 (mb_intrs[20]),
.mb_intr_21 (mb_intrs[21]),
.mb_intr_22 (mb_intrs[22]),
.mb_intr_23 (mb_intrs[23]),
.mb_intr_24 (mb_intrs[24]),
.mb_intr_25 (mb_intrs[25]),
.mb_intr_26 (mb_intrs[26]),
.mb_intr_27 (mb_intrs[27]),
.mb_intr_28 (mb_intrs[28]),
.mb_intr_29 (mb_intrs[29]),
.mb_intr_30 (mb_intrs[30]),
.mb_intr_31 (mb_intrs[31]),
.fmcomms2_spi_irq(mb_intrs[10]),
.fmcomms2_gpio_irq(mb_intrs[11]),
.ad9361_adc_dma_irq (mb_intrs[12]),
.ad9361_dac_dma_irq (mb_intrs[13]),
.mdio_mdc (mdio_mdc), .mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio), .mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n), .mgt_clk_clk_n (mgt_clk_n),
@ -300,7 +312,7 @@ module system_top (
.sys_clk_p (sys_clk_p), .sys_clk_p (sys_clk_p),
.sys_rst (sys_rst), .sys_rst (sys_rst),
.spi_csn_i (1'b1), .spi_csn_i (1'b1),
.spi_csn_o (spi_csn), .spi_csn_o (spi_csn),
.spi_miso_i (spi_miso), .spi_miso_i (spi_miso),
.spi_mosi_i (1'b0), .spi_mosi_i (1'b0),
.spi_mosi_o (spi_mosi), .spi_mosi_o (spi_mosi),
@ -311,16 +323,15 @@ module system_top (
.rx_data_in_n (rx_data_in_n), .rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p), .rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n), .rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p), .rx_frame_in_p (rx_frame_in_p),
.tx_clk_out_n (tx_clk_out_n), .tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p), .tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n), .tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p), .tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin), .uart_sin (uart_sin),
.uart_sout (uart_sout), .uart_sout (uart_sout));
.unc_int4 (1'b0));
endmodule endmodule