Ip automatic version update: common/board

- vc707 - zc702 - zed
2017-04-12 18:50:42 +03:00 · 2017-04-12 18:50:42 +03:00 · 627f78ec19
parent 3f0633aadc
commit 627f78ec19
3 changed files with 152 additions and 148 deletions
--- a/projects/common/vc707/vc707_system_bd.tcl
+++ b/projects/common/vc707/vc707_system_bd.tcl
@ -49,101 +49,102 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]

 # instance: microblaze - processor

-set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb]
-set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
-set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
+ad_ip_instance microblaze sys_mb
+ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4
+ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1

 # instance: microblaze - local memory & bus

-set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
-set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
+ad_ip_instance lmb_v10 sys_dlmb
+ad_ip_instance lmb_v10 sys_ilmb

-set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
-set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
+ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr
+ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC 0

-set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
-set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
+ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr
+ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC 0

-set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
-set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
+ad_ip_instance blk_mem_gen sys_lmb_bram
+ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM
+ad_ip_parameter sys_lmb_bram  CONFIG.use_bram_block BRAM_Controller

 # instance: microblaze- mdm

-set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 sys_mb_debug]
-set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
+ad_ip_instance mdm sys_mb_debug
+ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1

 # instance: system reset/clocks

-set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
+ad_ip_instance proc_sys_reset sys_rstgen

 # instance: ddr (mig)

-set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
-set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
+ad_ip_instance mig_7series axi_ddr_cntrl
+set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]]
 file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/"
-set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl
+ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE vc707_system_mig.prj
+ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE Custom

 # instance: default peripherals

-set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
-set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
-set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
-set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
-set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
-set_property -dict [list CONFIG.RXMEM {8k}] $axi_ethernet
+ad_ip_instance axi_ethernet axi_ethernet
+ad_ip_parameter axi_ethernet CONFIG.PHY_TYPE SGMII
+ad_ip_parameter axi_ethernet CONFIG.TXCSUM Full
+ad_ip_parameter axi_ethernet CONFIG.RXCSUM Full
+ad_ip_parameter axi_ethernet CONFIG.TXMEM 8k
+ad_ip_parameter axi_ethernet CONFIG.RXMEM 8k

-set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
-set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
-set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
-set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
+ad_ip_instance axi_dma axi_ethernet_dma
+ad_ip_parameter axi_ethernet_dma CONFIG.c_include_mm2s_dre 1
+ad_ip_parameter axi_ethernet_dma CONFIG.c_sg_use_stsapp_length 1
+ad_ip_parameter axi_ethernet_dma CONFIG.c_include_s2mm_dre 1

-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+ad_ip_instance axi_iic axi_iic_main

-set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
-set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
+ad_ip_instance axi_uartlite axi_uart
+ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200

-set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
+ad_ip_instance axi_timer axi_timer

-set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd]
-set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd
-set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd
+ad_ip_instance axi_gpio axi_gpio_lcd
+ad_ip_parameter axi_gpio_lcd CONFIG.C_GPIO_WIDTH 7
+ad_ip_parameter axi_gpio_lcd CONFIG.C_INTERRUPT_PRESENT 1

-set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi]
-set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_spi
-set_property -dict [list CONFIG.C_NUM_SS_BITS {8}] $axi_spi
-set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi
+ad_ip_instance axi_quad_spi axi_spi
+ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0
+ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8
+ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8

-set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio]
-set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio
-set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio
-set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio
-set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio
+ad_ip_instance axi_gpio axi_gpio
+ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1
+ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32
+ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32
+ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1

 # instance: interrupt

-set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
-set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
+ad_ip_instance axi_intc axi_intc
+ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0

-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+ad_ip_instance xlconcat sys_concat_intc
+ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16

 # linear flash

-set axi_linear_flash [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_linear_flash]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_linear_flash
-set_property -dict [list CONFIG.EMC_BOARD_INTERFACE {linear_flash}] $axi_linear_flash
-set_property -dict [list CONFIG.C_MEM0_TYPE {2}] $axi_linear_flash
-set_property -dict [list CONFIG.C_S_AXI_MEM_ID_WIDTH {0}] $axi_linear_flash
-set_property -dict [list CONFIG.C_THZCE_PS_MEM_0 {7000}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TLZWE_PS_MEM_0 {0}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TWC_PS_MEM_0 {15000}] $axi_linear_flash
-set_property -dict [list CONFIG.C_WR_REC_TIME_MEM_0 {0}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TWP_PS_MEM_0 {40000}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TWPH_PS_MEM_0 {20000}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TPACC_PS_FLASH_0 {15000}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TCEDV_PS_MEM_0 {96000}] $axi_linear_flash
-set_property -dict [list CONFIG.C_TAVDV_PS_MEM_0 {96000}] $axi_linear_flash
+ad_ip_instance axi_emc axi_linear_flash
+ad_ip_parameter axi_linear_flash CONFIG.USE_BOARD_FLOW true
+ad_ip_parameter axi_linear_flash CONFIG.EMC_BOARD_INTERFACE linear_flash
+ad_ip_parameter axi_linear_flash CONFIG.C_MEM0_TYPE 2
+ad_ip_parameter axi_linear_flash CONFIG.C_S_AXI_MEM_ID_WIDTH 0
+ad_ip_parameter axi_linear_flash CONFIG.C_THZCE_PS_MEM_0 7000
+ad_ip_parameter axi_linear_flash CONFIG.C_TLZWE_PS_MEM_0 0
+ad_ip_parameter axi_linear_flash CONFIG.C_TWC_PS_MEM_0 15000
+ad_ip_parameter axi_linear_flash CONFIG.C_WR_REC_TIME_MEM_0 0
+ad_ip_parameter axi_linear_flash CONFIG.C_TWP_PS_MEM_0 40000
+ad_ip_parameter axi_linear_flash CONFIG.C_TWPH_PS_MEM_0 20000
+ad_ip_parameter axi_linear_flash CONFIG.C_TPACC_PS_FLASH_0 15000
+ad_ip_parameter axi_linear_flash CONFIG.C_TCEDV_PS_MEM_0 96000
+ad_ip_parameter axi_linear_flash CONFIG.C_TAVDV_PS_MEM_0 96000

 # connections

--- a/projects/common/zc702/zc702_system_bd.tcl
+++ b/projects/common/zc702/zc702_system_bd.tcl
@ -61,54 +61,56 @@ create_bd_port -dir I -type intr ps_intr_13

 # instance: sys_ps7

-set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC702}] $sys_ps7
-set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+ad_ip_instance processing_system7 sys_ps7
+ad_ip_parameter sys_ps7 CONFIG.PCW_IMPORT_BOARD_PRESET ZC702
+ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
+ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
+ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP0 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA0 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO

-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
+ad_ip_instance axi_iic axi_iic_main
+ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true
+ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE IIC_MAIN

-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+ad_ip_instance xlconcat sys_concat_intc
+ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16

-set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
-set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+ad_ip_instance proc_sys_reset sys_rstgen
+ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1

 # hdmi peripherals

-set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
-set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+ad_ip_instance axi_clkgen axi_hdmi_clkgen
+ad_ip_instance axi_hdmi_tx axi_hdmi_core

-set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
-set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
-set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
-set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
+ad_ip_instance axi_vdma axi_hdmi_dma
+ad_ip_parameter axi_hdmi_dma CONFIG.c_m_axis_mm2s_tdata_width 64
+ad_ip_parameter axi_hdmi_dma CONFIG.c_use_mm2s_fsync 1
+ad_ip_parameter axi_hdmi_dma CONFIG.c_include_s2mm 0

 # audio peripherals

-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
-set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
-set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
+ad_ip_instance clk_wiz sys_audio_clkgen
+ad_ip_parameter sys_audio_clkgen CONFIG.PRIM_IN_FREQ 200.000
+ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 12.288
+ad_ip_parameter sys_audio_clkgen CONFIG.USE_LOCKED false
+ad_ip_parameter sys_audio_clkgen CONFIG.USE_RESET true
+ad_ip_parameter sys_audio_clkgen CONFIG.RESET_TYPE ACTIVE_LOW

-set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
-set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
-set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
+ad_ip_instance axi_spdif_tx axi_spdif_tx_core
+ad_ip_parameter axi_spdif_tx_core CONFIG.DMA_TYPE 1
+ad_ip_parameter axi_spdif_tx_core CONFIG.S_AXI_ADDRESS_WIDTH 16

 # system reset/clock definitions

--- a/projects/common/zed/zed_system_bd.tcl
+++ b/projects/common/zed/zed_system_bd.tcl
@ -76,72 +76,73 @@ create_bd_port -dir I -type intr ps_intr_13

 # instance: sys_ps7

-set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
-set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7
-set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
-set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
+ad_ip_instance processing_system7 sys_ps7
+ad_ip_parameter sys_ps7 CONFIG.PCW_IMPORT_BOARD_PRESET ZedBoard
+ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
+ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
+ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP0 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA0 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA1 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA2 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1
+ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO

-set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
-set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_main
-set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
+ad_ip_instance axi_iic axi_iic_main
+ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true
+ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE Custom

-set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
+ad_ip_instance util_i2c_mixer sys_i2c_mixer

-set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
+ad_ip_instance xlconcat sys_concat_intc
+ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16

-set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
-set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
+ad_ip_instance proc_sys_reset sys_rstgen
+ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1

-set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
-set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
-set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
+ad_ip_instance util_vector_logic sys_logic_inv
+ad_ip_parameter sys_logic_inv CONFIG.C_SIZE 1
+ad_ip_parameter sys_logic_inv CONFIG.C_OPERATION not

 # hdmi peripherals

-set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
-set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+ad_ip_instance axi_clkgen axi_hdmi_clkgen
+ad_ip_instance axi_hdmi_tx axi_hdmi_core

-set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
-set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
-set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
-set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
+ad_ip_instance axi_vdma axi_hdmi_dma
+ad_ip_parameter axi_hdmi_dma CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH 64
+ad_ip_parameter axi_hdmi_dma CONFIG.C_USE_MM2S_FSYNC 1
+ad_ip_parameter axi_hdmi_dma CONFIG.C_INCLUDE_S2MM 0

 # audio peripherals

-set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
-set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
-set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
-set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
+ad_ip_instance clk_wiz sys_audio_clkgen
+ad_ip_parameter sys_audio_clkgen CONFIG.PRIM_IN_FREQ 200.000
+ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 12.288
+ad_ip_parameter sys_audio_clkgen CONFIG.USE_LOCKED false
+ad_ip_parameter sys_audio_clkgen CONFIG.USE_RESET true
+ad_ip_parameter sys_audio_clkgen CONFIG.RESET_TYPE ACTIVE_LOW

-set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
-set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
-set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
+ad_ip_instance axi_spdif_tx axi_spdif_tx_core
+ad_ip_parameter axi_spdif_tx_core CONFIG.DMA_TYPE 1
+ad_ip_parameter axi_spdif_tx_core CONFIG.S_AXI_ADDRESS_WIDTH 16

-set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
-set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
-set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
+ad_ip_instance axi_i2s_adi axi_i2s_adi
+ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 1
+ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 16

 # iic (fmc)

-set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_fmc]
+ad_ip_instance axi_iic axi_iic_fmc

 # system reset/clock definitions