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adaq7980_sdz: Initial commit 

The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
main
Istvan Csomortani 2017-01-04 12:23:56 +02:00
parent a4c422ac4c
commit 63cab50872
6 changed files with 438 additions and 0 deletions
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88
projects/adaq7980_sdz/common/adaq7980_bd.tcl Normal file
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
# create a SPI Engine architecture
create_bd_cell -type hier spi
current_bd_instance /spi
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution]
set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi]
set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload]
set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect]
set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi]
set_property -dict [list CONFIG.DATA_WIDTH 16] $spi_engine_offload
set_property -dict [list CONFIG.DATA_WIDTH 16] $axi_spi_engine
set_property -dict [list CONFIG.DATA_WIDTH 16] $spi_engine_interconnect
set_property -dict [list CONFIG.DATA_WIDTH 16] $spi_engine
set_property -dict [list CONFIG.NUM_OF_CS 1] $spi_engine
set_property -dict [list CONFIG.NUM_OF_CS 1] $util_sigma_delta_spi
set_property -dict [list CONFIG.NUM_OFFLOAD 1] $axi_spi_engine
ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
ad_connect interconnect/m_ctrl execution/ctrl
ad_connect offload/offload_sdi M_AXIS_SAMPLE
ad_connect util_sigma_delta_spi/data_ready offload/trigger
ad_connect execution/active util_sigma_delta_spi/spi_active
ad_connect execution/spi util_sigma_delta_spi/s_spi
ad_connect util_sigma_delta_spi/m_spi m_spi
ad_connect clk offload/spi_clk
ad_connect clk offload/ctrl_clk
ad_connect clk execution/clk
ad_connect clk axi/s_axi_aclk
ad_connect clk axi/spi_clk
ad_connect clk interconnect/clk
ad_connect clk util_sigma_delta_spi/clk
ad_connect axi/spi_resetn offload/spi_resetn
ad_connect axi/spi_resetn execution/resetn
ad_connect axi/spi_resetn interconnect/resetn
ad_connect axi/spi_resetn util_sigma_delta_spi/resetn
ad_connect resetn axi/s_axi_aresetn
ad_connect irq axi/irq
current_bd_instance /
set axi_adaq7980_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_adaq7980_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_adaq7980_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_adaq7980_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_adaq7980_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_adaq7980_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_adaq7980_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_adaq7980_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_adaq7980_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_adaq7980_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_adaq7980_dma
ad_connect sys_cpu_clk spi/clk
ad_connect sys_cpu_resetn spi/resetn
ad_connect sys_cpu_resetn axi_adaq7980_dma/m_dest_axi_aresetn
ad_connect spi/m_spi spi
ad_connect axi_adaq7980_dma/s_axis spi/M_AXIS_SAMPLE
ad_cpu_interconnect 0x44a00000 spi/axi
ad_cpu_interconnect 0x44a30000 axi_adaq7980_dma
ad_connect sys_cpu_clk axi_adaq7980_dma/s_axis_aclk
ad_cpu_interrupt "ps-13" "mb-13" axi_adaq7980_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" spi/irq
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_adaq7980_dma/m_dest_axi

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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/adaq7980_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
M_DEPS += ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
M_DEPS += ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
M_DEPS += ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
M_DEPS += ../../../library/util_sigma_delta_spi/util_sigma_delta_spi.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib adaq7980_sdz_zed.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/spi_engine/axi_spi_engine clean
make -C ../../../library/spi_engine/spi_engine_execution clean
make -C ../../../library/spi_engine/spi_engine_interconnect clean
make -C ../../../library/spi_engine/spi_engine_offload clean
make -C ../../../library/util_i2c_mixer clean
make -C ../../../library/util_sigma_delta_spi clean
adaq7980_sdz_zed.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> adaq7980_sdz_zed_vivado.log 2>&1
lib:
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_spdif_tx
make -C ../../../library/spi_engine/axi_spi_engine
make -C ../../../library/spi_engine/spi_engine_execution
make -C ../../../library/spi_engine/spi_engine_interconnect
make -C ../../../library/spi_engine/spi_engine_offload
make -C ../../../library/util_i2c_mixer
make -C ../../../library/util_sigma_delta_spi
####################################################################################
####################################################################################

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projects/adaq7980_sdz/zed/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/adaq7980_bd.tcl

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# SPI interface
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports spi_sdi] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA15_P
# GPIO signals
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[2]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[3]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[4]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[5]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[6]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports adaq7980_gpio[7]] ; ## FMC_LPC_LA27_N
# REF_PD and RBUF_PD
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports adaq7980_ref_pd] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports adaq7980_rbuf_pd] ; ## FMC_LPC_LA29_P

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projects/adaq7980_sdz/zed/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create adaq7980_sdz_zed
adi_project_files adaq7980_sdz_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run adaq7980_sdz_zed

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projects/adaq7980_sdz/zed/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2016(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
input spi_sdi,
output spi_sclk,
output spi_cs,
inout [ 7:0] adaq7980_gpio,
inout adaq7980_rbuf_pd,
inout adaq7980_ref_pd);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_pd (
.dio_t(gpio_t[41:40]),
.dio_i(gpio_o[41:40]),
.dio_o(gpio_i[41:40]),
.dio_p({adaq7980_rbuf_pd, adaq7980_ref_pd}));
ad_iobuf #(
.DATA_WIDTH(8)
) i_iobuf_gpio (
.dio_t(gpio_t[39:32]),
.dio_i(gpio_o[39:32]),
.dio_o(gpio_i[39:32]),
.dio_p(adaq7980_gpio));
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spi_sdo (),
.spi_sdo_t (),
.spi_sdi (spi_sdi),
.spi_cs (spi_cs),
.spi_sclk (spi_sclk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************