fmcomms7: Move project to a feature branch
Istvan Csomortani
István Csomortáni
parent
05ce6dea26
commit
6458e825e9
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@ -1,6 +0,0 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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@ -1,206 +0,0 @@
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# spi2
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ad_ip_instance axi_quad_spi axi_fmcomms7_spi
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ad_ip_parameter axi_fmcomms7_spi CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_fmcomms7_spi CONFIG.C_NUM_SS_BITS 12
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ad_ip_parameter axi_fmcomms7_spi CONFIG.C_SCK_RATIO 8
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# connections (spi2)
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create_bd_port -dir O -from 11 -to 0 spi2_csn_o
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create_bd_port -dir I -from 11 -to 0 spi2_csn_i
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create_bd_port -dir I spi2_clk_i
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create_bd_port -dir O spi2_clk_o
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create_bd_port -dir I spi2_sdo_i
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create_bd_port -dir O spi2_sdo_o
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create_bd_port -dir I spi2_sdi_i
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ad_connect spi2_csn_i axi_fmcomms7_spi/ss_i
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ad_connect spi2_csn_o axi_fmcomms7_spi/ss_o
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ad_connect spi2_clk_i axi_fmcomms7_spi/sck_i
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ad_connect spi2_clk_o axi_fmcomms7_spi/sck_o
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ad_connect spi2_sdo_i axi_fmcomms7_spi/io0_i
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ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o
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ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i
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ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_ad9144_xcvr
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ad_ip_parameter axi_ad9144_xcvr CONFIG.NUM_OF_LANES 8
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ad_ip_parameter axi_ad9144_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_ad9144_xcvr CONFIG.TX_OR_RX_N 1
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ad_ip_instance jesd204 axi_ad9144_jesd
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ad_ip_parameter axi_ad9144_jesd CONFIG.C_NODE_IS_TRANSMIT 1
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ad_ip_parameter axi_ad9144_jesd CONFIG.C_LANES 8
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ad_ip_instance axi_ad9144 axi_ad9144_core
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ad_ip_parameter axi_ad9144_core CONFIG.QUAD_OR_DUAL_N 1
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ad_ip_instance axi_dmac axi_ad9144_dma
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ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_ad9144_dma CONFIG.ID 1
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ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9144_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9144_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9144_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_SRC 256
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ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_DEST 256
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ad_ip_instance util_upack axi_ad9144_upack
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ad_ip_parameter axi_ad9144_upack CONFIG.CHANNEL_DATA_WIDTH 64
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ad_ip_parameter axi_ad9144_upack CONFIG.NUM_OF_CHANNELS 4
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad9680_xcvr
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ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
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ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_instance jesd204 axi_ad9680_jesd
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ad_ip_parameter axi_ad9680_jesd CONFIG.C_NODE_IS_TRANSMIT 0
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ad_ip_parameter axi_ad9680_jesd CONFIG.C_LANES 4
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ad_ip_instance axi_ad9680 axi_ad9680_core
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ad_ip_instance axi_dmac axi_ad9680_dma
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_instance util_cpack axi_ad9680_cpack
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ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
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ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 2
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# dac/adc common gt
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ad_ip_instance util_adxcvr util_fmcomms7_xcvr
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ad_ip_parameter util_fmcomms7_xcvr CONFIG.RX_NUM_OF_LANES 4
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ad_ip_parameter util_fmcomms7_xcvr CONFIG.TX_NUM_OF_LANES 8
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# reference clocks & resets
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create_bd_port -dir I tx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_0
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ad_xcvrpll tx_ref_clk_0 util_fmcomms7_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcomms7_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_fmcomms7_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcomms7_xcvr/up_cpll_rst_*
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ad_connect sys_cpu_resetn util_fmcomms7_xcvr/up_rstn
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ad_connect sys_cpu_clk util_fmcomms7_xcvr/up_clk
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# connections (dac)
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ad_xcvrcon util_fmcomms7_xcvr axi_ad9144_xcvr axi_ad9144_jesd
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ad_reconct util_fmcomms7_xcvr/tx_0 axi_ad9144_jesd/gt5_tx
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ad_reconct util_fmcomms7_xcvr/tx_1 axi_ad9144_jesd/gt3_tx
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ad_reconct util_fmcomms7_xcvr/tx_2 axi_ad9144_jesd/gt6_tx
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ad_reconct util_fmcomms7_xcvr/tx_3 axi_ad9144_jesd/gt7_tx
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ad_reconct util_fmcomms7_xcvr/tx_4 axi_ad9144_jesd/gt2_tx
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ad_reconct util_fmcomms7_xcvr/tx_5 axi_ad9144_jesd/gt0_tx
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ad_reconct util_fmcomms7_xcvr/tx_6 axi_ad9144_jesd/gt1_tx
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ad_reconct util_fmcomms7_xcvr/tx_7 axi_ad9144_jesd/gt4_tx
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ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
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ad_connect axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
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ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
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ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
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ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
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ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
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ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1
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ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1
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ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
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ad_connect axi_ad9144_core/dac_enable_2 axi_ad9144_upack/dac_enable_2
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ad_connect axi_ad9144_core/dac_ddata_2 axi_ad9144_upack/dac_data_2
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ad_connect axi_ad9144_core/dac_valid_2 axi_ad9144_upack/dac_valid_2
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ad_connect axi_ad9144_core/dac_enable_3 axi_ad9144_upack/dac_enable_3
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ad_connect axi_ad9144_core/dac_ddata_3 axi_ad9144_upack/dac_data_3
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ad_connect axi_ad9144_core/dac_valid_3 axi_ad9144_upack/dac_valid_3
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ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
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ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_fifo/dac_rst
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ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
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ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
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ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk
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ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst
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ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
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ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req
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ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
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ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
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ad_connect axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
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ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
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# connections (adc)
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ad_xcvrcon util_fmcomms7_xcvr axi_ad9680_xcvr axi_ad9680_jesd
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ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
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ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
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ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
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ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
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ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
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ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
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ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
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ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
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ad_cpu_interconnect 0x44A00000 axi_ad9144_core
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ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
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ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9680_core
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ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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ad_cpu_interconnect 0x44A80000 axi_fmcomms7_spi
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9144_dma/m_src_axi
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-9 mb-9 axi_ad9144_dma/irq
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ad_cpu_interrupt ps-10 mb-10 axi_ad9680_dma/irq
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ad_cpu_interrupt ps-12 mb-12 axi_fmcomms7_spi/ip2intc_irpt
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ad_connect axi_ad9144_fifo/bypass GND
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@ -1,98 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module fmcomms7_spi (
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input [ 2:0] spi_csn,
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input spi_clk,
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input spi_mosi,
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output spi_miso,
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inout spi_sdio,
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output spi_dir);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_dir = ~spi_enable_s;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if (spi_count == 6'd16) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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// io butter
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IOBUF i_iobuf_sdio (
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.T (spi_enable_s),
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.I (spi_mosi),
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.O (spi_miso),
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.IO (spi_sdio));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,30 +0,0 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := fmcomms7_zc706
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M_DEPS += ../common/fmcomms7_spi.v
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M_DEPS += ../common/fmcomms7_bd.tcl
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M_DEPS += ../../common/zc706/zc706_system_constr.xdc
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M_DEPS += ../../common/zc706/zc706_system_bd.tcl
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M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
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M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl
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M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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LIB_DEPS += axi_ad9144
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LIB_DEPS += axi_ad9680
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_cpack
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LIB_DEPS += util_dacfifo
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LIB_DEPS += util_upack
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LIB_DEPS += xilinx/axi_adcfifo
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
|
||||
|
||||
include ../../scripts/project-xilinx.mk
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
|
||||
set adc_fifo_name axi_ad9680_fifo
|
||||
set adc_fifo_address_width 16
|
||||
set adc_data_width 128
|
||||
set adc_dma_data_width 64
|
||||
|
||||
set dac_fifo_name axi_ad9144_fifo
|
||||
set dac_fifo_address_width 10
|
||||
set dac_data_width 256
|
||||
set dac_dma_data_width 256
|
||||
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
|
||||
source ../common/fmcomms7_bd.tcl
|
||||
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
# fmcomms7
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[5])
|
||||
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[5])
|
||||
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
|
||||
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3])
|
||||
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[6])
|
||||
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[6])
|
||||
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[7])
|
||||
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[7])
|
||||
set_property -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[4]] ; ## A34 FMC_HPC_DP4_C2M_P (tx_data_p[2])
|
||||
set_property -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[4]] ; ## A35 FMC_HPC_DP4_C2M_N (tx_data_n[2])
|
||||
set_property -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[5]] ; ## A38 FMC_HPC_DP5_C2M_P (tx_data_p[0])
|
||||
set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[5]] ; ## A39 FMC_HPC_DP5_C2M_N (tx_data_n[0])
|
||||
set_property -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[6]] ; ## B36 FMC_HPC_DP6_C2M_P (tx_data_p[1])
|
||||
set_property -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[6]] ; ## B37 FMC_HPC_DP6_C2M_N (tx_data_n[1])
|
||||
set_property -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[7]] ; ## B32 FMC_HPC_DP7_C2M_P (tx_data_p[4])
|
||||
set_property -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[7]] ; ## B33 FMC_HPC_DP7_C2M_N (tx_data_n[4])
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync0_p] ; ## H07 FMC_HPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync0_n] ; ## H08 FMC_HPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync1_p] ; ## H19 FMC_HPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync1_n] ; ## H20 FMC_HPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
|
||||
|
||||
# spi (clock, dac and adc only & sdio)
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## C10 FMC_HPC_LA06_P
|
||||
|
||||
# spi (others, sdi and/or sdo)
|
||||
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1] ; ## H22 FMC_HPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2] ; ## H23 FMC_HPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1] ; ## H25 FMC_HPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2] ; ## H26 FMC_HPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3] ; ## G19 FMC_HPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1] ; ## D20 FMC_HPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2] ; ## D21 FMC_HPC_LA17_CC_N
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1] ; ## G21 FMC_HPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2] ; ## G22 FMC_HPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports spi2_clk] ; ## C26 FMC_HPC_LA27_P
|
||||
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports spi2_sdo] ; ## C27 FMC_HPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2] ; ## D18 FMC_HPC_LA13_N
|
||||
|
||||
# external trigger
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
|
||||
|
||||
# clock gpio
|
||||
|
||||
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports clk_gpio[0]] ; ## G27 FMC_HPC_LA25_P
|
||||
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports clk_gpio[1]] ; ## G28 FMC_HPC_LA25_N
|
||||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports clk_gpio[2]] ; ## H28 FMC_HPC_LA24_P
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports clk_gpio[3]] ; ## H29 FMC_HPC_LA24_N
|
||||
|
||||
# status
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G13 FMC_HPC_LA08_N
|
||||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports adf4355_1_ld] ; ## D26 FMC_HPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports adf4355_2_ld] ; ## D27 FMC_HPC_LA26_N
|
||||
|
||||
# control
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports xo_en] ; ## G18 FMC_HPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clk_sync] ; ## G12 FMC_HPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_txen0] ; ## G15 FMC_HPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen1] ; ## G16 FMC_HPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset] ; ## G24 FMC_HPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset] ; ## G25 FMC_HPC_LA22_N
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports hmc349_sel] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports hmc922_a] ; ## D23 FMC_HPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b] ; ## D24 FMC_HPC_LA23_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
|
||||
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
|
||||
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_xilinx fmcomms7_zc706
|
||||
adi_project_files fmcomms7_zc706 [list \
|
||||
"../common/fmcomms7_spi.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
set_property is_enabled false [get_files *system_axi*_spi*.xdc]
|
||||
adi_project_run fmcomms7_zc706
|
||||
|
||||
|
||||
|
|
@ -1,422 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [ 14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [ 31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [ 53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [ 14:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [ 23:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
input sys_rst,
|
||||
input sys_clk_p,
|
||||
input sys_clk_n,
|
||||
|
||||
output [ 13:0] ddr3_addr,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_cas_n,
|
||||
output [ 0:0] ddr3_ck_n,
|
||||
output [ 0:0] ddr3_ck_p,
|
||||
output [ 0:0] ddr3_cke,
|
||||
output [ 0:0] ddr3_cs_n,
|
||||
output [ 7:0] ddr3_dm,
|
||||
inout [ 63:0] ddr3_dq,
|
||||
inout [ 7:0] ddr3_dqs_n,
|
||||
inout [ 7:0] ddr3_dqs_p,
|
||||
output [ 0:0] ddr3_odt,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_we_n,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
|
||||
input rx_ref_clk_p,
|
||||
input rx_ref_clk_n,
|
||||
input rx_sysref_p,
|
||||
input rx_sysref_n,
|
||||
output rx_sync_p,
|
||||
output rx_sync_n,
|
||||
input [ 3:0] rx_data_p,
|
||||
input [ 3:0] rx_data_n,
|
||||
|
||||
input tx_ref_clk_p,
|
||||
input tx_ref_clk_n,
|
||||
input tx_sysref_p,
|
||||
input tx_sysref_n,
|
||||
input tx_sync0_p,
|
||||
input tx_sync0_n,
|
||||
input tx_sync1_p,
|
||||
input tx_sync1_n,
|
||||
output [ 7:0] tx_data_p,
|
||||
output [ 7:0] tx_data_n,
|
||||
|
||||
input trig_p,
|
||||
input trig_n,
|
||||
|
||||
output spi_csn_clk,
|
||||
output spi_csn_dac,
|
||||
output spi_csn_adc,
|
||||
output spi_clk,
|
||||
inout spi_sdio,
|
||||
output spi_dir,
|
||||
|
||||
output spi2_csn_adf4355_1,
|
||||
output spi2_csn_adf4355_2,
|
||||
output spi2_csn_hmc1044_1,
|
||||
output spi2_csn_hmc1044_2,
|
||||
output spi2_csn_hmc1044_3,
|
||||
output spi2_csn_adl5240_1,
|
||||
output spi2_csn_adl5240_2,
|
||||
output spi2_csn_hmc271_1,
|
||||
output spi2_csn_hmc271_2,
|
||||
output spi2_clk,
|
||||
output spi2_sdo,
|
||||
input spi2_sdi_hmc271_1,
|
||||
input spi2_sdi_hmc271_2,
|
||||
|
||||
inout [ 3:0] clk_gpio,
|
||||
inout adc_fda,
|
||||
inout adc_fdb,
|
||||
inout dac_irq,
|
||||
inout adf4355_1_ld,
|
||||
inout adf4355_2_ld,
|
||||
inout xo_en,
|
||||
inout clk_sync,
|
||||
inout adf4355_2_pd,
|
||||
inout dac_txen0,
|
||||
inout dac_txen1,
|
||||
inout hmc271_1_reset,
|
||||
inout hmc271_2_reset,
|
||||
inout hmc349_sel,
|
||||
inout hmc922_a,
|
||||
inout hmc922_b);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_drd = 'd0;
|
||||
reg [ 63:0] dac_ddata_0 = 'd0;
|
||||
reg [ 63:0] dac_ddata_1 = 'd0;
|
||||
reg [ 63:0] dac_ddata_2 = 'd0;
|
||||
reg [ 63:0] dac_ddata_3 = 'd0;
|
||||
reg adc_dsync = 'd0;
|
||||
reg adc_dwr = 'd0;
|
||||
reg [127:0] adc_ddata = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 63:0] gpio_i;
|
||||
wire [ 63:0] gpio_o;
|
||||
wire [ 63:0] gpio_t;
|
||||
wire [ 2:0] spi0_csn;
|
||||
wire spi0_clk;
|
||||
wire spi0_mosi;
|
||||
wire spi0_miso;
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_clk;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
wire [ 11:0] spi2_csn;
|
||||
wire spi2_mosi;
|
||||
wire spi2_miso;
|
||||
wire trig;
|
||||
wire rx_ref_clk;
|
||||
wire rx_sysref;
|
||||
wire rx_sync;
|
||||
wire tx_ref_clk;
|
||||
wire tx_sysref;
|
||||
wire tx_sync0;
|
||||
wire tx_sync1;
|
||||
wire tx_sync;
|
||||
|
||||
// spi
|
||||
|
||||
assign spi_csn_adc = spi0_csn[2];
|
||||
assign spi_csn_dac = spi0_csn[1];
|
||||
assign spi_csn_clk = spi0_csn[0];
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (rx_ref_clk_p),
|
||||
.IB (rx_ref_clk_n),
|
||||
.O (rx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_rx_sysref (
|
||||
.I (rx_sysref_p),
|
||||
.IB (rx_sysref_n),
|
||||
.O (rx_sysref));
|
||||
|
||||
OBUFDS i_obufds_rx_sync (
|
||||
.I (rx_sync),
|
||||
.O (rx_sync_p),
|
||||
.OB (rx_sync_n));
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_tx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (tx_ref_clk_p),
|
||||
.IB (tx_ref_clk_n),
|
||||
.O (tx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_tx_sysref (
|
||||
.I (tx_sysref_p),
|
||||
.IB (tx_sysref_n),
|
||||
.O (tx_sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_sync0 (
|
||||
.I (tx_sync0_p),
|
||||
.IB (tx_sync0_n),
|
||||
.O (tx_sync0));
|
||||
|
||||
IBUFDS i_ibufds_tx_sync1 (
|
||||
.I (tx_sync1_p),
|
||||
.IB (tx_sync1_n),
|
||||
.O (tx_sync1));
|
||||
|
||||
assign tx_sync = tx_sync0 & tx_sync1;
|
||||
|
||||
fmcomms7_spi i_spi (
|
||||
.spi_csn (spi0_csn),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi0_mosi),
|
||||
.spi_miso (spi0_miso),
|
||||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
IBUFDS i_ibufds_trig (
|
||||
.I (trig_p),
|
||||
.IB (trig_n),
|
||||
.O (trig));
|
||||
|
||||
assign spi2_csn_adf4355_1 = spi2_csn[0];
|
||||
assign spi2_csn_adf4355_2 = spi2_csn[1];
|
||||
assign spi2_csn_hmc1044_1 = spi2_csn[2];
|
||||
assign spi2_csn_hmc1044_2 = spi2_csn[3];
|
||||
assign spi2_csn_hmc1044_3 = spi2_csn[4];
|
||||
assign spi2_csn_adl5240_1 = spi2_csn[5];
|
||||
assign spi2_csn_adl5240_2 = spi2_csn[6];
|
||||
assign spi2_csn_hmc271_1 = spi2_csn[7];
|
||||
assign spi2_csn_hmc271_2 = spi2_csn[8];
|
||||
assign spi2_sdo = spi2_mosi;
|
||||
assign spi2_miso = (~spi2_csn[7] & spi2_sdi_hmc271_1) |
|
||||
(~spi2_csn[8] & spi2_sdi_hmc271_2);
|
||||
|
||||
assign gpio_i[51] = trig;
|
||||
assign spi_clk = spi0_clk;
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(19)) i_iobuf (
|
||||
.dio_t (gpio_t[50:32]),
|
||||
.dio_i (gpio_o[50:32]),
|
||||
.dio_o (gpio_i[50:32]),
|
||||
.dio_p ({ xo_en, // 50
|
||||
clk_sync, // 49
|
||||
adf4355_2_pd, // 48
|
||||
dac_txen0, // 47
|
||||
dac_txen1, // 46
|
||||
hmc271_1_reset, // 45
|
||||
hmc271_2_reset, // 44
|
||||
hmc349_sel, // 43
|
||||
hmc922_a, // 42
|
||||
hmc922_b, // 41
|
||||
adf4355_2_ld, // 40
|
||||
adf4355_1_ld, // 39
|
||||
dac_irq, // 38
|
||||
adc_fdb, // 37
|
||||
adc_fda, // 36
|
||||
clk_gpio[3], // 35
|
||||
clk_gpio[2], // 34
|
||||
clk_gpio[1], // 33
|
||||
clk_gpio[0]})); // 32
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
|
||||
.dio_t (gpio_t[14:0]),
|
||||
.dio_i (gpio_o[14:0]),
|
||||
.dio_o (gpio_i[14:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
.ddr3_ck_n (ddr3_ck_n),
|
||||
.ddr3_ck_p (ddr3_ck_p),
|
||||
.ddr3_cke (ddr3_cke),
|
||||
.ddr3_cs_n (ddr3_cs_n),
|
||||
.ddr3_dm (ddr3_dm),
|
||||
.ddr3_dq (ddr3_dq),
|
||||
.ddr3_dqs_n (ddr3_dqs_n),
|
||||
.ddr3_dqs_p (ddr3_dqs_p),
|
||||
.ddr3_odt (ddr3_odt),
|
||||
.ddr3_ras_n (ddr3_ras_n),
|
||||
.ddr3_reset_n (ddr3_reset_n),
|
||||
.ddr3_we_n (ddr3_we_n),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.rx_data_0_n (rx_data_n[0]),
|
||||
.rx_data_0_p (rx_data_p[0]),
|
||||
.rx_data_1_n (rx_data_n[1]),
|
||||
.rx_data_1_p (rx_data_p[1]),
|
||||
.rx_data_2_n (rx_data_n[2]),
|
||||
.rx_data_2_p (rx_data_p[2]),
|
||||
.rx_data_3_n (rx_data_n[3]),
|
||||
.rx_data_3_p (rx_data_p[3]),
|
||||
.rx_ref_clk_0 (rx_ref_clk),
|
||||
.rx_sync_0 (rx_sync),
|
||||
.rx_sysref_0 (rx_sysref),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (spi0_clk),
|
||||
.spi0_clk_o (spi0_clk),
|
||||
.spi0_csn_0_o (spi0_csn[0]),
|
||||
.spi0_csn_1_o (spi0_csn[1]),
|
||||
.spi0_csn_2_o (spi0_csn[2]),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi0_miso),
|
||||
.spi0_sdo_i (spi0_mosi),
|
||||
.spi0_sdo_o (spi0_mosi),
|
||||
.spi1_clk_i (spi1_clk),
|
||||
.spi1_clk_o (spi1_clk),
|
||||
.spi1_csn_0_o (spi1_csn[0]),
|
||||
.spi1_csn_1_o (spi1_csn[1]),
|
||||
.spi1_csn_2_o (spi1_csn[2]),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b1),
|
||||
.spi1_sdo_i (spi1_mosi),
|
||||
.spi1_sdo_o (spi1_mosi),
|
||||
.spi2_clk_i (spi2_clk),
|
||||
.spi2_clk_o (spi2_clk),
|
||||
.spi2_csn_i (12'hfff),
|
||||
.spi2_csn_o (spi2_csn),
|
||||
.spi2_sdi_i (spi2_miso),
|
||||
.spi2_sdo_i (spi2_mosi),
|
||||
.spi2_sdo_o (spi2_mosi),
|
||||
.sys_clk_clk_n (sys_clk_n),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_rst (sys_rst),
|
||||
.tx_data_0_n (tx_data_n[0]),
|
||||
.tx_data_0_p (tx_data_p[0]),
|
||||
.tx_data_1_n (tx_data_n[1]),
|
||||
.tx_data_1_p (tx_data_p[1]),
|
||||
.tx_data_2_n (tx_data_n[2]),
|
||||
.tx_data_2_p (tx_data_p[2]),
|
||||
.tx_data_3_n (tx_data_n[3]),
|
||||
.tx_data_3_p (tx_data_p[3]),
|
||||
.tx_data_4_n (tx_data_n[4]),
|
||||
.tx_data_4_p (tx_data_p[4]),
|
||||
.tx_data_5_n (tx_data_n[5]),
|
||||
.tx_data_5_p (tx_data_p[5]),
|
||||
.tx_data_6_n (tx_data_n[6]),
|
||||
.tx_data_6_p (tx_data_p[6]),
|
||||
.tx_data_7_n (tx_data_n[7]),
|
||||
.tx_data_7_p (tx_data_p[7]),
|
||||
.tx_ref_clk_0 (tx_ref_clk),
|
||||
.tx_sync_0 (tx_sync),
|
||||
.tx_sysref_0 (tx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue