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Merge remote-tracking branch 'origin/dev_ad7616' into dev

main
Istvan Csomortani 2016-06-29 12:32:39 +03:00
parent 2e80dec513 583bafd17a
commit 64633e519c
31 changed files with 3221 additions and 424 deletions
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2
library/Makefile
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@ -11,6 +11,7 @@ all: lib
clean:
make -C axi_ad6676 clean
make -C axi_ad7616 clean
make -C axi_ad9122 clean
make -C axi_ad9144 clean
make -C axi_ad9152 clean
@ -80,6 +81,7 @@ clean-all:clean
lib:
-make -C axi_ad6676
-make -C axi_ad7616
-make -C axi_ad9122
-make -C axi_ad9144
-make -C axi_ad9152

57
library/axi_ad7616/Makefile Normal file
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@ -0,0 +1,57 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := axi_ad7616_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_ad7616.v
M_DEPS += axi_ad7616_control.v
M_DEPS += axi_ad7616_pif.v
M_DEPS += ../common/ad_edge_detect.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
M_FLIST += *.hw
M_FLIST += *.sim
.PHONY: all dep clean clean-all
all: dep axi_ad7616.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_ad7616.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad7616_ip.tcl >> axi_ad7616_ip.log 2>&1
dep:
make -C ../spi_engine/spi_engine_execution
make -C ../spi_engine/axi_spi_engine
make -C ../spi_engine/spi_engine_offload
make -C ../spi_engine/spi_engine_interconnect
####################################################################################
####################################################################################

506
library/axi_ad7616/axi_ad7616.v Normal file
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@ -0,0 +1,506 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616 (
// physical data interface
sclk,
cs_n,
sdo,
sdi_0,
sdi_1,
db_o,
db_i,
db_t,
rd_n,
wr_n,
// physical control interface
cnvst,
busy,
// AXI Slave Memory Map
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// AXI-Stream Master
m_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_xfer_req,
irq
);
// parameters
parameter ID = 0;
parameter IF_TYPE = 1;
parameter M_AXIS_READY_ENABLE = 0;
// local parameters
localparam DATA_WIDTH = 8;
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
localparam PARALLEL = 1;
localparam NEG_EDGE = 1;
localparam UP_ADDRESS_WIDTH = 14;
// IO definitions
output sclk;
output cs_n;
output sdo;
input sdi_0;
input sdi_1;
output [15:0] db_o;
input [15:0] db_i;
output db_t;
output rd_n;
output wr_n;
output cnvst;
input busy;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
output [(NUM_OF_SDI * DATA_WIDTH-1):0] m_axis_tdata;
input m_axis_tready;
output m_axis_tvalid;
input m_axis_xfer_req;
output irq;
// internal registers
// internal signals
wire up_clk;
wire up_rstn;
wire up_rst;
wire up_rreq_s;
wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s;
wire up_wreq_s;
wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_if_s;
wire up_rack_if_s;
wire [31:0] up_rdata_if_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire trigger_s;
wire rd_req_s;
wire wr_req_s;
wire [15:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire m_axis_ready_s;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
// defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_rst = ~s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wack_if_s | up_wack_cntrl_s;
up_rack <= up_rack_if_s | up_rack_cntrl_s;
up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
end
end
assign m_axis_ready_s = (M_AXIS_READY_ENABLE) ? m_axis_tready : 1'b1;
generate if (IF_TYPE == SERIAL) begin
// ground all parallel interface signals
assign db_o = 16'b0;
assign rd_n = 1'b0;
assign wr_n = 1'b0;
// SPI Framework instances and logic
wire spi_resetn_s;
wire s0_cmd_ready_s;
wire s0_cmd_valid_s;
wire [15:0] s0_cmd_data_s;
wire s0_sdo_data_ready_s;
wire s0_sdo_data_valid_s;
wire [(DATA_WIDTH-1):0] s0_sdo_data_s;
wire s0_sdi_data_ready_s;
wire s0_sdi_data_valid_s;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data_s;
wire s0_sync_ready_s;
wire s0_sync_valid_s;
wire [ 7:0] s0_sync_s;
wire s1_cmd_ready_s;
wire s1_cmd_valid_s;
wire [15:0] s1_cmd_data_s;
wire s1_sdo_data_ready_s;
wire s1_sdo_data_valid_s;
wire [(DATA_WIDTH-1):0] s1_sdo_data_s;
wire s1_sdi_data_ready_s;
wire s1_sdi_data_valid_s;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data_s;
wire s1_sync_ready_s;
wire s1_sync_valid_s;
wire [ 7:0] s1_sync_s;
wire m_cmd_ready_s;
wire m_cmd_valid_s;
wire [15:0] m_cmd_data_s;
wire m_sdo_data_ready_s;
wire m_sdo_data_valid_s;
wire [(DATA_WIDTH-1):0] m_sdo_data_s;
wire m_sdi_data_ready_s;
wire m_sdi_data_valid_s;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data_s;
wire m_sync_ready_s;
wire m_sync_valid_s;
wire [ 7:0] m_sync_s;
wire offload0_cmd_wr_en_s;
wire [15:0] offload0_cmd_wr_data_s;
wire offload0_sdo_wr_en_s;
wire [(DATA_WIDTH-1):0] offload0_sdo_wr_data_s;
wire offload0_mem_reset_s;
wire offload0_enable_s;
wire offload0_enabled_s;
axi_spi_engine #(
.DATA_WIDTH (DATA_WIDTH),
.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OFFLOAD(1),
.MM_IF_TYPE(1),
.UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
) i_axi_spi_engine(
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_if_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_if_s),
.up_rack (up_rack_if_s),
.irq (irq),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.cmd_ready (s0_cmd_ready_s),
.cmd_valid (s0_cmd_valid_s),
.cmd_data (s0_cmd_data_s),
.sdo_data_ready (s0_sdo_data_ready_s),
.sdo_data_valid (s0_sdo_data_valid_s),
.sdo_data (s0_sdo_data_s),
.sdi_data_ready (s0_sdi_data_ready_s),
.sdi_data_valid (s0_sdi_data_valid_s),
.sdi_data (s0_sdi_data_s),
.sync_ready (s0_sync_ready_s),
.sync_valid (s0_sync_valid_s),
.sync_data (s0_sync_s),
.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
.offload0_mem_reset (offload0_mem_reset_s),
.offload0_enable (offload0_enable_s),
.offload0_enabled(offload0_enabled_s));
spi_engine_offload #(
.DATA_WIDTH (DATA_WIDTH),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_offload(
.ctrl_clk (up_clk),
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
.ctrl_enable (offload0_enable_s),
.ctrl_enabled (offload0_enabled_s),
.ctrl_mem_reset (offload0_mem_reset_s),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.trigger (trigger_s),
.cmd_valid (s1_cmd_valid_s),
.cmd_ready (s1_cmd_ready_s),
.cmd (s1_cmd_data_s),
.sdo_data_valid (s1_sdo_data_valid_s),
.sdo_data_ready (s1_sdo_data_ready_s),
.sdo_data (s1_sdo_data_s),
.sdi_data_valid (s1_sdi_data_valid_s),
.sdi_data_ready (s1_sdi_data_ready_s),
.sdi_data (s1_sdi_data_s),
.sync_valid (s1_sync_valid_s),
.sync_ready (s1_sync_ready_s),
.sync_data (s1_sync_s),
.offload_sdi_valid (m_axis_tvalid),
.offload_sdi_ready (m_axis_ready_s),
.offload_sdi_data (m_axis_tdata));
spi_engine_interconnect #(
.DATA_WIDTH (DATA_WIDTH),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_interconnect (
.clk (up_clk),
.resetn (spi_resetn_s),
.m_cmd_valid (m_cmd_valid_s),
.m_cmd_ready (m_cmd_ready_s),
.m_cmd_data (m_cmd_data_s),
.m_sdo_valid (m_sdo_data_valid_s),
.m_sdo_ready (m_sdo_data_ready_s),
.m_sdo_data (m_sdo_data_s),
.m_sdi_valid (m_sdi_data_valid_s),
.m_sdi_ready (m_sdi_data_ready_s),
.m_sdi_data (m_sdi_data_s),
.m_sync_valid (m_sync_valid_s),
.m_sync_ready (m_sync_ready_s),
.m_sync (m_sync_s),
.s0_cmd_valid (s0_cmd_valid_s),
.s0_cmd_ready (s0_cmd_ready_s),
.s0_cmd_data (s0_cmd_data_s),
.s0_sdo_valid (s0_sdo_data_valid_s),
.s0_sdo_ready (s0_sdo_data_ready_s),
.s0_sdo_data (s0_sdo_data_s),
.s0_sdi_valid (s0_sdi_data_valid_s),
.s0_sdi_ready (s0_sdi_data_ready_s),
.s0_sdi_data (s0_sdi_data_s),
.s0_sync_valid (s0_sync_valid_s),
.s0_sync_ready (s0_sync_ready_s),
.s0_sync (s0_sync_s),
.s1_cmd_valid (s1_cmd_valid_s),
.s1_cmd_ready (s1_cmd_ready_s),
.s1_cmd_data (s1_cmd_data_s),
.s1_sdo_valid (s1_sdo_data_valid_s),
.s1_sdo_ready (s1_sdo_data_ready_s),
.s1_sdo_data (s1_sdo_data_s),
.s1_sdi_valid (s1_sdi_data_valid_s),
.s1_sdi_ready (s1_sdi_data_ready_s),
.s1_sdi_data (s1_sdi_data_s),
.s1_sync_valid (s1_sync_valid_s),
.s1_sync_ready (s1_sync_ready_s),
.s1_sync (s1_sync_s));
spi_engine_execution #(
.DATA_WIDTH (DATA_WIDTH),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_execution (
.clk (up_clk),
.resetn (spi_resetn_s),
.active (),
.cmd_ready (m_cmd_ready_s),
.cmd_valid (m_cmd_valid_s),
.cmd (m_cmd_data_s),
.sdo_data_valid (m_sdo_data_valid_s),
.sdo_data_ready (m_sdo_data_ready_s),
.sdo_data (m_sdo_data_s),
.sdi_data_ready (m_sdi_data_ready_s),
.sdi_data_valid (m_sdi_data_valid_s),
.sdi_data (m_sdi_data_s),
.sync_ready (m_sync_ready_s),
.sync_valid (m_sync_valid_s),
.sync (m_sync_s),
.sclk (sclk),
.sdo (sdo),
.sdo_t (),
.sdi (sdi_0),
.sdi_1 (sdi_1),
.sdi_2 (1'b0),
.sdi_3 (1'b0),
.cs (cs_n),
.three_wire ());
end
endgenerate
generate if (IF_TYPE == PARALLEL) begin
assign sclk = 1'h0;
assign sdo = 1'h0;
assign irq = 1'h0;
assign up_wack_if_s = 1'h0;
assign up_rack_if_s = 1'h0;
assign up_rdata_if_s = 1'h0;
axi_ad7616_pif i_ad7616_parallel_interface (
.cs_n(cs_n),
.db_o(db_o),
.db_i(db_i),
.db_t(db_t),
.rd_n(rd_n),
.wr_n(wr_n),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_xfer_req(m_axis_xfer_req),
.end_of_conv(trigger_s),
.clk(up_clk),
.rstn(up_rstn),
.rd_req(rd_req_s),
.wr_req(wr_req_s),
.wr_data(wr_data_s),
.rd_data(rd_data_s),
.rd_valid(rd_valid_s)
);
end
endgenerate
axi_ad7616_control #(
.ID(ID),
.IF_TYPE(IF_TYPE)
) i_ad7616_control (
.cnvst (cnvst),
.busy (busy),
.up_read_data (rd_data_s),
.up_read_valid (rd_valid_s),
.up_write_data (wr_data_s),
.up_read_req (rd_req_s),
.up_write_req (wr_req_s),
.end_of_conv (trigger_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_cntrl_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_cntrl_s),
.up_rack (up_rack_cntrl_s));
// up bus interface
up_axi #(
.ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_control (
// control signals
cnvst,
busy,
up_read_data,
up_read_valid,
up_write_data,
up_read_req,
up_write_req,
end_of_conv,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack
);
parameter ID = 0;
parameter IF_TYPE = 0;
localparam PCORE_VERSION = 'h0001001;
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
localparam SERIAL = 0;
localparam PARALLEL = 1;
output cnvst;
input busy;
output end_of_conv;
input [15:0] up_read_data;
input up_read_valid;
output [15:0] up_write_data;
output up_read_req;
output up_write_req;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
reg [31:0] up_scratch = 32'b0;
reg up_resetn = 1'b0;
reg up_cnvst_en = 1'b0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_conv_rate = 32'b0;
reg [15:0] up_write_data = 16'h0;
reg [31:0] cnvst_counter = 32'b0;
reg [ 3:0] pulse_counter = 8'b0;
reg cnvst_buf = 1'b0;
reg cnvst_pulse = 1'b0;
reg [ 2:0] chsel_ff = 3'b0;
wire up_rst;
wire up_rreq_s;
wire up_rack_s;
wire up_wreq_s;
wire [31:0] up_read_data_s;
wire up_read_valid_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0;
// the up_[read/write]_data interfaces are valid just in parallel mode
assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'b0;
up_resetn <= 1'b0;
up_cnvst_en <= 1'b0;
up_conv_rate <= 32'b0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
up_cnvst_en <= up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_conv_rate <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_write_data <= up_wdata;
end
end
end
assign up_write_req = (up_waddr[7:0] == 8'h13) ? up_wreq_s : 1'h0;
// processor read interface
assign up_rack_s = (up_raddr[7:0] == 8'h12) ? up_read_valid_s : up_rreq_s;
assign up_read_req = (up_raddr[7:0] == 8'h12) ? up_rreq_s : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 32'b0;
end else begin
up_rack <= up_rack_s;
if (up_rack_s == 1'b1) begin
case (up_raddr[7:0])
8'h00 : up_rdata = PCORE_VERSION;
8'h01 : up_rdata = ID;
8'h02 : up_rdata = up_scratch;
8'h03 : up_rdata = IF_TYPE;
8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
8'h11 : up_rdata = up_conv_rate;
8'h12 : up_rdata = up_read_data_s;
endcase
end
end
end
// instantiations
assign up_rst = ~up_rstn;
ad_edge_detect #(
.EDGE(NEG_EDGE)
) i_ad_edge_detect (
.clk (up_clk),
.rst (up_rst),
.in (busy),
.out (end_of_conv)
);
// convertion start generator
// NOTE: + The minimum convertion cycle is 1 us
// + The rate of the cnvst must be defined in a way,
// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
// See the AD7616 datasheet for more information.
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
cnvst_counter <= 32'b0;
end else begin
cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
end
end
always @(cnvst_counter, up_conv_rate) begin
cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
end
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
pulse_counter <= 3'b0;
cnvst_buf <= 1'b0;
end else begin
pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
if(cnvst_pulse == 1'b1) begin
cnvst_buf <= 1'b1;
end else if (pulse_counter[2] == 1'b1) begin
cnvst_buf <= 1'b0;
end
end
end
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
endmodule

24
library/axi_ad7616/axi_ad7616_ip.tcl Normal file
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@ -0,0 +1,24 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad7616
adi_ip_files axi_ad7616 [list \
"axi_ad7616.v" \
"axi_ad7616_control.v" \
"axi_ad7616_pif.v" \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/common/up_axi.v"]
adi_ip_properties axi_ad7616
adi_ip_add_core_dependencies { \
analog.com:user:spi_engine_execution:1.0 \
analog.com:user:axi_spi_engine:1.0 \
analog.com:user:spi_engine_offload:1.0 \
analog.com:user:spi_engine_interconnect:1.0 \
}
ipx::save_core [ipx::current_core]

241
library/axi_ad7616/axi_ad7616_pif.v Normal file
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@ -0,0 +1,241 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_pif (
// physical interface
cs_n,
db_o,
db_i,
db_t,
rd_n,
wr_n,
// axi stream master
m_axis_tdata,
m_axis_tvalid,
m_axis_xfer_req,
// end of convertion
end_of_conv,
// register access
clk,
rstn,
rd_req,
wr_req,
wr_data,
rd_data,
rd_valid
);
parameter UP_ADDRESS_WIDTH = 14;
// IO definitions
output cs_n;
output [15:0] db_o;
input [15:0] db_i;
output db_t;
output rd_n;
output wr_n;
input end_of_conv;
input clk;
input rstn;
input rd_req;
input wr_req;
input [15:0] wr_data;
output [15:0] rd_data;
output rd_valid;
output [31:0] m_axis_tdata;
output m_axis_tvalid;
input m_axis_xfer_req;
// state registers
localparam [ 2:0] IDLE = 3'h0,
CS_LOW = 3'h1,
CNTRL0_LOW = 3'h2,
CNTRL0_HIGH = 3'h3,
CNTRL1_LOW = 3'h4,
CNTRL1_HIGH = 3'h5,
CS_HIGH = 3'h6;
// internal registers
reg [ 2:0] transfer_state = 3'h0;
reg [ 2:0] transfer_state_next = 3'h0;
reg [ 1:0] width_counter = 2'h0;
reg wr_req_d = 1'h0;
reg rd_req_d = 1'h0;
reg rd_conv_d = 1'h0;
reg xfer_req_d = 1'h0;
reg [15:0] data_out_a = 16'h0;
reg [15:0] data_out_b = 16'h0;
reg rd_db_valid_div2 = 1'h0;
reg rd_valid = 1'h0;
// internal wires
wire start_transfer;
wire rd_db_valid;
// FSM state register
always @(posedge clk) begin
if (rstn == 1'b0) begin
transfer_state <= 3'h0;
end else begin
transfer_state <= transfer_state_next;
end
end
// counters to control the RD_N and WR_N lines
assign start_transfer = end_of_conv | rd_req | wr_req;
always @(posedge clk) begin
if (rstn == 1'b0) begin
width_counter <= 2'h0;
end else begin
if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) ||
(transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH))
width_counter <= width_counter + 1;
else
width_counter <= 2'h0;
end
end
always @(negedge clk) begin
if (transfer_state == IDLE) begin
wr_req_d <= wr_req;
rd_req_d <= rd_req;
rd_conv_d <= end_of_conv;
end
end
// FSM next state logic
always @(*) begin
case (transfer_state)
IDLE : begin
transfer_state_next <= (start_transfer == 1'b1) ? CS_LOW : IDLE;
end
CS_LOW : begin
transfer_state_next <= CNTRL0_LOW;
end
CNTRL0_LOW : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
end
CNTRL0_HIGH : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH :
((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW;
end
CNTRL1_LOW : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
end
CNTRL1_HIGH : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
end
CS_HIGH : begin
transfer_state_next <= IDLE;
end
default : begin
transfer_state_next <= IDLE;
end
endcase
end
// data valid for the register access and m_axis interface
assign rd_db_valid = ((transfer_state == CS_HIGH) &&
((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (cs_n) begin
rd_db_valid_div2 <= 1'h0;
end else begin
rd_db_valid_div2 <= (rd_db_valid) ? ~rd_db_valid_div2 : rd_db_valid_div2;
end
end
// FSM output logic
assign db_o = wr_data;
always @(posedge clk) begin
data_out_a <= (transfer_state == CNTRL0_HIGH) ? db_i : data_out_a;
data_out_b <= (transfer_state == CNTRL1_HIGH) ? db_i : data_out_b;
rd_valid <= rd_db_valid;
end
assign rd_data = data_out_a;
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
assign db_t = ~wr_req_d;
assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) ||
(transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
// Master AXI stream output logic with additional xfer_req signal
// The first valid data is ALWAYS the first sample of a convertion
always @(negedge clk) begin
if (end_of_conv == 1'b1) begin
xfer_req_d <= m_axis_xfer_req;
end
end
assign m_axis_tdata = {data_out_b, data_out_a};
assign m_axis_tvalid = xfer_req_d & rd_valid & rd_db_valid_div2;
endmodule

95
library/common/ad_edge_detect.v Normal file
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@ -0,0 +1,95 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple edge detector circuit
`timescale 1ns/100ps
module ad_edge_detect (
clk,
rst,
in,
out
);
parameter EDGE = 0;
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
localparam ANY_EDGE = 2;
input clk;
input rst;
input in;
output out;
reg ff_m1 = 0;
reg ff_m2 = 0;
reg out = 0;
always @(posedge clk) begin
if (rst == 1) begin
ff_m1 <= 0;
ff_m2 <= 0;
end else begin
ff_m1 <= in;
ff_m2 <= ff_m1;
end
end
always @(posedge clk) begin
if (rst == 1) begin
out <= 1'b0;
end else begin
if (EDGE == POS_EDGE) begin
out <= ff_m1 & ~ff_m2;
end else if (EDGE == NEG_EDGE) begin
out <= ~ff_m1 & ff_m2;
end else begin
out <= ff_m1 ^ ff_m2;
end
end
end
endmodule

26
library/common/up_axi.v
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@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -135,14 +135,14 @@ module up_axi (
reg up_rsel = 'd0;
reg up_rreq = 'd0;
reg [AW:0] up_raddr = 'd0;
reg [ 3:0] up_rcount = 'd0;
reg [ 4:0] up_rcount = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
reg up_rack_int_d = 'd0;
reg [31:0] up_rdata_int_d = 'd0;
// write channel interface
assign up_axi_bresp = 2'd0;
always @(negedge up_rstn or posedge up_clk) begin
@ -167,7 +167,7 @@ module up_axi (
up_axi_bvalid <= 1'b1;
end
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
@ -230,7 +230,7 @@ module up_axi (
up_axi_rdata <= up_rdata_int_d;
end
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
@ -251,11 +251,11 @@ module up_axi (
up_raddr <= up_axi_araddr[AW+2:2];
end
if (up_rack_int == 1'b1) begin
up_rcount <= 4'd0;
end else if (up_rcount[3] == 1'b1) begin
up_rcount <= 5'd0;
end else if (up_rcount[4] == 1'b1) begin
up_rcount <= up_rcount + 1'b1;
end else if (up_rreq == 1'b1) begin
up_rcount <= 4'd8;
up_rcount <= 5'd16;
end
end
end
@ -267,7 +267,7 @@ module up_axi (
up_rack_int_d <= 'd0;
up_rdata_int_d <= 'd0;
end else begin
if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin
if ((up_rcount == 5'h1f) && (up_rack == 1'b0)) begin
up_rack_int <= 1'b1;
up_rdata_int <= {2{16'hdead}};
end else begin

497
library/spi_engine/axi_spi_engine/axi_spi_engine.v
View File

@ -1,68 +1,82 @@
module axi_spi_engine (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
// Slave AXI interface
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
output reg irq,
// up interface
input up_clk,
input up_rstn,
input up_wreq,
input [(UP_ADDRESS_WIDTH-1):0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [(UP_ADDRESS_WIDTH-1):0] up_raddr,
output [31:0] up_rdata,
output up_rack,
// SPI signals
input spi_clk,
output reg irq,
output spi_resetn,
// SPI signals
input spi_clk,
input cmd_ready,
output cmd_valid,
output [15:0] cmd_data,
output spi_resetn,
input sdo_data_ready,
output sdo_data_valid,
output [7:0] sdo_data,
input cmd_ready,
output cmd_valid,
output [15:0] cmd_data,
output sdi_data_ready,
input sdi_data_valid,
input [7:0] sdi_data,
input sdo_data_ready,
output sdo_data_valid,
output [(DATA_WIDTH-1):0] sdo_data,
output sync_ready,
input sync_valid,
input [7:0] sync_data,
output sdi_data_ready,
input sdi_data_valid,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
// Offload ctrl signals
output offload0_cmd_wr_en,
output [15:0] offload0_cmd_wr_data,
output sync_ready,
input sync_valid,
input [7:0] sync_data,
output offload0_sdo_wr_en,
output [7:0] offload0_sdo_wr_data,
// Offload ctrl signals
output offload0_cmd_wr_en,
output [15:0] offload0_cmd_wr_data,
output reg offload0_mem_reset,
output reg offload0_enable,
input offload0_enabled
output offload0_sdo_wr_en,
output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
output reg offload0_mem_reset,
output reg offload0_enable,
input offload0_enabled
);
parameter CMD_FIFO_ADDRESS_WIDTH = 4;
parameter SDO_FIFO_ADDRESS_WIDTH = 5;
parameter SDI_FIFO_ADDRESS_WIDTH = 5;
parameter MM_IF_TYPE = 0;
parameter UP_ADDRESS_WIDTH = 14;
parameter ASYNC_SPI_CLK = 0;
@ -72,7 +86,15 @@ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4;
parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4;
parameter ID = 'h00;
localparam PCORE_VERSION = 'h010061;
parameter DATA_WIDTH = 8;
parameter NUM_OF_SDI = 1;
localparam PCORE_VERSION = 'h010071;
localparam S_AXI = 0;
localparam UP_FIFO = 1;
wire clk;
wire rstn;
wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
wire cmd_fifo_almost_empty;
@ -84,66 +106,103 @@ wire cmd_fifo_in_valid;
wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
wire sdo_fifo_almost_empty;
wire [7:0] sdo_fifo_in_data;
wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
wire sdo_fifo_in_ready;
wire sdo_fifo_in_valid;
wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
wire sdi_fifo_almost_full;
wire [7:0] sdi_fifo_out_data;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
wire sdi_fifo_out_ready;
wire sdi_fifo_out_valid;
reg up_reset = 1'b1;
wire up_resetn = ~up_reset;
reg up_sw_reset = 1'b1;
wire up_sw_resetn = ~up_sw_reset;
reg [31:0] up_rdata = 'd0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
wire up_wreq;
wire up_rreq;
wire [31:0] up_wdata;
wire [ 7:0] up_waddr;
wire [ 7:0] up_raddr;
reg [31:0] up_rdata_ff = 'd0;
reg up_wack_ff = 1'b0;
reg up_rack_ff = 1'b0;
wire up_wreq_s;
wire up_rreq_s;
wire [31:0] up_wdata_s;
wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s;
wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s;
// Scratch register
reg [31:0] up_scratch = 'h00;
reg [7:0] sync_id = 'h00;
reg sync_id_pending = 1'b0;
reg sync_id_pending = 1'b0;
generate if (MM_IF_TYPE == S_AXI) begin
// assign clock and reset
assign clk = s_axi_aclk;
assign rstn = s_axi_aresetn;
// interface wrapper
up_axi #(
.ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
) i_up_axi (
.up_rstn(rstn),
.up_clk(clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq_s),
.up_waddr(up_waddr_s),
.up_wdata(up_wdata_s),
.up_wack(up_wack_ff),
.up_rreq(up_rreq_s),
.up_raddr(up_raddr_s),
.up_rdata(up_rdata_ff),
.up_rack(up_rack_ff)
);
assign up_rdata = 32'b0;
assign up_rack = 1'b0;
assign up_wack = 1'b0;
end
endgenerate
generate if (MM_IF_TYPE == UP_FIFO) begin
// assign clock and reset
assign clk = up_clk;
assign rstn = up_rstn;
assign up_wreq_s = up_wreq;
assign up_waddr_s = up_waddr;
assign up_wdata_s = up_wdata;
assign up_wack = up_wack_ff;
assign up_rreq_s = up_rreq;
assign up_raddr_s = up_raddr;
assign up_rdata = up_rdata_ff;
assign up_rack = up_rack_ff;
end
endgenerate
up_axi #(
.ADDRESS_WIDTH (8)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack)
);
// IRQ handling
reg [3:0] up_irq_mask = 'h0;
@ -151,85 +210,85 @@ wire [3:0] up_irq_source;
wire [3:0] up_irq_pending;
assign up_irq_source = {
sync_id_pending,
sdi_fifo_almost_full,
sdo_fifo_almost_empty,
cmd_fifo_almost_empty
sync_id_pending,
sdi_fifo_almost_full,
sdo_fifo_almost_empty,
cmd_fifo_almost_empty
};
assign up_irq_pending = up_irq_mask & up_irq_source;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
always @(posedge clk) begin
if (rstn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
up_wack <= 1'b0;
up_scratch <= 'h00;
up_reset <= 1'b1;
up_irq_mask <= 'h00;
offload0_enable <= 1'b0;
offload0_mem_reset <= 1'b0;
end else begin
up_wack <= up_wreq;
offload0_mem_reset <= 1'b0;
if (up_wreq) begin
case (up_waddr)
8'h02: up_scratch <= up_wdata;
8'h10: up_reset <= up_wdata;
8'h20: up_irq_mask <= up_wdata;
8'h40: offload0_enable <= up_wdata[0];
8'h42: offload0_mem_reset <= up_wdata[0];
endcase
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
up_wack_ff <= 1'b0;
up_scratch <= 'h00;
up_sw_reset <= 1'b1;
up_irq_mask <= 'h00;
offload0_enable <= 1'b0;
offload0_mem_reset <= 1'b0;
end else begin
up_wack_ff <= up_wreq_s;
offload0_mem_reset <= 1'b0;
if (up_wreq_s) begin
case (up_waddr_s)
8'h02: up_scratch <= up_wdata_s;
8'h10: up_sw_reset <= up_wdata_s;
8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable <= up_wdata_s[0];
8'h42: offload0_mem_reset <= up_wdata_s[0];
endcase
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
up_rack <= 'd0;
end else begin
up_rack <= up_rreq;
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
up_rack_ff <= 'd0;
end else begin
up_rack_ff <= up_rreq_s;
end
end
always @(posedge s_axi_aclk) begin
case (up_raddr)
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= up_reset;
8'h20: up_rdata <= up_irq_mask;
8'h21: up_rdata <= up_irq_pending;
8'h22: up_rdata <= up_irq_source;
8'h30: up_rdata <= sync_id;
8'h34: up_rdata <= cmd_fifo_room;
8'h35: up_rdata <= sdo_fifo_room;
8'h36: up_rdata <= sdi_fifo_level;
8'h3a: up_rdata <= sdi_fifo_out_data;
8'h3c: up_rdata <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata <= {offload0_enable};
8'h41: up_rdata <= {offload0_enabled};
default: up_rdata <= 'h00;
endcase
always @(posedge clk) begin
case (up_raddr_s)
8'h00: up_rdata_ff <= PCORE_VERSION;
8'h01: up_rdata_ff <= ID;
8'h02: up_rdata_ff <= up_scratch;
8'h10: up_rdata_ff <= up_sw_reset;
8'h20: up_rdata_ff <= up_irq_mask;
8'h21: up_rdata_ff <= up_irq_pending;
8'h22: up_rdata_ff <= up_irq_source;
8'h30: up_rdata_ff <= sync_id;
8'h34: up_rdata_ff <= cmd_fifo_room;
8'h35: up_rdata_ff <= sdo_fifo_room;
8'h36: up_rdata_ff <= sdi_fifo_level;
8'h3a: up_rdata_ff <= sdi_fifo_out_data;
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata_ff <= {offload0_enable};
8'h41: up_rdata_ff <= {offload0_enabled};
default: up_rdata_ff <= 'h00;
endcase
end
always @(posedge s_axi_aclk) begin
if (up_resetn == 1'b0) begin
sync_id <= 'h00;
sync_id_pending <= 1'b0;
end else begin
if (sync_valid == 1'b1) begin
sync_id <= sync_data;
sync_id_pending <= 1'b1;
end else if (up_wreq == 1'b1 && up_waddr == 8'h21 && up_wdata[3] == 1'b1) begin
sync_id_pending <= 1'b0;
end
end
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
sync_id <= 'h00;
sync_id_pending <= 1'b0;
end else begin
if (sync_valid == 1'b1) begin
sync_id <= sync_data;
sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
sync_id_pending <= 1'b0;
end
end
end
assign sync_ready = 1'b1;
@ -238,98 +297,98 @@ generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
ad_rst i_spi_resetn (
.preset(up_reset),
.clk(spi_clk),
.rst(spi_reset)
.preset(up_sw_reset),
.clk(spi_clk),
.rst(spi_reset)
);
assign spi_resetn = ~spi_reset;
end else begin
assign spi_resetn = ~up_reset;
assign spi_resetn = ~up_sw_reset;
end
endgenerate
/* Evaluates to true if FIFO level/room is 3/4 or above */
`define axi_spi_engine_check_watermark(x, n) \
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
assign cmd_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h38;
assign cmd_fifo_in_data = up_wdata[15:0];
assign cmd_fifo_in_data = up_wdata_s[15:0];
assign cmd_fifo_almost_empty =
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(16),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
.DATA_WIDTH(16),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_cmd_fifo (
.s_axis_aclk(s_axi_aclk),
.s_axis_aresetn(up_resetn),
.s_axis_ready(cmd_fifo_in_ready),
.s_axis_valid(cmd_fifo_in_valid),
.s_axis_data(cmd_fifo_in_data),
.s_axis_room(cmd_fifo_room),
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(cmd_fifo_in_ready),
.s_axis_valid(cmd_fifo_in_valid),
.s_axis_data(cmd_fifo_in_data),
.s_axis_room(cmd_fifo_room),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(cmd_ready),
.m_axis_valid(cmd_valid),
.m_axis_data(cmd_data)
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(cmd_ready),
.m_axis_valid(cmd_valid),
.m_axis_data(cmd_data)
);
assign sdo_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h39;
assign sdo_fifo_in_data = up_wdata[7:0];
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
assign sdo_fifo_almost_empty =
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
.DATA_WIDTH(DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sdo_fifo (
.s_axis_aclk(s_axi_aclk),
.s_axis_aresetn(up_resetn),
.s_axis_ready(sdo_fifo_in_ready),
.s_axis_valid(sdo_fifo_in_valid),
.s_axis_data(sdo_fifo_in_data),
.s_axis_room(sdo_fifo_room),
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(sdo_fifo_in_ready),
.s_axis_valid(sdo_fifo_in_valid),
.s_axis_data(sdo_fifo_in_data),
.s_axis_room(sdo_fifo_room),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(sdo_data_ready),
.m_axis_valid(sdo_data_valid),
.m_axis_data(sdo_data)
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(sdo_data_ready),
.m_axis_valid(sdo_data_valid),
.m_axis_data(sdo_data)
);
assign sdi_fifo_out_ready = up_rreq == 1'b1 && up_raddr == 8'h3a;
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
assign sdi_fifo_almost_full =
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sdi_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sdi_data_ready),
.s_axis_valid(sdi_data_valid),
.s_axis_data(sdi_data),
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sdi_data_ready),
.s_axis_valid(sdi_data_valid),
.s_axis_data(sdi_data),
.m_axis_aclk(s_axi_aclk),
.m_axis_aresetn(up_resetn),
.m_axis_ready(sdi_fifo_out_ready),
.m_axis_valid(sdi_fifo_out_valid),
.m_axis_data(sdi_fifo_out_data),
.m_axis_level(sdi_fifo_level)
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(sdi_fifo_out_ready),
.m_axis_valid(sdi_fifo_out_valid),
.m_axis_data(sdi_fifo_out_data),
.m_axis_level(sdi_fifo_level)
);
assign offload0_cmd_wr_en = up_wreq == 1'b1 && up_waddr == 8'h44;
assign offload0_cmd_wr_data = up_wdata[15:0];
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
assign offload0_cmd_wr_data = up_wdata_s[15:0];
assign offload0_sdo_wr_en = up_wreq == 1'b1 && up_waddr == 8'h45;
assign offload0_sdo_wr_data = up_wdata[7:0];
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
assign offload0_sdo_wr_data = up_wdata_s[7:0];
endmodule

382
library/spi_engine/spi_engine_execution/spi_engine_execution.v
View File

@ -1,39 +1,45 @@
module spi_engine_execution (
input clk,
input resetn,
input clk,
input resetn,
output reg active,
output reg active,
output cmd_ready,
input cmd_valid,
input [15:0] cmd,
output cmd_ready,
input cmd_valid,
input [15:0] cmd,
input sdo_data_valid,
output reg sdo_data_ready,
input [7:0] sdo_data,
input sdo_data_valid,
output reg sdo_data_ready,
input [(DATA_WIDTH-1):0] sdo_data,
input sdi_data_ready,
output reg sdi_data_valid,
output [7:0] sdi_data,
input sync_ready,
output reg sync_valid,
output [7:0] sync,
input sdi_data_ready,
output reg sdi_data_valid,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output reg sclk,
output sdo,
output reg sdo_t,
input sdi,
output reg [NUM_OF_CS-1:0] cs,
output reg three_wire
input sync_ready,
output reg sync_valid,
output [7:0] sync,
output reg sclk,
output sdo,
output reg sdo_t,
input sdi,
input sdi_1,
input sdi_2,
input sdi_3,
output reg [NUM_OF_CS-1:0] cs,
output reg three_wire
);
parameter NUM_OF_CS = 1;
parameter DEFAULT_SPI_CFG = 0;
parameter DEFAULT_CLK_DIV = 0;
parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
parameter NUM_OF_SDI = 1;
localparam CMD_TRANSFER = 2'b00;
localparam CMD_TRANSFER = 2'b00;
localparam CMD_CHIPSELECT = 2'b01;
localparam CMD_WRITE = 2'b10;
localparam CMD_MISC = 2'b11;
@ -44,19 +50,22 @@ localparam MISC_SLEEP = 1'b1;
localparam REG_CLK_DIV = 1'b0;
localparam REG_CONFIG = 1'b1;
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
DATA_WIDTH > 8 ? 4 : 3;
reg idle;
reg [7:0] clk_div_counter = 'h00;
reg [7:0] clk_div_counter_next = 'h00;
reg clk_div_last;
reg [11:0] counter = 'h00;
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
wire [7:0] sleep_counter = counter[11:4];
wire [1:0] cs_sleep_counter = counter[5:4];
wire [2:0] cs_sleep_counter2 = counter[6:4];
wire [2:0] bit_counter = counter[3:1];
wire [7:0] transfer_counter = counter[11:4];
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
wire ntx_rx = counter[0];
reg trigger = 1'b0;
@ -70,7 +79,7 @@ reg last_transfer;
wire end_of_word;
assign first_bit = bit_counter == 'h0;
assign last_bit = bit_counter == 'h7;
assign last_bit = bit_counter == DATA_WIDTH - 1;
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
reg [15:0] cmd_d1;
@ -82,7 +91,10 @@ reg [7:0] clk_div = DEFAULT_CLK_DIV;
wire sdo_enabled = cmd_d1[8];
wire sdi_enabled = cmd_d1[9];
reg [8:0] data_shift = 'h0;
reg [(DATA_WIDTH):0] data_shift = 'h0;
reg [(DATA_WIDTH):0] data_shift_1 = 'h0;
reg [(DATA_WIDTH):0] data_shift_2 = 'h0;
reg [(DATA_WIDTH):0] data_shift_3 = 'h0;
wire [1:0] inst = cmd[13:12];
wire [1:0] inst_d1 = cmd_d1[13:12];
@ -97,54 +109,54 @@ wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
assign cmd_ready = idle;
always @(posedge clk) begin
if (cmd_ready)
cmd_d1 <= cmd;
if (cmd_ready)
cmd_d1 <= cmd;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
active <= 1'b0;
end else begin
if (exec_cmd == 1'b1)
active <= 1'b1;
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
active <= 1'b0;
end
if (resetn == 1'b0) begin
active <= 1'b0;
end else begin
if (exec_cmd == 1'b1)
active <= 1'b1;
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
active <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cpha <= DEFAULT_SPI_CFG[0];
cpol <= DEFAULT_SPI_CFG[1];
three_wire <= DEFAULT_SPI_CFG[2];
clk_div <= DEFAULT_CLK_DIV;
end else if (exec_write_cmd == 1'b1) begin
if (cmd[8] == REG_CONFIG) begin
cpha <= cmd[0];
cpol <= cmd[1];
three_wire <= cmd[2];
end else if (cmd[8] == REG_CLK_DIV) begin
clk_div <= cmd[7:0];
end
end
if (resetn == 1'b0) begin
cpha <= DEFAULT_SPI_CFG[0];
cpol <= DEFAULT_SPI_CFG[1];
three_wire <= DEFAULT_SPI_CFG[2];
clk_div <= DEFAULT_CLK_DIV;
end else if (exec_write_cmd == 1'b1) begin
if (cmd[8] == REG_CONFIG) begin
cpha <= cmd[0];
cpol <= cmd[1];
three_wire <= cmd[2];
end else if (cmd[8] == REG_CLK_DIV) begin
clk_div <= cmd[7:0];
end
end
end
always @(posedge clk) begin
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
clk_div_counter == 'h01) || clk_div == 'h00)
clk_div_last <= 1'b1;
else
clk_div_last <= 1'b0;
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
clk_div_counter == 'h01) || clk_div == 'h00)
clk_div_last <= 1'b1;
else
clk_div_last <= 1'b0;
end
always @(posedge clk) begin
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
clk_div_counter <= clk_div;
trigger <= 1'b1;
end else begin
clk_div_counter <= clk_div_counter - 1'b1;
trigger <= 1'b0;
end
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
clk_div_counter <= clk_div;
trigger <= 1'b1;
end else begin
clk_div_counter <= clk_div_counter - 1'b1;
trigger <= 1'b0;
end
end
wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
@ -155,159 +167,169 @@ wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last
wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
always @(posedge clk) begin
if (idle == 1'b1)
counter <= 'h00;
else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
counter <= counter + (transfer_active ? 'h1 : 'h10);
if (idle == 1'b1)
counter <= 'h00;
else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
counter <= counter + (transfer_active ? 'h1 : 'h10);
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle <= 1'b1;
end else begin
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
idle <= 1'b0;
end else begin
case (inst_d1)
CMD_TRANSFER: begin
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
idle <= 1'b1;
end
CMD_CHIPSELECT: begin
if (cs_sleep_counter_compare2)
idle <= 1'b1;
end
CMD_MISC: begin
case (cmd_d1[8])
MISC_SLEEP: begin
if (sleep_counter_compare)
idle <= 1'b1;
end
MISC_SYNC: begin
if (sync_ready)
idle <= 1'b1;
end
endcase
end
endcase
end
end
if (resetn == 1'b0) begin
idle <= 1'b1;
end else begin
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
idle <= 1'b0;
end else begin
case (inst_d1)
CMD_TRANSFER: begin
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
idle <= 1'b1;
end
CMD_CHIPSELECT: begin
if (cs_sleep_counter_compare2)
idle <= 1'b1;
end
CMD_MISC: begin
case (cmd_d1[8])
MISC_SLEEP: begin
if (sleep_counter_compare)
idle <= 1'b1;
end
MISC_SYNC: begin
if (sync_ready)
idle <= 1'b1;
end
endcase
end
endcase
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cs <= 'hff;
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
cs <= cmd_d1[NUM_OF_CS-1:0];
end
if (resetn == 1'b0) begin
cs <= 'hff;
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
cs <= cmd_d1[NUM_OF_CS-1:0];
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
sync_valid <= 1'b0;
end else begin
if (exec_sync_cmd == 1'b1) begin
sync_valid <= 1'b1;
end else if (sync_ready == 1'b1) begin
sync_valid <= 1'b0;
end
end
if (resetn == 1'b0) begin
sync_valid <= 1'b0;
end else begin
if (exec_sync_cmd == 1'b1) begin
sync_valid <= 1'b1;
end else if (sync_ready == 1'b1) begin
sync_valid <= 1'b0;
end
end
end
assign sync = cmd_d1[7:0];
always @(posedge clk) begin
if (resetn == 1'b0)
sdo_data_ready <= 1'b0;
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
transfer_active == 1'b1)
sdo_data_ready <= 1'b1;
else if (sdo_data_valid == 1'b1)
sdo_data_ready <= 1'b0;
if (resetn == 1'b0)
sdo_data_ready <= 1'b0;
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
transfer_active == 1'b1)
sdo_data_ready <= 1'b1;
else if (sdo_data_valid == 1'b1)
sdo_data_ready <= 1'b0;
end
always @(posedge clk) begin
if (resetn == 1'b0)
sdi_data_valid <= 1'b0;
else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
transfer_active == 1'b1)
sdi_data_valid <= 1'b1;
else if (sdi_data_ready == 1'b1)
sdi_data_valid <= 1'b0;
if (resetn == 1'b0)
sdi_data_valid <= 1'b0;
else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
transfer_active == 1'b1)
sdi_data_valid <= 1'b1;
else if (sdi_data_ready == 1'b1)
sdi_data_valid <= 1'b0;
end
wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
always @(posedge clk) begin
if (idle == 1'b1) begin
last_transfer <= 1'b0;
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
if (transfer_counter == cmd_d1[7:0])
last_transfer <= 1'b1;
else
last_transfer <= 1'b0;
end
if (idle == 1'b1) begin
last_transfer <= 1'b0;
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
if (transfer_counter == cmd_d1[7:0])
last_transfer <= 1'b1;
else
last_transfer <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
transfer_active <= 1'b0;
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
if (io_ready2 == 1'b0)
wait_for_io <= 1'b1;
end
end
if (resetn == 1'b0) begin
transfer_active <= 1'b0;
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
if (io_ready2 == 1'b0)
wait_for_io <= 1'b1;
end
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
begin
sdo_t <= ~sdo_enabled;
end else begin
sdo_t <= 1'b1;
end
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
begin
sdo_t <= ~sdo_enabled;
end else begin
sdo_t <= 1'b1;
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
if (first_bit == 1'b1)
data_shift[8:1] <= sdo_data;
else
data_shift[8:1] <= data_shift[7:0];
end
if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
if (first_bit == 1'b1)
data_shift[DATA_WIDTH:1] <= sdo_data;
else
data_shift[DATA_WIDTH:1] <= data_shift[(DATA_WIDTH-1):0];
data_shift_1[DATA_WIDTH:1] <= data_shift_1[(DATA_WIDTH-1):0];
data_shift_2[DATA_WIDTH:1] <= data_shift_2[(DATA_WIDTH-1):0];
data_shift_3[DATA_WIDTH:1] <= data_shift_3[(DATA_WIDTH-1):0];
end
end
assign sdo = data_shift[8];
assign sdi_data = data_shift[7:0];
assign sdo = data_shift[DATA_WIDTH];
assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[(DATA_WIDTH-1):0] :
(NUM_OF_SDI == 2) ? {data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
(NUM_OF_SDI == 3) ? {data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
(NUM_OF_SDI == 4) ? {data_shift_3[(DATA_WIDTH-1):0], data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
data_shift[7:0];
always @(posedge clk) begin
if (trigger_rx == 1'b1) begin
data_shift[0] <= sdi;
end
if (trigger_rx == 1'b1) begin
data_shift[0] <= sdi;
data_shift_1[0] <= sdi_1;
data_shift_2[0] <= sdi_2;
data_shift_3[0] <= sdi_3;
end
end
always @(posedge clk) begin
if (transfer_active == 1'b1) begin
sclk <= cpol ^ cpha ^ ntx_rx;
end else begin
sclk <= cpol;
end
if (transfer_active == 1'b1) begin
sclk <= cpol ^ cpha ^ ntx_rx;
end else begin
sclk <= cpol;
end
end
endmodule

15
library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
View File

@ -10,11 +10,11 @@ module spi_engine_interconnect (
output m_sdo_valid,
input m_sdo_ready,
output [7:0] m_sdo_data,
output [(DATA_WIDTH-1):0] m_sdo_data,
input m_sdi_valid,
output m_sdi_ready,
input [7:0] m_sdi_data,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
input m_sync_valid,
output m_sync_ready,
@ -27,11 +27,11 @@ module spi_engine_interconnect (
input s0_sdo_valid,
output s0_sdo_ready,
input [7:0] s0_sdo_data,
input [(DATA_WIDTH-1):0] s0_sdo_data,
output s0_sdi_valid,
input s0_sdi_ready,
output [7:0] s0_sdi_data,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
output s0_sync_valid,
input s0_sync_ready,
@ -44,17 +44,20 @@ module spi_engine_interconnect (
input s1_sdo_valid,
output s1_sdo_ready,
input [7:0] s1_sdo_data,
input [(DATA_WIDTH-1):0] s1_sdo_data,
output s1_sdi_valid,
input s1_sdi_ready,
output [7:0] s1_sdi_data,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
output s1_sync_valid,
input s1_sync_ready,
output [7:0] s1_sync
);
parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
parameter NUM_OF_SDI = 1;
reg s_active = 1'b0;
reg idle = 1'b1;

1
library/spi_engine/spi_engine_offload/Makefile
View File

@ -8,6 +8,7 @@
M_DEPS := spi_engine_offload_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += ../../common/sync_bits.v
M_DEPS += spi_engine_offload.v
M_VIVADO := vivado -mode batch -source

14
library/spi_engine/spi_engine_offload/spi_engine_offload.v
View File

@ -6,7 +6,7 @@ module spi_engine_offload (
input [15:0] ctrl_cmd_wr_data,
input ctrl_sdo_wr_en,
input [7:0] ctrl_sdo_wr_data,
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
input ctrl_enable,
output ctrl_enabled,
@ -23,11 +23,11 @@ module spi_engine_offload (
output sdo_data_valid,
input sdo_data_ready,
output [7:0] sdo_data,
output [(DATA_WIDTH-1):0] sdo_data,
input sdi_data_valid,
output sdi_data_ready,
input [7:0] sdi_data,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
input sync_valid,
output sync_ready,
@ -35,12 +35,14 @@ module spi_engine_offload (
output offload_sdi_valid,
input offload_sdi_ready,
output [7:0] offload_sdi_data
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
);
parameter ASYNC_SPI_CLK = 0;
parameter CMD_MEM_ADDRESS_WIDTH = 4;
parameter SDO_MEM_ADDRESS_WIDTH = 4;
parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
parameter NUM_OF_SDI = 1;
reg spi_active = 1'b0;
@ -50,7 +52,7 @@ reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
reg [7:0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
@ -92,7 +94,7 @@ end
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
always @(posedge spi_clk) begin
spi_enabled <= spi_enable | spi_active;
spi_enabled <= spi_enable | spi_active;
end
sync_bits # (

1
library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
View File

@ -3,6 +3,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create spi_engine_offload
adi_ip_files spi_engine_offload [list \
"$ad_hdl_dir/library/common/sync_bits.v" \
"spi_engine_offload.v" \
]

3
projects/Makefile
View File

@ -9,6 +9,7 @@
all:
-make -C ad6676evb all
-make -C ad7768evb all
-make -C ad7616_sdz all
-make -C ad9265_fmc all
-make -C ad9434_fmc all
-make -C ad9467_fmc all
@ -44,6 +45,7 @@ all:
clean:
make -C ad6676evb clean
make -C ad7768evb clean
make -C ad7616_sdz clean
make -C ad9265_fmc clean
make -C ad9434_fmc clean
make -C ad9467_fmc clean
@ -79,6 +81,7 @@ clean:
clean-all:
make -C ad6676evb clean-all
make -C ad7768evb clean-all
make -C ad7616_sdz clean-all
make -C ad9265_fmc clean-all
make -C ad9434_fmc clean-all
make -C ad9467_fmc clean-all

24
projects/ad7616_sdz/Makefile Normal file
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@ -0,0 +1,24 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
.PHONY: all clean clean-all
all:
-make -C zc706 all
-make -C zed all
clean:
make -C zc706 clean
make -C zed clean
clean-all:
make -C zc706 clean-all
make -C zed clean-all
####################################################################################
####################################################################################

81
projects/ad7616_sdz/common/ad7616_bd.tcl Normal file
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@ -0,0 +1,81 @@
global ad7616_if
# data interfaces
create_bd_port -dir O sclk
create_bd_port -dir O sdo
create_bd_port -dir I sdi_0
create_bd_port -dir I sdi_1
create_bd_port -dir O -from 15 -to 0 db_o
create_bd_port -dir I -from 15 -to 0 db_i
create_bd_port -dir O db_t
create_bd_port -dir O rd_n
create_bd_port -dir O wr_n
# control lines
create_bd_port -dir O cnvst
create_bd_port -dir O cs_n
create_bd_port -dir I busy
# instantiation
set axi_ad7616 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7616:1.0 axi_ad7616]
set_property -dict [list CONFIG.IF_TYPE $ad7616_if] $axi_ad7616
set axi_ad7616_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7616_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad7616_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad7616_dma
# interface connections
if {$ad7616_if == 0} {
ad_connect sclk axi_ad7616/sclk
ad_connect sdo axi_ad7616/sdo
ad_connect sdi_0 axi_ad7616/sdi_0
ad_connect sdi_1 axi_ad7616/sdi_1
ad_connect cs_n axi_ad7616/cs_n
ad_connect cnvst axi_ad7616/cnvst
ad_connect busy axi_ad7616/busy
} else {
ad_connect db_o axi_ad7616/db_o
ad_connect db_i axi_ad7616/db_i
ad_connect db_t axi_ad7616/db_t
ad_connect rd_n axi_ad7616/rd_n
ad_connect wr_n axi_ad7616/wr_n
ad_connect cs_n axi_ad7616/cs_n
ad_connect cnvst axi_ad7616/cnvst
ad_connect busy axi_ad7616/busy
}
ad_connect sys_cpu_clk axi_ad7616_dma/s_axis_aclk
ad_connect axi_ad7616/m_axis axi_ad7616_dma/s_axis
ad_connect axi_ad7616/m_axis_xfer_req axi_ad7616_dma/s_axis_xfer_req
# interconnect
ad_cpu_interconnect 0x44A00000 axi_ad7616
ad_cpu_interconnect 0x44A30000 axi_ad7616_dma
# memory interconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad7616_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad7616_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad7616/irq

73
projects/ad7616_sdz/zc706/Makefile Normal file
View File

@ -0,0 +1,73 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top_si.v
M_DEPS += system_top_pi.v
M_DEPS += system_project.tcl
M_DEPS += system_bd.tcl
M_DEPS += serial_if_constr.xdc
M_DEPS += parallel_if_constr.xdc
M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += .Xil
.PHONY: all lib clean clean-all
all: lib ad7616_sdz_zc706.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad7616 clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean
ad7616_sdz_zc706.sdk/system_top.hdf: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> ad7616_sdz_zc706_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad7616
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx
####################################################################################
####################################################################################

36
projects/ad7616_sdz/zc706/parallel_if_constr.xdc Normal file
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@ -0,0 +1,36 @@
# ad7616
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

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# ad7616
# data interface
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi_0] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi_1] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad7616_bd.tcl

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
##--------------------------------------------------------------
# IMPORTANT: Set AD7616 operation and interface mode
#
# ad7616_if - Defines the interface type (serial OR parallel)
#
# LEGEND: Serial - 0
# Parallel - 1
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
#
##--------------------------------------------------------------
set ad7616_if 0
adi_project_create ad7616_sdz_zc706
if { $ad7616_if == 0 } {
adi_project_files ad7616_sdz_zc706 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top_si.v" \
"serial_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
} elseif { $ad7616_if == 1 } {
adi_project_files ad7616_sdz_zc706 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top_pi.v" \
"parallel_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
} else {
return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
}
adi_project_run ad7616_sdz_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
adc_db,
adc_rd_n,
adc_wr_n,
adc_cs_n,
adc_reset_n,
adc_convst,
adc_busy,
adc_seq_en,
adc_hw_rngsel,
adc_chsel);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
inout [15:0] adc_db;
output adc_rd_n;
output adc_wr_n;
output adc_cs_n;
output adc_reset_n;
output adc_convst;
input adc_busy;
output adc_seq_en;
output [ 1:0] adc_hw_rngsel;
output [ 2:0] adc_chsel;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;
// instantiations
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i (gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o (gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_seq_en, // 37
adc_chsel})); // 35:33
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.spdif (spdif),
.cnvst (adc_convst),
.cs_n (adc_cs_n),
.busy (adc_busy),
.db_o (adc_db_o),
.db_i (adc_db_i),
.db_t (adc_db_t),
.rd_n (adc_rd_n),
.wr_n (adc_wr_n)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
spi_sclk,
spi_sdo,
spi_sdi_0,
spi_sdi_1,
spi_cs_n,
adc_reset_n,
adc_convst,
adc_busy,
adc_seq_en,
adc_hw_rngsel,
adc_chsel,
adc_crcen,
adc_burst,
adc_os);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
output spi_sclk;
output spi_sdo;
input spi_sdi_0;
input spi_sdi_1;
output spi_cs_n;
output adc_reset_n;
output adc_convst;
input adc_busy;
output adc_seq_en;
output [ 1:0] adc_hw_rngsel;
output [ 2:0] adc_chsel;
output adc_crcen;
output adc_burst;
output [ 2:0] adc_os;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_os, // 40:38
adc_seq_en, // 37
adc_burst, // 36
adc_chsel, // 35:33
adc_crcen})); // 32
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.spdif (spdif),
.sclk (spi_sclk),
.sdo (spi_sdo),
.sdi_0 (spi_sdi_0),
.sdi_1 (spi_sdi_1),
.cnvst (adc_convst),
.cs_n (spi_cs_n),
.busy (adc_busy));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top_si.v
M_DEPS += system_top_pi.v
M_DEPS += system_project.tcl
M_DEPS += system_bd.tcl
M_DEPS += serial_if_constr.xdc
M_DEPS += parallel_if_constr.xdc
M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += .Xil
.PHONY: all lib clean clean-all
all: lib ad7616_sdz_zed.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad7616 clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_i2c_mixer clean
ad7616_sdz_zed.sdk/system_top.hdf: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> ad7616_sdz_zed_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad7616
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_i2c_mixer
####################################################################################
####################################################################################

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# ad7616
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N
# control lines
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

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# ad7616
# data interface
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports spi_sdi_0] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdi_1] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad7616_bd.tcl

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
##--------------------------------------------------------------
# IMPORTANT: Set AD7616 operation and interface mode
#
# ad7616_if - Defines the interface type (serial OR parallel)
#
# LEGEND: Serial - 0
# Parallel - 1
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
#
##--------------------------------------------------------------
set ad7616_if 0
adi_project_create ad7616_sdz_zed
if { $ad7616_if == 0 } {
adi_project_files ad7616_sdz_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top_si.v" \
"serial_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
} elseif { $ad7616_if == 1 } {
adi_project_files ad7616_sdz_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top_pi.v" \
"parallel_if_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
} else {
return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."]
}
adi_project_run ad7616_sdz_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
adc_db,
adc_rd_n,
adc_wr_n,
adc_cs_n,
adc_reset_n,
adc_convst,
adc_busy,
adc_seq_en,
adc_hw_rngsel,
adc_chsel);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
inout [15:0] adc_db;
output adc_rd_n;
output adc_wr_n;
output adc_cs_n;
output adc_reset_n;
output adc_convst;
input adc_busy;
output adc_seq_en;
output [ 1:0] adc_hw_rngsel;
output [ 2:0] adc_chsel;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;
// instantiations
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
.dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_seq_en, // 37
adc_chsel})); // 35:33
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.cnvst (adc_convst),
.cs_n (adc_cs_n),
.busy (adc_busy),
.db_o (adc_db_o),
.db_i (adc_db_i),
.db_t (adc_db_t),
.rd_n (adc_rd_n),
.wr_n (adc_wr_n)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
spi_sclk,
spi_sdo,
spi_sdi_0,
spi_sdi_1,
spi_cs_n,
adc_reset_n,
adc_convst,
adc_busy,
adc_seq_en,
adc_hw_rngsel,
adc_chsel,
adc_crcen,
adc_burst,
adc_os);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
output spi_sclk;
output spi_sdo;
input spi_sdi_0;
input spi_sdi_1;
output spi_cs_n;
output adc_reset_n;
output adc_convst;
input adc_busy;
output adc_seq_en;
output [ 1:0] adc_hw_rngsel;
output [ 2:0] adc_chsel;
output adc_crcen;
output adc_burst;
output [ 2:0] adc_os;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_os, // 40:38
adc_seq_en, // 37
adc_burst, // 36
adc_chsel, // 35:33
adc_crcen})); // 32
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.cnvst (adc_convst),
.sclk (spi_sclk),
.sdo (spi_sdo),
.sdi_0 (spi_sdi_0),
.sdi_1 (spi_sdi_1),
.cs_n (spi_cs_n),
.busy (adc_busy)
);
endmodule
// ***************************************************************************
// ***************************************************************************