zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_ad9122: Update core to the new DRP interface

main
Istvan Csomortani 2016-09-21 16:09:55 +03:00
parent bae839acd4
commit 64cd7dc002
4 changed files with 39 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
library/axi_ad9122/axi_ad9122.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -187,8 +187,8 @@ module axi_ad9122 (
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire [31:0] up_drp_wdata_s;
wire [31:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;

20
library/axi_ad9122/axi_ad9122_channel.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -197,7 +197,7 @@ module axi_ad9122_channel (
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
@ -212,7 +212,7 @@ module axi_ad9122_channel (
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
@ -227,7 +227,7 @@ module axi_ad9122_channel (
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
@ -242,7 +242,7 @@ module axi_ad9122_channel (
.dds_data (dac_dds_data_3_s));
end
endgenerate
// single channel processor
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
@ -284,7 +284,7 @@ module axi_ad9122_channel (
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************

4
library/axi_ad9122/axi_ad9122_core.v
View File

@ -156,8 +156,8 @@ module axi_ad9122_core (
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
output [31:0] up_drp_wdata;
input [31:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;

35
library/axi_ad9122/axi_ad9122_if.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -156,8 +156,8 @@ module axi_ad9122_if (
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
@ -186,12 +186,13 @@ module axi_ad9122_if (
ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (16))
i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_s0 (dac_data_i0),
.data_s1 (dac_data_q0),
.data_s2 (dac_data_i1),
@ -204,15 +205,16 @@ module axi_ad9122_if (
.data_out_n (dac_data_out_n));
// dac frame output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1))
i_serdes_out_frame (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_s0 (dac_frame_i0),
.data_s1 (dac_frame_q0),
.data_s2 (dac_frame_i1),
@ -225,15 +227,16 @@ module axi_ad9122_if (
.data_out_n (dac_frame_out_n));
// dac clock output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_out_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
@ -248,21 +251,23 @@ module axi_ad9122_if (
// dac clock input buffers
ad_serdes_clk #(
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_serdes_clk (
.mmcm_rst (mmcm_rst),
.rst (mmcm_rst),
.clk_in_p (dac_clk_in_p),
.clk_in_n (dac_clk_in_n),
.clk (dac_clk),
.div_clk (dac_div_clk),
.out_clk (dac_out_clk),
.loaden (),
.phase (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),