From 64d1d54ec04ba542314e531a787892cc7410da48 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 10 Nov 2016 17:45:03 +0200 Subject: [PATCH] util_fir_int: Update filter, as it's used with ad9361 in CMOS mode --- library/util_fir_int/util_fir_int_ip.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/util_fir_int/util_fir_int_ip.tcl b/library/util_fir_int/util_fir_int_ip.tcl index 1a0fbe32b..83d0b2dac 100644 --- a/library/util_fir_int/util_fir_int_ip.tcl +++ b/library/util_fir_int/util_fir_int_ip.tcl @@ -5,7 +5,7 @@ adi_ip_create util_fir_int set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp] set_property -dict [ list \ -CONFIG.Clock_Frequency {128.8} \ +CONFIG.Clock_Frequency {61.44} \ CONFIG.CoefficientSource {COE_File} \ CONFIG.Coefficient_File {../../../../coefile_int.coe} \ CONFIG.Coefficient_Fractional_Bits {0} \ @@ -26,7 +26,7 @@ CONFIG.Output_Rounding_Mode {Truncate_LSBs} \ CONFIG.Output_Width {16} \ CONFIG.Quantization {Integer_Coefficients} \ CONFIG.RateSpecification {Frequency_Specification} \ -CONFIG.Sample_Frequency {8} \ +CONFIG.Sample_Frequency {7.68} \ CONFIG.Zero_Pack_Factor {1} \ ] [get_ips fir_interp]