util_fir_int: Update filter, as it's used with ad9361 in CMOS mode
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66098b7ae7
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64d1d54ec0
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@ -5,7 +5,7 @@ adi_ip_create util_fir_int
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set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp]
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set_property -dict [ list \
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CONFIG.Clock_Frequency {128.8} \
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CONFIG.Clock_Frequency {61.44} \
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CONFIG.CoefficientSource {COE_File} \
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CONFIG.Coefficient_File {../../../../coefile_int.coe} \
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CONFIG.Coefficient_Fractional_Bits {0} \
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@ -26,7 +26,7 @@ CONFIG.Output_Rounding_Mode {Truncate_LSBs} \
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CONFIG.Output_Width {16} \
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CONFIG.Quantization {Integer_Coefficients} \
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CONFIG.RateSpecification {Frequency_Specification} \
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CONFIG.Sample_Frequency {8} \
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CONFIG.Sample_Frequency {7.68} \
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CONFIG.Zero_Pack_Factor {1} \
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] [get_ips fir_interp]
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