From 6551672ce590650ebd485b1751df6e0ce7234bb5 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 23 Apr 2015 17:56:35 +0300 Subject: [PATCH] fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells. This is a the maximum BRAM FIFO depth in case of the VC707. --- projects/fmcadc2/vc707/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl index b94ea5ac4..437a6f4f6 100644 --- a/projects/fmcadc2/vc707/system_bd.tcl +++ b/projects/fmcadc2/vc707/system_bd.tcl @@ -2,7 +2,7 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl -p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 10 +p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18 source ../common/fmcadc2_bd.tcl