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fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. 

The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
main
Istvan Csomortani 2015-04-23 17:56:35 +03:00
parent 9670265468
commit 6551672ce5
1 changed files with 1 additions and 1 deletions
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2
projects/fmcadc2/vc707/system_bd.tcl
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@ -2,7 +2,7 @@
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 10
p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18
source ../common/fmcadc2_bd.tcl