axi_spi_engine: Add generic config params
The 4 parameters are added to facilitate transmiting project related information to the software. They act as read-only memory which is written in Vivado when the project builds. Set 31 to SDI FIFO's almost full thresholdmain
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6570c23a76
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@ -48,7 +48,11 @@ module axi_spi_engine #(
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parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
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parameter ID = 0,
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parameter [15:0] DATA_WIDTH = 8,
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parameter [ 7:0] NUM_OF_SDI = 1 ) (
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parameter [ 7:0] NUM_OF_SDI = 1,
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parameter CFG_INFO_0 = 0,
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parameter CFG_INFO_1 = 0,
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parameter CFG_INFO_2 = 0,
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parameter CFG_INFO_3 = 0) (
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// Slave AXI interface
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@ -349,6 +353,10 @@ module axi_spi_engine #(
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8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
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8'h40: up_rdata_ff <= {offload0_enable_reg};
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8'h41: up_rdata_ff <= {offload0_enabled_s};
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8'h80: up_rdata_ff <= CFG_INFO_0;
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8'h81: up_rdata_ff <= CFG_INFO_1;
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8'h82: up_rdata_ff <= CFG_INFO_2;
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8'h83: up_rdata_ff <= CFG_INFO_3;
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default: up_rdata_ff <= 'h00;
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endcase
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end
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@ -466,7 +474,7 @@ module axi_spi_engine #(
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.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
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.M_AXIS_REGISTERED(0),
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.ALMOST_EMPTY_THRESHOLD(1),
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.ALMOST_FULL_THRESHOLD(1)
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.ALMOST_FULL_THRESHOLD(31)
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) i_sdi_fifo (
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.s_axis_aclk(spi_clk),
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.s_axis_aresetn(spi_resetn),
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