From 6570c23a76893a07593b936d69d653bb58121146 Mon Sep 17 00:00:00 2001 From: sergiu arpadi Date: Tue, 8 Jun 2021 16:48:41 +0300 Subject: [PATCH] axi_spi_engine: Add generic config params The 4 parameters are added to facilitate transmiting project related information to the software. They act as read-only memory which is written in Vivado when the project builds. Set 31 to SDI FIFO's almost full threshold --- library/spi_engine/axi_spi_engine/axi_spi_engine.v | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 0f6411242..f95b6ba19 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -48,7 +48,11 @@ module axi_spi_engine #( parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4, parameter ID = 0, parameter [15:0] DATA_WIDTH = 8, - parameter [ 7:0] NUM_OF_SDI = 1 ) ( + parameter [ 7:0] NUM_OF_SDI = 1, + parameter CFG_INFO_0 = 0, + parameter CFG_INFO_1 = 0, + parameter CFG_INFO_2 = 0, + parameter CFG_INFO_3 = 0) ( // Slave AXI interface @@ -349,6 +353,10 @@ module axi_spi_engine #( 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ 8'h40: up_rdata_ff <= {offload0_enable_reg}; 8'h41: up_rdata_ff <= {offload0_enabled_s}; + 8'h80: up_rdata_ff <= CFG_INFO_0; + 8'h81: up_rdata_ff <= CFG_INFO_1; + 8'h82: up_rdata_ff <= CFG_INFO_2; + 8'h83: up_rdata_ff <= CFG_INFO_3; default: up_rdata_ff <= 'h00; endcase end @@ -466,7 +474,7 @@ module axi_spi_engine #( .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), .M_AXIS_REGISTERED(0), .ALMOST_EMPTY_THRESHOLD(1), - .ALMOST_FULL_THRESHOLD(1) + .ALMOST_FULL_THRESHOLD(31) ) i_sdi_fifo ( .s_axis_aclk(spi_clk), .s_axis_aresetn(spi_resetn),