axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the request splitter when disabling the DMAC. Otherwise it is possible that under certain conditions the DMAC is disabled with a partially accepted request and when it is enabled again it will continue in an inconsistent state which can lead to transfer corruption or pipeline stalls. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
731e1c0996
commit
65bda6505e
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@ -198,7 +198,7 @@ localparam DMA_TYPE_AXI_MM = 0;
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localparam DMA_TYPE_AXI_STREAM = 1;
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localparam DMA_TYPE_AXI_STREAM = 1;
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localparam DMA_TYPE_FIFO = 2;
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localparam DMA_TYPE_FIFO = 2;
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localparam PCORE_VERSION = 'h00040061;
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localparam PCORE_VERSION = 'h00040062;
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localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
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localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
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localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
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localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
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@ -883,15 +883,30 @@ axi_register_slice #(
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// We do not accept any requests until all components are enabled
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// We do not accept any requests until all components are enabled
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reg _req_valid = 1'b0;
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wire _req_ready;
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wire _req_ready;
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assign req_ready = _req_ready & enabled;
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always @(posedge req_aclk)
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begin
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if (req_aresetn == 1'b0) begin
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_req_valid <= 1'b0;
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end else begin
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if (_req_valid == 1'b1 && _req_ready == 1'b1) begin
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_req_valid <= 1'b0;
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end else if (req_valid == 1'b1 && enabled == 1'b1) begin
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_req_valid <= 1'b1;
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end
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end
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end
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assign req_ready = _req_ready & _req_valid & enable;
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splitter #(
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splitter #(
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.C_NUM_M(3)
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.C_NUM_M(3)
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) i_req_splitter (
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) i_req_splitter (
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.clk(req_aclk),
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.clk(req_aclk),
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.resetn(req_aresetn),
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.resetn(req_aresetn),
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.s_valid(req_valid & enabled),
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.s_valid(_req_valid),
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.s_ready(_req_ready),
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.s_ready(_req_ready),
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.m_valid({
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.m_valid({
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req_gen_valid,
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req_gen_valid,
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