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axi_dmac: Correctly handle shutdown for the request splitter 

We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-02-19 14:23:05 +01:00
parent 731e1c0996
commit 65bda6505e
2 changed files with 18 additions and 3 deletions
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2
library/axi_dmac/axi_dmac.v
View File

@ -198,7 +198,7 @@ localparam DMA_TYPE_AXI_MM = 0;
localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
localparam PCORE_VERSION = 'h00040061;
localparam PCORE_VERSION = 'h00040062;
localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;

19
library/axi_dmac/request_arb.v
View File

@ -883,15 +883,30 @@ axi_register_slice #(
// We do not accept any requests until all components are enabled
reg _req_valid = 1'b0;
wire _req_ready;
assign req_ready = _req_ready & enabled;
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
_req_valid <= 1'b0;
end else begin
if (_req_valid == 1'b1 && _req_ready == 1'b1) begin
_req_valid <= 1'b0;
end else if (req_valid == 1'b1 && enabled == 1'b1) begin
_req_valid <= 1'b1;
end
end
end
assign req_ready = _req_ready & _req_valid & enable;
splitter #(
.C_NUM_M(3)
) i_req_splitter (
.clk(req_aclk),
.resetn(req_aresetn),
.s_valid(req_valid & enabled),
.s_valid(_req_valid),
.s_ready(_req_ready),
.m_valid({
req_gen_valid,