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axi_ad9434 : Update the IO delay interface

main
Istvan Csomortani 2015-05-22 19:47:09 +03:00
parent f91fbf1bc1
commit 660c84e01c
4 changed files with 99 additions and 140 deletions
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40
library/axi_ad9434/axi_ad9434.v
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@ -152,15 +152,14 @@ module axi_ad9434 (
wire [ 1:0] up_status_or_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire [12:0] up_dld_s;
wire [64:0] up_dwdata_s;
wire [64:0] up_drdata_s;
wire delay_clk_s;
wire delay_rst;
wire delay_locked_s;
wire drp_sel_s;
wire drp_rst_s;
wire drp_wr_s;
@ -196,15 +195,13 @@ module axi_ad9434 (
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_status(adc_status_s),
.delay_clk(delay_clk),
.delay_rst(delay_rst_s),
.delay_sel(delay_sel_s),
.delay_rwn(delay_rwn_s),
.delay_addr(delay_addr_s),
.delay_wdata(delay_wdata_s),
.delay_rdata(delay_rdata_s),
.delay_ack_t(delay_ack_t_s),
.delay_locked(delay_locked_s),
.up_clk (up_clk),
.up_adc_dld (up_dld_s),
.up_adc_dwdata (up_dwdata_s),
.up_adc_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.mmcm_rst(mmcm_rst),
.drp_clk(drp_clk),
.drp_rst(drp_rst_s),
@ -228,14 +225,11 @@ module axi_ad9434 (
.dma_dvalid (adc_valid),
.dma_data (adc_data),
.dma_dovf (adc_dovf),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.drp_clk (drp_clk),
.drp_rst (drp_rst_s),

67
library/axi_ad9434/axi_ad9434_core.v
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@ -68,14 +68,11 @@ module axi_ad9434_core (
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// processor interface
@ -122,14 +119,11 @@ module axi_ad9434_core (
input drp_locked;
// delay interface
output [12:0] up_dld;
output [64:0] up_dwdata;
input [64:0] up_drdata;
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// processor interface
@ -166,9 +160,9 @@ module axi_ad9434_core (
wire adc_pn_err_s;
wire adc_pn_oos_s;
wire up_wack_s[0:1];
wire [31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:2];
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
// instantiations
axi_ad9434_pnmon i_pnmon (
@ -203,9 +197,9 @@ module axi_ad9434_core (
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rdata_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_rdata_s[2];
end
end
@ -213,27 +207,24 @@ module axi_ad9434_core (
.PCORE_ID(PCORE_ID))
i_adc_common(
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status),
.adc_sync_status (1'd0),
.adc_status_ovf (dma_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd4),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
@ -243,10 +234,12 @@ module axi_ad9434_core (
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
@ -306,4 +299,24 @@ module axi_ad9434_core (
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(13), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
endmodule

93
library/axi_ad9434/axi_ad9434_if.v
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@ -60,14 +60,12 @@ module axi_ad9434_if (
adc_status,
// delay interface (for IDELAY macros)
up_clk,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// mmcm reset
@ -110,15 +108,14 @@ module axi_ad9434_if (
input adc_rst;
output adc_status;
// delay control signals
// delay interface
input up_clk;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// mmcm reset
@ -135,17 +132,12 @@ module axi_ad9434_if (
output drp_ready;
output drp_locked;
// output registers
reg [ 4:0] delay_rdata = 'b0;
reg delay_ack_t = 'b0;
// internal registers
reg [12:0] delay_ld = 'd0;
reg adc_status = 'd0;
reg adc_status_m1 = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[12:0];
wire [3:0] adc_or_s;
@ -157,55 +149,6 @@ module axi_ad9434_if (
// output assignment for adc clock (1:4 of the sampling clock)
assign adc_clk = adc_div_clk;
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'd12 : delay_ld <= 13'h1000;
8'd11 : delay_ld <= 13'h0800;
8'd10 : delay_ld <= 13'h0400;
8'd9 : delay_ld <= 13'h0200;
8'd8 : delay_ld <= 13'h0100;
8'd7 : delay_ld <= 13'h0080;
8'd6 : delay_ld <= 13'h0040;
8'd5 : delay_ld <= 13'h0020;
8'd4 : delay_ld <= 13'h0010;
8'd3 : delay_ld <= 13'h0008;
8'd2 : delay_ld <= 13'h0004;
8'd1 : delay_ld <= 13'h0002;
8'd0 : delay_ld <= 13'h0001;
default : delay_ld <= 13'h0000;
endcase
end else begin
delay_ld <= 13'h000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'd12 : delay_rdata <= delay_rdata_s[12];
8'd11 : delay_rdata <= delay_rdata_s[11];
8'd10 : delay_rdata <= delay_rdata_s[10];
8'd9 : delay_rdata <= delay_rdata_s[9];
8'd8 : delay_rdata <= delay_rdata_s[8];
8'd7 : delay_rdata <= delay_rdata_s[7];
8'd6 : delay_rdata <= delay_rdata_s[6];
8'd5 : delay_rdata <= delay_rdata_s[5];
8'd4 : delay_rdata <= delay_rdata_s[4];
8'd3 : delay_rdata <= delay_rdata_s[3];
8'd2 : delay_rdata <= delay_rdata_s[2];
8'd1 : delay_rdata <= delay_rdata_s[1];
8'd0 : delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
@ -229,11 +172,12 @@ module axi_ad9434_if (
.data_s7(),
.data_in_p(adc_data_in_p[l_inst]),
.data_in_n(adc_data_in_n[l_inst]),
.up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_ld(delay_ld[l_inst]),
.delay_wdata(delay_wdata),
.delay_rdata(delay_rdata_s[l_inst]),
.delay_locked());
end
endgenerate
@ -259,11 +203,12 @@ module axi_ad9434_if (
.data_s7(),
.data_in_p(adc_or_in_p),
.data_in_n(adc_or_in_n),
.up_clk (up_clk),
.up_dld (up_adc_dld[12]),
.up_dwdata (up_adc_dwdata[64:60]),
.up_drdata (up_adc_drdata[64:60]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_ld(delay_ld[12]),
.delay_wdata(delay_wdata),
.delay_rdata(delay_rdata_s[12]),
.delay_locked(delay_locked));
// clock input buffers and MMCM

39
library/common/ad_serdes_in.v
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@ -60,13 +60,17 @@ module ad_serdes_in (
data_in_p,
data_in_n,
// delay interface
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-control interface
delay_clk,
delay_rst,
delay_ld,
delay_wdata,
delay_rdata,
delay_locked);
// parameters
@ -103,13 +107,16 @@ module ad_serdes_in (
input data_in_p;
input data_in_n;
// delay interface
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-control interface
input delay_clk;
input delay_rst;
input delay_ld;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_locked;
// internal signals
@ -160,12 +167,12 @@ module ad_serdes_in (
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.C (up_clk),
.IDATAIN (data_in_ibuf_s),
.DATAOUT (data_in_idelay_s),
.LD (delay_ld),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata));
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
// Note: The first sample in time will be data_s7, the last data_s0!
if(IF_TYPE == SDR) begin
@ -290,12 +297,12 @@ module ad_serdes_in (
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.C (up_clk),
.IDATAIN (data_in_ibuf_s),
.DATAOUT (data_in_idelay_s),
.RST (delay_ld),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata));
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
ISERDESE1 #(
.DATA_RATE("DDR"),