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daq3- round about way to avoid ip getting locked

main
Rejeesh Kutty 2017-01-20 15:55:33 -05:00
parent afcd11da87
commit 661413627f
2 changed files with 9 additions and 8 deletions
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11
projects/daq3/zc706/system_constr.xdc
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@ -52,8 +52,11 @@ set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
# clocks
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]

6
projects/daq3/zc706/system_project.tcl
View File

@ -14,10 +14,8 @@ adi_project_files daq3_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property part "xc7z045ffg900-3" [current_project]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
set_property part "xc7z045ffg900-3" [get_runs synth_1]
set_property part "xc7z045ffg900-3" [get_runs impl_1]
adi_project_run daq3_zc706