diff --git a/projects/fmcomms8/a10soc/Makefile b/projects/fmcomms8/a10soc/Makefile new file mode 100755 index 000000000..1ada9a853 --- /dev/null +++ b/projects/fmcomms8/a10soc/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := fmcomms8_a10soc + +M_DEPS += ../common/fmcomms8_spi.v +M_DEPS += ../common/fmcomms8_qsys.tcl +M_DEPS += ../../scripts/adi_pd_intel.tcl +M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl +M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-intel.mk diff --git a/projects/fmcomms8/a10soc/system_constr.sdc b/projects/fmcomms8/a10soc/system_constr.sdc new file mode 100755 index 000000000..7ba3779c9 --- /dev/null +++ b/projects/fmcomms8/a10soc/system_constr.sdc @@ -0,0 +1,15 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.069 ns" -name ref_clk_c [get_ports {ref_clk_c}] +create_clock -period "4.069 ns" -name ref_clk_d [get_ports {ref_clk_d}] +create_clock -period "4.069 ns" -name core_clk_c [get_ports {core_clk_c}] +create_clock -period "4.069 ns" -name core_clk_d [get_ports {core_clk_d}] +create_clock -period "100 ns" -name spi_clk [get_nets {i_system_bd|sys_spi|sys_spi|SCLK_reg}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] +set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/fmcomms8/a10soc/system_project.tcl b/projects/fmcomms8/a10soc/system_project.tcl new file mode 100755 index 000000000..96614bf62 --- /dev/null +++ b/projects/fmcomms8/a10soc/system_project.tcl @@ -0,0 +1,226 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project fmcomms8_a10soc + +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl + +# files + +set_global_assignment -name VERILOG_FILE ../common/fmcomms8_spi.v +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/xilinx/common/ad_iobuf.v + +# fmcomms8 + +set_location_assignment PIN_N29 -to ref_clk_c ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_location_assignment PIN_N28 -to "ref_clk_c(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_location_assignment PIN_R29 -to ref_clk_d ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_location_assignment PIN_R28 -to "ref_clk_d(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_location_assignment PIN_T31 -to rx_serial_data_c[0] ; ## C06 FMC_HPC_DP0_M2C_P +set_location_assignment PIN_T30 -to "rx_serial_data_c[0](n)" ; ## C07 FMC_HPC_DP0_M2C_N +set_location_assignment PIN_R33 -to rx_serial_data_c[1] ; ## A02 FMC_HPC_DP1_M2C_P +set_location_assignment PIN_R32 -to "rx_serial_data_c[1](n)" ; ## A03 FMC_HPC_DP1_M2C_N +set_location_assignment PIN_P35 -to rx_serial_data_c[2] ; ## A06 FMC_HPC_DP2_M2C_P +set_location_assignment PIN_P34 -to "rx_serial_data_c[2](n)" ; ## A07 FMC_HPC_DP2_M2C_N +set_location_assignment PIN_P31 -to rx_serial_data_c[3] ; ## A10 FMC_HPC_DP3_M2C_P +set_location_assignment PIN_P30 -to "rx_serial_data_c[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N +set_location_assignment PIN_N37 -to tx_serial_data_c[0] ; ## C02 FMC_HPC_DP0_C2M_P (tx_serial_data_p[1]) +set_location_assignment PIN_N36 -to "tx_serial_data_c[0](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_serial_data_n[1]) +set_location_assignment PIN_M39 -to tx_serial_data_c[1] ; ## A22 FMC_HPC_DP1_C2M_P (tx_serial_data_p[0]) +set_location_assignment PIN_M38 -to "tx_serial_data_c[1](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_serial_data_n[0]) +set_location_assignment PIN_L37 -to tx_serial_data_c[2] ; ## A26 FMC_HPC_DP2_C2M_P +set_location_assignment PIN_L36 -to "tx_serial_data_c[2](n)" ; ## A27 FMC_HPC_DP2_C2M_N +set_location_assignment PIN_K39 -to tx_serial_data_c[3] ; ## A30 FMC_HPC_DP3_C2M_P +set_location_assignment PIN_K38 -to "tx_serial_data_c[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N + +set_location_assignment PIN_N33 -to rx_serial_data_d[0] ; ## A14 FMC_HPC_DP4_M2C_P +set_location_assignment PIN_N32 -to "rx_serial_data_d[0](n)" ; ## A15 FMC_HPC_DP4_M2C_N +set_location_assignment PIN_M35 -to rx_serial_data_d[1] ; ## A18 FMC_HPC_DP5_M2C_P +set_location_assignment PIN_M34 -to "rx_serial_data_d[1](n)" ; ## A19 FMC_HPC_DP5_M2C_N +set_location_assignment PIN_M31 -to rx_serial_data_d[2] ; ## B16 FMC_HPC_DP6_M2C_P +set_location_assignment PIN_M30 -to "rx_serial_data_d[2](n)" ; ## B17 FMC_HPC_DP6_M2C_N +set_location_assignment PIN_L33 -to rx_serial_data_d[3] ; ## B12 FMC_HPC_DP7_M2C_P +set_location_assignment PIN_L32 -to "rx_serial_data_d[3](n)" ; ## B13 FMC_HPC_DP7_M2C_N +set_location_assignment PIN_J37 -to tx_serial_data_d[0] ; ## A34 FMC_HPC_DP4_C2M_P +set_location_assignment PIN_J36 -to "tx_serial_data_d[0](n)" ; ## A35 FMC_HPC_DP4_C2M_N +set_location_assignment PIN_H39 -to tx_serial_data_d[1] ; ## A38 FMC_HPC_DP5_C2M_P +set_location_assignment PIN_H38 -to "tx_serial_data_d[1](n)" ; ## A39 FMC_HPC_DP5_C2M_N +set_location_assignment PIN_G37 -to tx_serial_data_d[2] ; ## B36 FMC_HPC_DP6_C2M_P +set_location_assignment PIN_G36 -to "tx_serial_data_d[2](n)" ; ## B37 FMC_HPC_DP6_C2M_N +set_location_assignment PIN_F39 -to tx_serial_data_d[3] ; ## B32 FMC_HPC_DP7_C2M_P +set_location_assignment PIN_F38 -to "tx_serial_data_d[3](n)" ; ## B33 FMC_HPC_DP7_C2M_N + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data_c +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data_d +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data_c +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data_d + +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk_c +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk_d +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data_c +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data_c +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data_d +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data_d + +# Merge RX and TX into single transceiver +for {set i 0} {$i < 4} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_c_${i} -to rx_serial_data_c[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_c_${i} -to tx_serial_data_c[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_d_${i} -to rx_serial_data_d[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_d_${i} -to tx_serial_data_d[${i}] +} + +set_location_assignment PIN_C9 -to rx_sync_c ; ## H16 FMC_HPC_LA11_P +set_location_assignment PIN_D9 -to rx_sync_c(n) ; ## H17 FMC_HPC_LA11_N +set_location_assignment PIN_M12 -to rx_os_sync_c ; ## G15 FMC_HPC_LA12_P +set_location_assignment PIN_N13 -to rx_os_sync_c(n) ; ## G16 FMC_HPC_LA12_N +set_location_assignment PIN_G5 -to tx_sync_c ; ## H22 FMC_HPC_LA19_P +set_location_assignment PIN_G6 -to tx_sync_c(n) ; ## H23 FMC_HPC_LA19_N +set_location_assignment PIN_E12 -to core_clk_c ; ## D08 FMC_HPC_LA01_CC_P +set_location_assignment PIN_E13 -to core_clk_c(n) ; ## D09 FMC_HPC_LA01_CC_N +set_location_assignment PIN_E5 -to sysref_c ; ## H04 FMC_HPC_CLK0_M2C_P +set_location_assignment PIN_F5 -to sysref_c(n) ; ## H05 FMC_HPC_CLK0_M2C_N +set_location_assignment PIN_C3 -to tx_sync_c_1 ; ## G21 FMC_HPC_LA20_P +set_location_assignment PIN_C4 -to tx_sync_c_1(n) ; ## G22 FMC_HPC_LA20_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_c +set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync_c +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_c +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_c_1 +set_instance_assignment -name IO_STANDARD LVDS -to sysref_c +set_instance_assignment -name IO_STANDARD LVDS -to core_clk_c +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_c +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_c_1 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref_c +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to core_clk_c + +set_location_assignment PIN_D4 -to rx_sync_d ; ## H19 FMC_HPC_LA15_P +set_location_assignment PIN_D5 -to rx_sync_d(n) ; ## H20 FMC_HPC_LA15_N +set_location_assignment PIN_D6 -to rx_os_sync_d ; ## G18 FMC_HPC_LA16_P +set_location_assignment PIN_E6 -to rx_os_sync_d(n) ; ## G19 FMC_HPC_LA16_N +set_location_assignment PIN_C2 -to tx_sync_d ; ## H25 FMC_HPC_LA21_P +set_location_assignment PIN_D3 -to tx_sync_d(n) ; ## H26 FMC_HPC_LA21_N +set_location_assignment PIN_W5 -to sysref_d ; ## G02 FMC_HPC_CLK1_M2C_P +set_location_assignment PIN_W6 -to sysref_d(n) ; ## G03 FMC_HPC_CLK1_M2C_N +set_location_assignment PIN_G14 -to core_clk_d ; ## G06 FMC_HPC_LA00_CC_P +set_location_assignment PIN_H14 -to core_clk_d(n) ; ## G07 FMC_HPC_LA00_CC_N +set_location_assignment PIN_F4 -to tx_sync_d_1 ; ## G24 FMC_HPC_LA22_P +set_location_assignment PIN_G4 -to tx_sync_d_1(n) ; ## G25 FMC_HPC_LA22_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_d +set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync_d +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_d +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_d_1 +set_instance_assignment -name IO_STANDARD LVDS -to sysref_d +set_instance_assignment -name IO_STANDARD LVDS -to core_clk_d +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_d +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_d_1 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref_d +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to core_clk_d + +set_location_assignment PIN_D1 -to spi_csn_hmc7044 ; ## D24 FMC_HPC_LA23_N +set_location_assignment PIN_F13 -to spi_csn_adrv9009_c ; ## D11 FMC_HPC_LA05_P +set_location_assignment PIN_A12 -to spi_csn_adrv9009_d ; ## D14 FMC_HPC_LA09_P +set_location_assignment PIN_C1 -to spi_clk ; ## D23 FMC_HPC_LA23_P +set_location_assignment PIN_G2 -to spi_sdio ; ## D27 FMC_HPC_LA26_N +set_location_assignment PIN_F2 -to spi_miso ; ## D26 FMC_HPC_LA26_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_hmc7044 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adrv9009_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adrv9009_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_sdio +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso + +set_location_assignment PIN_A7 -to adrv9009_tx1_enable_c ; ## C14 FMC_HPC_LA10_P +set_location_assignment PIN_A8 -to adrv9009_tx2_enable_c ; ## C15 FMC_HPC_LA10_N +set_location_assignment PIN_A10 -to adrv9009_rx1_enable_c ; ## C10 FMC_HPC_LA06_P +set_location_assignment PIN_B10 -to adrv9009_rx2_enable_c ; ## C11 FMC_HPC_LA06_N +set_location_assignment PIN_J11 -to adrv9009_reset_b_c ; ## D17 FMC_HPC_LA13_P +set_location_assignment PIN_E3 -to adrv9009_gpint_c ; ## G27 FMC_HPC_LA25_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx1_enable_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx2_enable_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx1_enable_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx2_enable_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_reset_b_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpint_c + +set_location_assignment PIN_G1 -to adrv9009_tx1_enable_d ; ## C26 FMC_HPC_LA27_P +set_location_assignment PIN_H2 -to adrv9009_tx2_enable_d ; ## C27 FMC_HPC_LA27_N +set_location_assignment PIN_J9 -to adrv9009_rx1_enable_d ; ## C18 FMC_HPC_LA14_P +set_location_assignment PIN_J10 -to adrv9009_rx2_enable_d ; ## C19 FMC_HPC_LA14_N +set_location_assignment PIN_K11 -to adrv9009_reset_b_d ; ## D18 FMC_HPC_LA13_N +set_location_assignment PIN_F3 -to adrv9009_gpint_d ; ## G28 FMC_HPC_LA25_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx1_enable_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx2_enable_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx1_enable_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx2_enable_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_reset_b_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpint_d + +set_location_assignment PIN_G7 -to fan_tach ; ## C22 FMC_HPC_LA18_CC_P +set_location_assignment PIN_H7 -to fan_pwm ; ## C23 FMC_HPC_LA18_CC_P +set_location_assignment PIN_C14 -to hmc7044_reset ; ## G09 FMC_HPC_LA03_P +set_location_assignment PIN_D14 -to hmc7044_sync ; ## G10 FMC_HPC_LA03_N +set_location_assignment PIN_B11 -to hmc7044_gpio_1 ; ## G12 FMC_HPC_LA08_P +set_location_assignment PIN_B12 -to hmc7044_gpio_2 ; ## G13 FMC_HPC_LA08_N +set_location_assignment PIN_A9 -to hmc7044_gpio_3 ; ## H13 FMC_HPC_LA07_P +set_location_assignment PIN_B9 -to hmc7044_gpio_4 ; ## H14 FMC_HPC_LA07_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to fan_tach +set_instance_assignment -name IO_STANDARD "1.8 V" -to fan_pwm +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc7044_reset +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc7044_sync +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc7044_gpio_1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc7044_gpio_2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc7044_gpio_3 +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc7044_gpio_4 + +# single ended default + +set_location_assignment PIN_N9 -to adrv9009_gpio_00_c ; ## G30 FMC_HPC_LA29_P +set_location_assignment PIN_P8 -to adrv9009_gpio_01_c ; ## G33 FMC_HPC_LA31_P +set_location_assignment PIN_P11 -to adrv9009_gpio_02_c ; ## G36 FMC_HPC_LA33_P +set_location_assignment PIN_C13 -to adrv9009_gpio_03_c ; ## H07 FMC_HPC_LA02_P +set_location_assignment PIN_H12 -to adrv9009_gpio_04_c ; ## H10 FMC_HPC_LA04_P +set_location_assignment PIN_E1 -to adrv9009_gpio_05_c ; ## H28 FMC_HPC_LA24_P +set_location_assignment PIN_L5 -to adrv9009_gpio_06_c ; ## H31 FMC_HPC_LA28_P +set_location_assignment PIN_P9 -to adrv9009_gpio_07_c ; ## H34 FMC_HPC_LA30_P +set_location_assignment PIN_L8 -to adrv9009_gpio_08_c ; ## H37 FMC_HPC_LA32_P +set_location_assignment PIN_P10 -to adrv9009_gpio_00_d ; ## G31 FMC_HPC_LA29_N +set_location_assignment PIN_R8 -to adrv9009_gpio_01_d ; ## G34 FMC_HPC_LA31_N +set_location_assignment PIN_R11 -to adrv9009_gpio_02_d ; ## G37 FMC_HPC_LA33_N +set_location_assignment PIN_D13 -to adrv9009_gpio_03_d ; ## H08 FMC_HPC_LA02_N +set_location_assignment PIN_H13 -to adrv9009_gpio_04_d ; ## H11 FMC_HPC_LA04_N +set_location_assignment PIN_E2 -to adrv9009_gpio_05_d ; ## H29 FMC_HPC_LA24_N +set_location_assignment PIN_M5 -to adrv9009_gpio_06_d ; ## H32 FMC_HPC_LA28_N +set_location_assignment PIN_R10 -to adrv9009_gpio_07_d ; ## H35 FMC_HPC_LA30_N +set_location_assignment PIN_L9 -to adrv9009_gpio_08_d ; ## H38 FMC_HPC_LA32_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_00_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_01_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_02_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_03_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_04_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_05_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_06_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_07_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_08_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_00_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_01_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_02_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_03_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_04_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_05_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_06_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_07_d +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio_08_d + +# set optimization to get a better timing closure +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +execute_flow -compile diff --git a/projects/fmcomms8/a10soc/system_qsys.tcl b/projects/fmcomms8/a10soc/system_qsys.tcl new file mode 100755 index 000000000..0a956a976 --- /dev/null +++ b/projects/fmcomms8/a10soc/system_qsys.tcl @@ -0,0 +1,17 @@ + +set dac_fifo_address_width 16 + +source $ad_hdl_dir/projects/scripts/adi_pd_intel.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl +source ../common/fmcomms8_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +set sys_cstring "sys rom custom string placeholder"; +sysid_gen_sys_init_file $sys_cstring; + diff --git a/projects/fmcomms8/a10soc/system_top.v b/projects/fmcomms8/a10soc/system_top.v new file mode 100755 index 000000000..ffa9cfcf7 --- /dev/null +++ b/projects/fmcomms8/a10soc/system_top.v @@ -0,0 +1,423 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // hps-ddr4 (32) + + input hps_ddr_ref_clk, + output [ 0:0] hps_ddr_clk_p, + output [ 0:0] hps_ddr_clk_n, + output [ 16:0] hps_ddr_a, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_reset_n, + output [ 0:0] hps_ddr_act_n, + output [ 0:0] hps_ddr_par, + input [ 0:0] hps_ddr_alert_n, + inout [ 3:0] hps_ddr_dqs_p, + inout [ 3:0] hps_ddr_dqs_n, + inout [ 31:0] hps_ddr_dq, + inout [ 3:0] hps_ddr_dbi_n, + input hps_ddr_rzq, + + // pl-ddr4 + + input sys_ddr_ref_clk, + output [ 0:0] sys_ddr_clk_p, + output [ 0:0] sys_ddr_clk_n, + output [ 16:0] sys_ddr_a, + output [ 1:0] sys_ddr_ba, + output [ 0:0] sys_ddr_bg, + output [ 0:0] sys_ddr_cke, + output [ 0:0] sys_ddr_cs_n, + output [ 0:0] sys_ddr_odt, + output [ 0:0] sys_ddr_reset_n, + output [ 0:0] sys_ddr_act_n, + output [ 0:0] sys_ddr_par, + input [ 0:0] sys_ddr_alert_n, + inout [ 7:0] sys_ddr_dqs_p, + inout [ 7:0] sys_ddr_dqs_n, + inout [ 63:0] sys_ddr_dq, + inout [ 7:0] sys_ddr_dbi_n, + input sys_ddr_rzq, + + // hps-ethernet + + input [ 0:0] hps_eth_rxclk, + input [ 0:0] hps_eth_rxctl, + input [ 3:0] hps_eth_rxd, + output [ 0:0] hps_eth_txclk, + output [ 0:0] hps_eth_txctl, + output [ 3:0] hps_eth_txd, + output [ 0:0] hps_eth_mdc, + inout [ 0:0] hps_eth_mdio, + + // hps-sdio + + output [ 0:0] hps_sdio_clk, + inout [ 0:0] hps_sdio_cmd, + inout [ 7:0] hps_sdio_d, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // hps-gpio (max-v-u16) + + inout [ 3:0] hps_gpio, + + // gpio (max-v-u21) + + input [ 7:0] gpio_bd_i, + output [ 3:0] gpio_bd_o, + + // adrv9009-interface + + input ref_clk_c, + input core_clk_c, + input [ 3:0] rx_serial_data_c, + output [ 3:0] tx_serial_data_c, + output rx_sync_c, + output rx_os_sync_c, + input tx_sync_c, + input tx_sync_c_1, + input sysref_c, + + output adrv9009_tx1_enable_c, + output adrv9009_tx2_enable_c, + output adrv9009_rx1_enable_c, + output adrv9009_rx2_enable_c, + output adrv9009_reset_b_c, + input adrv9009_gpint_c, + + inout adrv9009_gpio_00_c, + inout adrv9009_gpio_01_c, + inout adrv9009_gpio_02_c, + inout adrv9009_gpio_03_c, + inout adrv9009_gpio_04_c, + inout adrv9009_gpio_05_c, + inout adrv9009_gpio_06_c, + inout adrv9009_gpio_07_c, + inout adrv9009_gpio_08_c, + + input ref_clk_d, + input core_clk_d, + input [ 3:0] rx_serial_data_d, + output [ 3:0] tx_serial_data_d, + output rx_sync_d, + output rx_os_sync_d, + input tx_sync_d, + input tx_sync_d_1, + input sysref_d, + + output adrv9009_tx1_enable_d, + output adrv9009_tx2_enable_d, + output adrv9009_rx1_enable_d, + output adrv9009_rx2_enable_d, + output adrv9009_reset_b_d, + input adrv9009_gpint_d, + + inout adrv9009_gpio_00_d, + inout adrv9009_gpio_01_d, + inout adrv9009_gpio_02_d, + inout adrv9009_gpio_03_d, + inout adrv9009_gpio_04_d, + inout adrv9009_gpio_05_d, + inout adrv9009_gpio_06_d, + inout adrv9009_gpio_07_d, + inout adrv9009_gpio_08_d, + + input fan_tach, + input fan_pwm, + output hmc7044_reset, + output hmc7044_sync, + inout hmc7044_gpio_1, + inout hmc7044_gpio_2, + inout hmc7044_gpio_3, + inout hmc7044_gpio_4, + output spi_csn_hmc7044, + output spi_csn_adrv9009_c, + output spi_csn_adrv9009_d, + + output spi_clk, + inout spi_sdio, + input spi_miso); + + // internal signals + + wire sys_ddr_cal_success; + wire sys_ddr_cal_fail; + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire [ 7:0] spi_csn_s; + wire dac_fifo_bypass; + wire spi_mosi; + wire spi0_miso; + + wire rx_sync; + wire rx_os_sync; + wire tx_sync; + + wire [ 22:0] fmcomms8_gpio; + + // assignments + + assign spi_csn_adrv9009_c = spi_csn_s[0]; + assign spi_csn_adrv9009_d = spi_csn_s[1]; + assign spi_csn_hmc7044 = spi_csn_s[2]; + + fmcomms8_spi i_spi ( + .spi_csn(spi_csn_s), + .spi_clk(spi_clk), + .spi_mosi(spi_mosi), + .spi_miso_i(spi_miso), + .spi_miso_o(spi0_miso), + .spi_sdio(spi_sdio)); + + assign rx_sync_c = rx_sync; + assign rx_sync_d = rx_sync; + + assign rx_os_sync_c = rx_os_sync; + assign rx_os_sync_d = rx_os_sync; + + assign tx_sync = tx_sync_c & tx_sync_d; + + assign adrv9009_gpio_00_c = fmcomms8_gpio[0]; + assign adrv9009_gpio_01_c = fmcomms8_gpio[1]; + assign adrv9009_gpio_02_c = fmcomms8_gpio[2]; + assign adrv9009_gpio_03_c = fmcomms8_gpio[3]; + assign adrv9009_gpio_04_c = fmcomms8_gpio[4]; + assign adrv9009_gpio_05_c = fmcomms8_gpio[5]; + assign adrv9009_gpio_06_c = fmcomms8_gpio[6]; + assign adrv9009_gpio_07_c = fmcomms8_gpio[7]; + assign adrv9009_gpio_08_c = fmcomms8_gpio[8]; + + assign adrv9009_gpio_00_d = fmcomms8_gpio[9]; + assign adrv9009_gpio_01_d = fmcomms8_gpio[10]; + assign adrv9009_gpio_02_d = fmcomms8_gpio[11]; + assign adrv9009_gpio_03_d = fmcomms8_gpio[12]; + assign adrv9009_gpio_04_d = fmcomms8_gpio[13]; + assign adrv9009_gpio_05_d = fmcomms8_gpio[14]; + assign adrv9009_gpio_06_d = fmcomms8_gpio[15]; + assign adrv9009_gpio_07_d = fmcomms8_gpio[16]; + assign adrv9009_gpio_08_d = fmcomms8_gpio[17]; + + assign hmc7044_gpio_1 = fmcomms8_gpio[18]; + assign hmc7044_gpio_2 = fmcomms8_gpio[19]; + assign hmc7044_gpio_3 = fmcomms8_gpio[20]; + assign hmc7044_gpio_4 = fmcomms8_gpio[21]; + assign hmc7044_reset = gpio_o[45]; + assign hmc7044_sync = gpio_o[46]; + + assign adrv9009_tx1_enable_d = gpio_o[39]; + assign adrv9009_tx2_enable_d = gpio_o[40]; + assign adrv9009_rx1_enable_d = gpio_o[41]; + assign adrv9009_rx2_enable_d = gpio_o[42]; + assign adrv9009_reset_b_d = gpio_o[43]; + assign gpio_i[44] = adrv9009_gpint_d; + + assign adrv9009_tx1_enable_c = gpio_o[33]; + assign adrv9009_tx2_enable_c = gpio_o[34]; + assign adrv9009_rx1_enable_c = gpio_o[35]; + assign adrv9009_rx2_enable_c = gpio_o[36]; + assign adrv9009_reset_b_c = gpio_o[37]; + assign gpio_i[38] = adrv9009_gpint_c; + + assign dac_fifo_bypass = gpio_o[32]; + + assign gpio_i[63:45] = gpio_o[63:45]; + assign gpio_i[43:39] = gpio_o[43:39]; + assign gpio_i[37:32] = gpio_o[37:32]; + + // board stuff (max-v-u21) + + assign gpio_i[31:14] = gpio_o[31:14]; + assign gpio_i[13:13] = sys_ddr_cal_success; + assign gpio_i[12:12] = sys_ddr_cal_fail; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[3:0]; + + assign gpio_bd_o = gpio_o[3:0]; + + // peripheral reset + + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + + // instantiations + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_ddr_mem_mem_ck (sys_ddr_clk_p), + .sys_ddr_mem_mem_ck_n (sys_ddr_clk_n), + .sys_ddr_mem_mem_a (sys_ddr_a), + .sys_ddr_mem_mem_act_n (sys_ddr_act_n), + .sys_ddr_mem_mem_ba (sys_ddr_ba), + .sys_ddr_mem_mem_bg (sys_ddr_bg), + .sys_ddr_mem_mem_cke (sys_ddr_cke), + .sys_ddr_mem_mem_cs_n (sys_ddr_cs_n), + .sys_ddr_mem_mem_odt (sys_ddr_odt), + .sys_ddr_mem_mem_reset_n (sys_ddr_reset_n), + .sys_ddr_mem_mem_par (sys_ddr_par), + .sys_ddr_mem_mem_alert_n (sys_ddr_alert_n), + .sys_ddr_mem_mem_dqs (sys_ddr_dqs_p), + .sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n), + .sys_ddr_mem_mem_dq (sys_ddr_dq), + .sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n), + .sys_ddr_oct_oct_rzqin (sys_ddr_rzq), + .sys_ddr_ref_clk_clk (sys_ddr_ref_clk), + .sys_ddr_status_local_cal_success (sys_ddr_cal_success), + .sys_ddr_status_local_cal_fail (sys_ddr_cal_fail), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hps_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + .sys_hps_rstn_reset_n (sys_resetn), + .sys_rstn_reset_n (sys_resetn_s), + .sys_spi_MISO (spi0_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .tx_serial_data_tx_serial_data ({tx_serial_data_d,tx_serial_data_c}), + .tx_fifo_bypass_bypass (dac_fifo_bypass), + .fmcomms8_gpio_export (fmcomms8_gpio), + .core_clk_c_clk (core_clk_c), + .core_clk_d_clk (core_clk_d), + .tx_ref_clk_clk (ref_clk_c), + .tx_sync_export (tx_sync), + .tx_sysref_export (sysref_c), + .rx_serial_data_rx_serial_data ({rx_serial_data_d[1:0],rx_serial_data_c[1:0]}), + .rx_os_serial_data_rx_serial_data ({rx_serial_data_d[3:2],rx_serial_data_c[3:2]}), + .rx_os_ref_clk_clk (ref_clk_c), + .rx_os_sync_export (rx_os_sync), + .rx_os_sysref_export (sysref_c), + .rx_ref_clk_clk (ref_clk_d), + .rx_sync_export (rx_sync), + .rx_sysref_export (sysref_c)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms8/common/fmcomms8_qsys.tcl b/projects/fmcomms8/common/fmcomms8_qsys.tcl new file mode 100644 index 000000000..0894fb33b --- /dev/null +++ b/projects/fmcomms8/common/fmcomms8_qsys.tcl @@ -0,0 +1,366 @@ + +# TX parameters +set TX_NUM_OF_LANES 8 ; # L +set TX_NUM_OF_CONVERTERS 8 ; # M +set TX_SAMPLE_WIDTH 16 ; # N/NP + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \ + ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N) + +# RX parameters +set RX_NUM_OF_LANES 4 ; # L +set RX_NUM_OF_CONVERTERS 8 ; # M +set RX_SAMPLE_WIDTH 16 ; # N/NP + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \ + ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N) + +# RX Observation parameters +set RX_OS_NUM_OF_LANES 4 ; # L +set RX_OS_NUM_OF_CONVERTERS 4 ; # M +set RX_OS_SAMPLE_WIDTH 16 ; # N/NP + +set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 32 / \ + ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] ; # L * 32 / (M * N) + +set dac_fifo_name avl_fmcomms8_tx_fifo +set dac_data_width 256 +set dac_dma_data_width 256 + +# JESD204B/C clock bridges + + add_instance core_clk_c altera_clock_bridge + set_instance_parameter_value core_clk_c {EXPLICIT_CLOCK_RATE} {245760000} + + add_instance core_clk_d altera_clock_bridge + set_instance_parameter_value core_clk_d {EXPLICIT_CLOCK_RATE} {245760000} + +# fmcomms8_tx JESD204 + +add_instance fmcomms8_tx_jesd204 adi_jesd204 +set_instance_parameter_value fmcomms8_tx_jesd204 {ID} {0} +set_instance_parameter_value fmcomms8_tx_jesd204 {TX_OR_RX_N} {1} +set_instance_parameter_value fmcomms8_tx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value fmcomms8_tx_jesd204 {LANE_RATE} {9830.4} +set_instance_parameter_value fmcomms8_tx_jesd204 {REFCLK_FREQUENCY} {245.76} +set_instance_parameter_value fmcomms8_tx_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES +set_instance_parameter_value fmcomms8_tx_jesd204 {LANE_MAP} {1 0 2 3 4 5 6 7} +set_instance_parameter_value fmcomms8_tx_jesd204 {EXT_DEVICE_CLK_EN} {1} + +add_connection sys_clk.clk fmcomms8_tx_jesd204.sys_clk +add_connection sys_clk.clk_reset fmcomms8_tx_jesd204.sys_resetn +add_interface tx_ref_clk clock sink +set_interface_property tx_ref_clk EXPORT_OF fmcomms8_tx_jesd204.ref_clk +add_interface tx_serial_data conduit end +set_interface_property tx_serial_data EXPORT_OF fmcomms8_tx_jesd204.serial_data +add_interface tx_sysref conduit end +set_interface_property tx_sysref EXPORT_OF fmcomms8_tx_jesd204.sysref +add_interface tx_sync conduit end +set_interface_property tx_sync EXPORT_OF fmcomms8_tx_jesd204.sync + +# fmcomms8_rx JESD204 + +add_instance fmcomms8_rx_jesd204 adi_jesd204 +set_instance_parameter_value fmcomms8_rx_jesd204 {ID} {1} +set_instance_parameter_value fmcomms8_rx_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value fmcomms8_rx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value fmcomms8_rx_jesd204 {LANE_RATE} {9830.4} +set_instance_parameter_value fmcomms8_rx_jesd204 {REFCLK_FREQUENCY} {245.76} +set_instance_parameter_value fmcomms8_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value fmcomms8_rx_jesd204 {EXT_DEVICE_CLK_EN} {1} + +add_connection sys_clk.clk fmcomms8_rx_jesd204.sys_clk +add_connection sys_clk.clk_reset fmcomms8_rx_jesd204.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF fmcomms8_rx_jesd204.ref_clk +add_interface rx_serial_data conduit end +set_interface_property rx_serial_data EXPORT_OF fmcomms8_rx_jesd204.serial_data +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF fmcomms8_rx_jesd204.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF fmcomms8_rx_jesd204.sync + +# fmcomms8_rx_os JESD204 + +add_instance fmcomms8_rx_os_jesd204 adi_jesd204 +set_instance_parameter_value fmcomms8_rx_os_jesd204 {ID} {1} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {LANE_RATE} {9830.4} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {REFCLK_FREQUENCY} {245.76} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {NUM_OF_LANES} $RX_OS_NUM_OF_LANES +set_instance_parameter_value fmcomms8_rx_os_jesd204 {EXT_DEVICE_CLK_EN} {1} + +add_connection sys_clk.clk fmcomms8_rx_os_jesd204.sys_clk +add_connection sys_clk.clk_reset fmcomms8_rx_os_jesd204.sys_resetn +add_interface rx_os_ref_clk clock sink +set_interface_property rx_os_ref_clk EXPORT_OF fmcomms8_rx_os_jesd204.ref_clk +add_interface rx_os_serial_data conduit end +set_interface_property rx_os_serial_data EXPORT_OF fmcomms8_rx_os_jesd204.serial_data +add_interface rx_os_sysref conduit end +set_interface_property rx_os_sysref EXPORT_OF fmcomms8_rx_os_jesd204.sysref +add_interface rx_os_sync conduit end +set_interface_property rx_os_sync EXPORT_OF fmcomms8_rx_os_jesd204.sync + +# fmcomms8 TPL cores + +add_instance axi_fmcomms8_tx ad_ip_jesd204_tpl_dac +set_instance_parameter_value axi_fmcomms8_tx {ID} {0} +set_instance_parameter_value axi_fmcomms8_tx {NUM_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_fmcomms8_tx {NUM_LANES} $TX_NUM_OF_LANES +set_instance_parameter_value axi_fmcomms8_tx {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH +set_instance_parameter_value axi_fmcomms8_tx {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH + +add_instance axi_fmcomms8_rx ad_ip_jesd204_tpl_adc +set_instance_parameter_value axi_fmcomms8_rx {ID} {0} +set_instance_parameter_value axi_fmcomms8_rx {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_fmcomms8_rx {NUM_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value axi_fmcomms8_rx {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH +set_instance_parameter_value axi_fmcomms8_rx {CONVERTER_RESOLUTION} $RX_SAMPLE_WIDTH +set_instance_parameter_value axi_fmcomms8_rx {TWOS_COMPLEMENT} {1} + +add_instance axi_fmcomms8_rx_os ad_ip_jesd204_tpl_adc +set_instance_parameter_value axi_fmcomms8_rx_os {ID} {1} +set_instance_parameter_value axi_fmcomms8_rx_os {NUM_CHANNELS} $RX_OS_NUM_OF_CONVERTERS +set_instance_parameter_value axi_fmcomms8_rx_os {NUM_LANES} $RX_OS_NUM_OF_LANES +set_instance_parameter_value axi_fmcomms8_rx_os {BITS_PER_SAMPLE} $RX_OS_SAMPLE_WIDTH +set_instance_parameter_value axi_fmcomms8_rx_os {CONVERTER_RESOLUTION} $RX_OS_SAMPLE_WIDTH +set_instance_parameter_value axi_fmcomms8_rx_os {TWOS_COMPLEMENT} {1} + +add_connection sys_clk.clk axi_fmcomms8_tx.s_axi_clock +add_connection sys_clk.clk_reset axi_fmcomms8_tx.s_axi_reset +add_connection sys_clk.clk axi_fmcomms8_rx.s_axi_clock +add_connection sys_clk.clk_reset axi_fmcomms8_rx.s_axi_reset +add_connection sys_clk.clk axi_fmcomms8_rx_os.s_axi_clock +add_connection sys_clk.clk_reset axi_fmcomms8_rx_os.s_axi_reset + +add_connection core_clk_c.out_clk axi_fmcomms8_tx.link_clk +add_connection core_clk_c.out_clk fmcomms8_tx_jesd204.device_clk +add_connection axi_fmcomms8_tx.link_data fmcomms8_tx_jesd204.link_data +add_connection core_clk_d.out_clk axi_fmcomms8_rx.link_clk +add_connection core_clk_d.out_clk fmcomms8_rx_jesd204.device_clk +add_connection fmcomms8_rx_jesd204.link_sof axi_fmcomms8_rx.if_link_sof +add_connection fmcomms8_rx_jesd204.link_data axi_fmcomms8_rx.link_data +add_connection core_clk_c.out_clk axi_fmcomms8_rx_os.link_clk +add_connection core_clk_c.out_clk fmcomms8_rx_os_jesd204.device_clk +add_connection fmcomms8_rx_os_jesd204.link_sof axi_fmcomms8_rx_os.if_link_sof +add_connection fmcomms8_rx_os_jesd204.link_data axi_fmcomms8_rx_os.link_data + +# pack(s) & unpack(s) + +add_instance axi_fmcomms8_tx_upack util_upack2 +set_instance_parameter_value axi_fmcomms8_tx_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_fmcomms8_tx_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL +set_instance_parameter_value axi_fmcomms8_tx_upack {SAMPLE_DATA_WIDTH} $TX_SAMPLE_WIDTH +set_instance_parameter_value axi_fmcomms8_tx_upack {INTERFACE_TYPE} {1} +add_connection core_clk_c.out_clk axi_fmcomms8_tx_upack.clk +add_connection fmcomms8_tx_jesd204.link_reset axi_fmcomms8_tx_upack.reset +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + add_connection axi_fmcomms8_tx_upack.dac_ch_$i axi_fmcomms8_tx.dac_ch_$i +} + +add_instance axi_fmcomms8_rx_cpack util_cpack2 +set_instance_parameter_value axi_fmcomms8_rx_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_fmcomms8_rx_cpack {SAMPLES_PER_CHANNEL} $RX_SAMPLES_PER_CHANNEL +set_instance_parameter_value axi_fmcomms8_rx_cpack {SAMPLE_DATA_WIDTH} $RX_SAMPLE_WIDTH +add_connection fmcomms8_rx_jesd204.link_reset axi_fmcomms8_rx_cpack.reset +add_connection core_clk_d.out_clk axi_fmcomms8_rx_cpack.clk +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + add_connection axi_fmcomms8_rx.adc_ch_$i axi_fmcomms8_rx_cpack.adc_ch_$i +} +add_connection axi_fmcomms8_rx_cpack.if_fifo_wr_overflow axi_fmcomms8_rx.if_adc_dovf + +add_instance axi_fmcomms8_rx_os_cpack util_cpack2 +set_instance_parameter_value axi_fmcomms8_rx_os_cpack {NUM_OF_CHANNELS} $RX_OS_NUM_OF_CONVERTERS +set_instance_parameter_value axi_fmcomms8_rx_os_cpack {SAMPLES_PER_CHANNEL} $RX_OS_SAMPLES_PER_CHANNEL +set_instance_parameter_value axi_fmcomms8_rx_os_cpack {SAMPLE_DATA_WIDTH} $RX_OS_SAMPLE_WIDTH +add_connection fmcomms8_rx_os_jesd204.link_reset axi_fmcomms8_rx_os_cpack.reset +add_connection core_clk_c.out_clk axi_fmcomms8_rx_os_cpack.clk +for {set i 0} {$i < $RX_OS_NUM_OF_CONVERTERS} {incr i} { + add_connection axi_fmcomms8_rx_os.adc_ch_$i axi_fmcomms8_rx_os_cpack.adc_ch_$i +} +add_connection axi_fmcomms8_rx_os_cpack.if_fifo_wr_overflow axi_fmcomms8_rx_os.if_adc_dovf + +# dac fifo + +ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width + +add_interface tx_fifo_bypass conduit end +set_interface_property tx_fifo_bypass EXPORT_OF avl_fmcomms8_tx_fifo.if_bypass + +add_connection core_clk_c.out_clk avl_fmcomms8_tx_fifo.if_dac_clk +add_connection fmcomms8_tx_jesd204.link_reset avl_fmcomms8_tx_fifo.if_dac_rst +add_connection axi_fmcomms8_tx_upack.if_packed_fifo_rd_en avl_fmcomms8_tx_fifo.if_dac_valid +add_connection avl_fmcomms8_tx_fifo.if_dac_data axi_fmcomms8_tx_upack.if_packed_fifo_rd_data +add_connection avl_fmcomms8_tx_fifo.if_dac_dunf axi_fmcomms8_tx.if_dac_dunf + +# dac & adc dma + +add_instance axi_fmcomms8_tx_dma axi_dmac +set_instance_parameter_value axi_fmcomms8_tx_dma {ID} {0} +set_instance_parameter_value axi_fmcomms8_tx_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_fmcomms8_tx_dma {DMA_DATA_WIDTH_DEST} [expr $TX_SAMPLE_WIDTH * \ + $TX_NUM_OF_CONVERTERS * \ + $TX_SAMPLES_PER_CHANNEL] +set_instance_parameter_value axi_fmcomms8_tx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_fmcomms8_tx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_fmcomms8_tx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_fmcomms8_tx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_fmcomms8_tx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_fmcomms8_tx_dma {CYCLIC} {1} +set_instance_parameter_value axi_fmcomms8_tx_dma {DMA_TYPE_DEST} {1} +set_instance_parameter_value axi_fmcomms8_tx_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_fmcomms8_tx_dma {FIFO_SIZE} {16} +set_instance_parameter_value axi_fmcomms8_tx_dma {HAS_AXIS_TLAST} {1} + +add_connection sys_dma_clk.clk avl_fmcomms8_tx_fifo.if_dma_clk +add_connection sys_dma_clk.clk_reset avl_fmcomms8_tx_fifo.if_dma_rst +add_connection sys_dma_clk.clk axi_fmcomms8_tx_dma.if_m_axis_aclk +add_connection axi_fmcomms8_tx_dma.m_axis avl_fmcomms8_tx_fifo.s_axis +add_connection axi_fmcomms8_tx_dma.if_m_axis_xfer_req avl_fmcomms8_tx_fifo.if_dma_xfer_req +add_connection sys_clk.clk axi_fmcomms8_tx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_fmcomms8_tx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_fmcomms8_tx_dma.m_src_axi_clock +add_connection sys_dma_clk.clk_reset axi_fmcomms8_tx_dma.m_src_axi_reset + +add_instance axi_fmcomms8_rx_dma axi_dmac +set_instance_parameter_value axi_fmcomms8_rx_dma {ID} {0} +set_instance_parameter_value axi_fmcomms8_rx_dma {DMA_DATA_WIDTH_SRC} [expr $RX_SAMPLE_WIDTH * \ + $RX_NUM_OF_CONVERTERS * \ + $RX_SAMPLES_PER_CHANNEL] +set_instance_parameter_value axi_fmcomms8_rx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_fmcomms8_rx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_fmcomms8_rx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_fmcomms8_rx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_fmcomms8_rx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_fmcomms8_rx_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_fmcomms8_rx_dma {CYCLIC} {0} +set_instance_parameter_value axi_fmcomms8_rx_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_fmcomms8_rx_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_fmcomms8_rx_dma {FIFO_SIZE} {32} +add_connection core_clk_d.out_clk axi_fmcomms8_rx_dma.if_fifo_wr_clk +add_connection axi_fmcomms8_rx_cpack.if_packed_fifo_wr_en axi_fmcomms8_rx_dma.if_fifo_wr_en +add_connection axi_fmcomms8_rx_cpack.if_packed_fifo_wr_sync axi_fmcomms8_rx_dma.if_fifo_wr_sync +add_connection axi_fmcomms8_rx_cpack.if_packed_fifo_wr_data axi_fmcomms8_rx_dma.if_fifo_wr_din +add_connection axi_fmcomms8_rx_dma.if_fifo_wr_overflow axi_fmcomms8_rx_cpack.if_packed_fifo_wr_overflow +add_connection sys_clk.clk axi_fmcomms8_rx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_fmcomms8_rx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_fmcomms8_rx_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_fmcomms8_rx_dma.m_dest_axi_reset + +add_instance axi_fmcomms8_rx_os_dma axi_dmac +set_instance_parameter_value axi_fmcomms8_rx_os_dma {ID} {0} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {DMA_DATA_WIDTH_SRC} [expr 32*$RX_OS_NUM_OF_LANES] +set_instance_parameter_value axi_fmcomms8_rx_os_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {CYCLIC} {0} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_fmcomms8_rx_os_dma {FIFO_SIZE} {32} +add_connection core_clk_c.out_clk axi_fmcomms8_rx_os_dma.if_fifo_wr_clk +add_connection axi_fmcomms8_rx_os_cpack.if_packed_fifo_wr_en axi_fmcomms8_rx_os_dma.if_fifo_wr_en +add_connection axi_fmcomms8_rx_os_cpack.if_packed_fifo_wr_sync axi_fmcomms8_rx_os_dma.if_fifo_wr_sync +add_connection axi_fmcomms8_rx_os_cpack.if_packed_fifo_wr_data axi_fmcomms8_rx_os_dma.if_fifo_wr_din +add_connection axi_fmcomms8_rx_os_dma.if_fifo_wr_overflow axi_fmcomms8_rx_os_cpack.if_packed_fifo_wr_overflow +add_connection sys_clk.clk axi_fmcomms8_rx_os_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_fmcomms8_rx_os_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_fmcomms8_rx_os_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_fmcomms8_rx_os_dma.m_dest_axi_reset + +# fmcomms8 gpio + +add_instance avl_fmcomms8_gpio altera_avalon_pio +set_instance_parameter_value avl_fmcomms8_gpio {direction} {Bidir} +set_instance_parameter_value avl_fmcomms8_gpio {generateIRQ} {1} +set_instance_parameter_value avl_fmcomms8_gpio {width} {22} +add_connection sys_clk.clk avl_fmcomms8_gpio.clk +add_connection sys_clk.clk_reset avl_fmcomms8_gpio.reset +add_interface fmcomms8_gpio conduit end +set_interface_property fmcomms8_gpio EXPORT_OF avl_fmcomms8_gpio.external_connection + +# reconfig sharing + +for {set i 0} {$i < 8} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 fmcomms8_tx_jesd204.phy_reconfig_${i} + +# if {$i < 2} { +# add_connection avl_adxcfg_${i}.rcfg_m1 fmcomms8_rx_jesd204.phy_reconfig_${i} +# } else { +# set j [expr $i - 2] +# add_connection avl_adxcfg_${i}.rcfg_m1 fmcomms8_rx_os_jesd204.phy_reconfig_${j} +# } +} + add_connection avl_adxcfg_0.rcfg_m1 fmcomms8_rx_jesd204.phy_reconfig_0 + add_connection avl_adxcfg_1.rcfg_m1 fmcomms8_rx_jesd204.phy_reconfig_1 + add_connection avl_adxcfg_4.rcfg_m1 fmcomms8_rx_jesd204.phy_reconfig_2 + add_connection avl_adxcfg_5.rcfg_m1 fmcomms8_rx_jesd204.phy_reconfig_3 + add_connection avl_adxcfg_2.rcfg_m1 fmcomms8_rx_os_jesd204.phy_reconfig_0 + add_connection avl_adxcfg_3.rcfg_m1 fmcomms8_rx_os_jesd204.phy_reconfig_1 + add_connection avl_adxcfg_6.rcfg_m1 fmcomms8_rx_os_jesd204.phy_reconfig_2 + add_connection avl_adxcfg_7.rcfg_m1 fmcomms8_rx_os_jesd204.phy_reconfig_3 + +add_interface core_clk_c clock sink +set_interface_property core_clk_c EXPORT_OF core_clk_c.in_clk + +add_interface core_clk_d clock sink +set_interface_property core_clk_d EXPORT_OF core_clk_d.in_clk + +# addresses + +ad_cpu_interconnect 0x00020000 fmcomms8_tx_jesd204.link_reconfig +ad_cpu_interconnect 0x00024000 fmcomms8_tx_jesd204.link_management +ad_cpu_interconnect 0x00025000 fmcomms8_tx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00026000 fmcomms8_tx_jesd204.lane_pll_reconfig +ad_cpu_interconnect 0x00028000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x0002c000 avl_adxcfg_4.rcfg_s0 +ad_cpu_interconnect 0x0002d000 avl_adxcfg_5.rcfg_s0 +ad_cpu_interconnect 0x0002e000 avl_adxcfg_6.rcfg_s0 +ad_cpu_interconnect 0x0002f000 avl_adxcfg_7.rcfg_s0 +ad_cpu_interconnect 0x00070000 axi_fmcomms8_tx_dma.s_axi + +ad_cpu_interconnect 0x00030000 fmcomms8_rx_jesd204.link_reconfig +ad_cpu_interconnect 0x00034000 fmcomms8_rx_jesd204.link_management +ad_cpu_interconnect 0x00035000 fmcomms8_rx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x0003a000 avl_adxcfg_4.rcfg_s1 +ad_cpu_interconnect 0x0003b000 avl_adxcfg_5.rcfg_s1 +ad_cpu_interconnect 0x0003c000 axi_fmcomms8_rx_dma.s_axi + +ad_cpu_interconnect 0x00040000 fmcomms8_rx_os_jesd204.link_reconfig +ad_cpu_interconnect 0x00044000 fmcomms8_rx_os_jesd204.link_management +ad_cpu_interconnect 0x00045000 fmcomms8_rx_os_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00048000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x00049000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x0004a000 avl_adxcfg_6.rcfg_s1 +ad_cpu_interconnect 0x0004b000 avl_adxcfg_7.rcfg_s1 +ad_cpu_interconnect 0x0004c000 axi_fmcomms8_rx_os_dma.s_axi + +ad_cpu_interconnect 0x00050000 axi_fmcomms8_rx.s_axi +ad_cpu_interconnect 0x00054000 axi_fmcomms8_tx.s_axi +ad_cpu_interconnect 0x00058000 axi_fmcomms8_rx_os.s_axi +ad_cpu_interconnect 0x00060000 avl_fmcomms8_gpio.s1 + +# dma interconnects + +ad_dma_interconnect axi_fmcomms8_tx_dma.m_src_axi +ad_dma_interconnect axi_fmcomms8_rx_dma.m_dest_axi +ad_dma_interconnect axi_fmcomms8_rx_os_dma.m_dest_axi + +# interrupts + +ad_cpu_interrupt 11 axi_fmcomms8_tx_dma.interrupt_sender +ad_cpu_interrupt 12 axi_fmcomms8_rx_dma.interrupt_sender +ad_cpu_interrupt 13 axi_fmcomms8_rx_os_dma.interrupt_sender +ad_cpu_interrupt 14 avl_fmcomms8_gpio.irq +