From 663588eeafa090a473b34cf5913c09cbffeb952b Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 29 Jul 2014 09:15:30 -0400 Subject: [PATCH] daq2/kcu105: working ddr version --- projects/common/kcu105/kcu105_system_bd.tcl | 114 +++++--- .../common/kcu105/kcu105_system_constr.xdc | 136 +-------- projects/common/kcu105/kcu105_system_mig.tcl | 266 +++++++++--------- projects/daq2/kcu105/system_top.v | 62 ++-- 4 files changed, 243 insertions(+), 335 deletions(-) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index ed520de98..8b882ebe0 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -3,15 +3,13 @@ # interface ports set sys_rst [create_bd_port -dir I -type rst sys_rst] -set sys_clk_p [create_bd_port -dir I sys_clk_p] -set sys_clk_n [create_bd_port -dir I sys_clk_n] -set sys_125m_clk_p [create_bd_port -dir I sys_125m_clk_p] -set sys_125m_clk_n [create_bd_port -dir I sys_125m_clk_n] +set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] set c0_ddr4 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4] set phy_rst_n [create_bd_port -dir O -type rst phy_rst_n] set phy_sd [create_bd_port -dir I phy_sd] +set phy_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 phy_clk] set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio] set sgmii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii] @@ -40,6 +38,8 @@ set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data] set spdif [create_bd_port -dir O spdif] set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst +set_property -dict [list CONFIG.FREQ_HZ {300000000}] $sys_clk +set_property -dict [list CONFIG.FREQ_HZ {625000000}] $phy_clk # instance: microblaze - processor @@ -86,6 +86,8 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:5.0 axi_ddr_cntrl] source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl +set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen] + # instance: axi interconnect (lite) set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] @@ -105,9 +107,36 @@ set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect # instance: default peripherals +set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 axi_ethernet_clkgen] +set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.CLKOUT2_USED {true}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {312}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.CLKOUT3_USED {true}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {625}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.CLKOUT4_USED {false}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen +set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen + +set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen] + set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.1 axi_ethernet] set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet set_property -dict [list CONFIG.ENABLE_LVDS {true}] $axi_ethernet +set_property -dict [list CONFIG.Statistics_Counters {true}] $axi_ethernet +set_property -dict [list CONFIG.MCAST_EXTEND {true}] $axi_ethernet +set_property -dict [list CONFIG.TXVLAN_TRAN {true}] $axi_ethernet +set_property -dict [list CONFIG.TXVLAN_TAG {true}] $axi_ethernet +set_property -dict [list CONFIG.TXVLAN_STRP {true}] $axi_ethernet +set_property -dict [list CONFIG.RXVLAN_TRAN {true}] $axi_ethernet +set_property -dict [list CONFIG.RXVLAN_TAG {true}] $axi_ethernet +set_property -dict [list CONFIG.RXVLAN_STRP {true}] $axi_ethernet +set_property -dict [list CONFIG.TXMEM {32k}] $axi_ethernet +set_property -dict [list CONFIG.TXCSUM {None}] $axi_ethernet +set_property -dict [list CONFIG.RXMEM {32k}] $axi_ethernet +set_property -dict [list CONFIG.RXCSUM {None}] $axi_ethernet +set_property -dict [list CONFIG.SupportLevel {0}] $axi_ethernet set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma] set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma @@ -204,12 +233,14 @@ connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get set sys_reset_source [get_bd_pins sys_rstgen/peripheral_reset] set sys_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] +set sys_mem_resetn_source [get_bd_pins axi_ddr_cntrl_rstgen/peripheral_aresetn] set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk] set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1] set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2] connect_bd_net -net sys_cpu_rst $sys_reset_source connect_bd_net -net sys_cpu_rstn $sys_resetn_source +connect_bd_net -net sys_mem_rstn $sys_mem_resetn_source connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source connect_bd_net -net sys_mem_clk $sys_mem_clk_source connect_bd_net -net sys_200m_clk $sys_200m_clk_source @@ -217,14 +248,14 @@ connect_bd_net -net sys_200m_clk $sys_200m_clk_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_resetn_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_resetn_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_resetn_source -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_resetn_source +connect_bd_net -net sys_mem_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_mem_resetn_source connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_mem_clk_source connect_bd_net -net sys_cpu_rstn [get_bd_pins sys_mb_debug/S_AXI_ARESETN] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn] +connect_bd_net -net sys_mem_rstn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn] connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_resetn_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_uart/s_axi_aresetn] connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_timer/s_axi_aresetn] @@ -299,7 +330,7 @@ connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG] connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S] connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM] -connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_resetn_source +connect_bd_net -net sys_mem_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_mem_resetn_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_resetn_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_resetn_source connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_resetn_source @@ -312,18 +343,6 @@ connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_cpu_clk_source connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_cpu_clk_source -# ethernet & ethernet dma - -connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n] -connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n] -connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n] -connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n] - -connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S] -connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL] -connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM] -connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS] - # defaults (interrupts) connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt] @@ -340,32 +359,51 @@ connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3] connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4] -# defaults (external interface) +# defaults (ddr) -connect_bd_net [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect] -connect_bd_net [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst] -connect_bd_net [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] [get_bd_pins sys_rstgen/ext_reset_in] +connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ddr_cntrl/C0_SYS_CLK] +connect_bd_intf_net -intf_net c0_ddr4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4] -connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_p] -connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_n] +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst] -connect_bd_intf_net -intf_net axi_ddr_cntrl_c0_ddr4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4] +connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] +connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins sys_rstgen/ext_reset_in] +connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ethernet_rstgen/ext_reset_in] +connect_bd_net -net axi_ddr_cntrl_rst [get_bd_pins axi_ddr_cntrl_rstgen/ext_reset_in] +connect_bd_net -net sys_mem_clk [get_bd_pins axi_ddr_cntrl_rstgen/slowest_sync_clk] -connect_bd_net -net axi_ethernet_phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n] -connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio] -connect_bd_intf_net -intf_net axi_ethernet_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet/sgmii] -connect_bd_net -net sys_125m_clk_p [get_bd_ports sys_125m_clk_p] [get_bd_pins axi_ethernet/ref_clk_125_p] -connect_bd_net -net sys_125m_clk_n [get_bd_ports sys_125m_clk_n] [get_bd_pins axi_ethernet/ref_clk_125_n] +# defaults (ethernet) -connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx] -connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx] +connect_bd_intf_net -intf_net phy_clk [get_bd_intf_ports phy_clk] [get_bd_intf_pins axi_ethernet_clkgen/CLK_IN1_D] +connect_bd_intf_net -intf_net mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio] +connect_bd_intf_net -intf_net sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet/sgmii] +connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S] +connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL] +connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM] +connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS] -connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio] -connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] -connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] +connect_bd_net -net phy_sd [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect] +connect_bd_net -net phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n] +connect_bd_net -net axi_ethernet_clkgen_125m_clk [get_bd_pins axi_ethernet_clkgen/clk_out1] [get_bd_pins axi_ethernet/clk125m] +connect_bd_net -net axi_ethernet_clkgen_312m_clk [get_bd_pins axi_ethernet_clkgen/clk_out2] [get_bd_pins axi_ethernet/clk312] +connect_bd_net -net axi_ethernet_clkgen_625m_clk [get_bd_pins axi_ethernet_clkgen/clk_out3] [get_bd_pins axi_ethernet/clk625] +connect_bd_net -net axi_ethernet_clkgen_locked [get_bd_pins axi_ethernet_clkgen/locked] [get_bd_pins axi_ethernet/mmcm_locked] +connect_bd_net -net axi_ethernet_rstgen_rst [get_bd_pins axi_ethernet_rstgen/peripheral_reset] [get_bd_pins axi_ethernet/rst_125] +connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n] +connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n] +connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n] +connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n] +connect_bd_net -net axi_ethernet_clkgen_125m_clk [get_bd_pins axi_ethernet_rstgen/slowest_sync_clk] -connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] -connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] +# defaults (misc) + +connect_bd_intf_net -intf_net gpio_lcd [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio] +connect_bd_intf_net -intf_net gpio_sw [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] +connect_bd_intf_net -intf_net gpio_led [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] +connect_bd_intf_net -intf_net iic_main [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] +connect_bd_net -net uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx] +connect_bd_net -net uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx] +connect_bd_net -net iic_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] # hdmi diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc index cea4dd419..6379de397 100644 --- a/projects/common/kcu105/kcu105_system_constr.xdc +++ b/projects/common/kcu105/kcu105_system_constr.xdc @@ -7,137 +7,15 @@ set_false_path -through [get_ports sys_rst] # clocks -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN AK16 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports sys_clk_n] +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_n] create_clock -name sys_clk -period 3.33 [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports sys_125m_clk_p] -set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports sys_125m_clk_n] +set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports phy_clk_p] +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports phy_clk_n] -create_clock -name sys_clk -period 8.00 [get_ports sys_125m_clk_p] - -# ddr - -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD SSTL12} [get_ports ddr4_act_n] -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL12} [get_ports ddr4_addr[0]] -set_property -dict {PACKAGE_PIN AH17 IOSTANDARD SSTL12} [get_ports ddr4_addr[1]] -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD SSTL12} [get_ports ddr4_addr[2]] -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD SSTL12} [get_ports ddr4_addr[3]] -set_property -dict {PACKAGE_PIN AG16 IOSTANDARD SSTL12} [get_ports ddr4_addr[4]] -set_property -dict {PACKAGE_PIN AL17 IOSTANDARD SSTL12} [get_ports ddr4_addr[5]] -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD SSTL12} [get_ports ddr4_addr[6]] -set_property -dict {PACKAGE_PIN AG17 IOSTANDARD SSTL12} [get_ports ddr4_addr[7]] -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD SSTL12} [get_ports ddr4_addr[8]] -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD SSTL12} [get_ports ddr4_addr[9]] -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL12} [get_ports ddr4_addr[10]] -set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL12} [get_ports ddr4_addr[11]] -set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD SSTL12} [get_ports ddr4_addr[12]] -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD SSTL12} [get_ports ddr4_addr[13]] -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL12} [get_ports ddr4_addr[14]] -set_property -dict {PACKAGE_PIN AG14 IOSTANDARD SSTL12} [get_ports ddr4_addr[15]] -set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL12} [get_ports ddr4_addr[16]] -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL12} [get_ports ddr4_ba[0]] -set_property -dict {PACKAGE_PIN AL15 IOSTANDARD SSTL12} [get_ports ddr4_ba[1]] -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD SSTL12} [get_ports ddr4_bg] -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD DIFF_POD12} [get_ports ddr4_ck_p] -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD DIFF_POD12} [get_ports ddr4_ck_n] -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL12} [get_ports ddr4_cke] -set_property -dict {PACKAGE_PIN AL19 IOSTANDARD SSTL12} [get_ports ddr4_cs_n] -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD POD12} [get_ports ddr4_dm_n[0]] -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD POD12} [get_ports ddr4_dm_n[1]] -set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD POD12} [get_ports ddr4_dm_n[2]] -set_property -dict {PACKAGE_PIN AM21 IOSTANDARD POD12} [get_ports ddr4_dm_n[3]] -set_property -dict {PACKAGE_PIN AH26 IOSTANDARD POD12} [get_ports ddr4_dm_n[4]] -set_property -dict {PACKAGE_PIN AN26 IOSTANDARD POD12} [get_ports ddr4_dm_n[5]] -set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD POD12} [get_ports ddr4_dm_n[6]] -set_property -dict {PACKAGE_PIN AL32 IOSTANDARD POD12} [get_ports ddr4_dm_n[7]] - -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[0]] -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[1]] -set_property -dict {PACKAGE_PIN AF22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[2]] -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[3]] -set_property -dict {PACKAGE_PIN AE22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[4]] -set_property -dict {PACKAGE_PIN AD20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[5]] -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[6]] -set_property -dict {PACKAGE_PIN AE20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[7]] -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[8]] -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[9]] -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[10]] -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[11]] -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[12]] -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[13]] -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[14]] -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[15]] -set_property -dict {PACKAGE_PIN AL22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[16]] -set_property -dict {PACKAGE_PIN AL25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[17]] -set_property -dict {PACKAGE_PIN AM20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[18]] -set_property -dict {PACKAGE_PIN AK23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[19]] -set_property -dict {PACKAGE_PIN AK22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[20]] -set_property -dict {PACKAGE_PIN AL24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[21]] -set_property -dict {PACKAGE_PIN AL20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[22]] -set_property -dict {PACKAGE_PIN AL23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[23]] -set_property -dict {PACKAGE_PIN AM24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[24]] -set_property -dict {PACKAGE_PIN AN23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[25]] -set_property -dict {PACKAGE_PIN AN24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[26]] -set_property -dict {PACKAGE_PIN AP23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[27]] -set_property -dict {PACKAGE_PIN AP25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[28]] -set_property -dict {PACKAGE_PIN AN22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[29]] -set_property -dict {PACKAGE_PIN AP24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[30]] -set_property -dict {PACKAGE_PIN AM22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[31]] -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[32]] -set_property -dict {PACKAGE_PIN AK26 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[33]] -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[34]] -set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[35]] -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[36]] -set_property -dict {PACKAGE_PIN AH27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[37]] -set_property -dict {PACKAGE_PIN AK27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[38]] -set_property -dict {PACKAGE_PIN AM26 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[39]] -set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[40]] -set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[41]] -set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[42]] -set_property -dict {PACKAGE_PIN AN28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[43]] -set_property -dict {PACKAGE_PIN AL29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[44]] -set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[45]] -set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[46]] -set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[47]] -set_property -dict {PACKAGE_PIN AH31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[48]] -set_property -dict {PACKAGE_PIN AH32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[49]] -set_property -dict {PACKAGE_PIN AJ34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[50]] -set_property -dict {PACKAGE_PIN AK31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[51]] -set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[52]] -set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[53]] -set_property -dict {PACKAGE_PIN AH34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[54]] -set_property -dict {PACKAGE_PIN AK32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[55]] -set_property -dict {PACKAGE_PIN AN33 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[56]] -set_property -dict {PACKAGE_PIN AP33 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[57]] -set_property -dict {PACKAGE_PIN AM34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[58]] -set_property -dict {PACKAGE_PIN AP31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[59]] -set_property -dict {PACKAGE_PIN AM32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[60]] -set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[61]] -set_property -dict {PACKAGE_PIN AL34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[62]] -set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[63]] - -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[0]] -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[0]] -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[1]] -set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[1]] -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[2]] -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[2]] -set_property -dict {PACKAGE_PIN AP20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[3]] -set_property -dict {PACKAGE_PIN AP21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[3]] -set_property -dict {PACKAGE_PIN AL27 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[4]] -set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[4]] -set_property -dict {PACKAGE_PIN AN29 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[5]] -set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[5]] -set_property -dict {PACKAGE_PIN AH33 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[6]] -set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[6]] -set_property -dict {PACKAGE_PIN AN34 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[7]] -set_property -dict {PACKAGE_PIN AP34 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[7]] - -set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD SSTL12} [get_ports ddr4_odt] -set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL12} [get_ports ddr4_par] -set_property -dict {PACKAGE_PIN AL18 IOSTANDARD LVCMOS12} [get_ports ddr4_reset_n] +create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p] # ethernet @@ -214,14 +92,14 @@ set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports spdif] # clocks -create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout1] #create_clock -name mem_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/c0_ddr4_ui_clk] +create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout1] create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout2] create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0] create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1] -set_clock_groups -asynchronous -group {cpu_clk} #set_clock_groups -asynchronous -group {mem_clk} +set_clock_groups -asynchronous -group {cpu_clk} set_clock_groups -asynchronous -group {m200_clk} set_clock_groups -asynchronous -group {hdmi_clk} set_clock_groups -asynchronous -group {spdif_clk} diff --git a/projects/common/kcu105/kcu105_system_mig.tcl b/projects/common/kcu105/kcu105_system_mig.tcl index b30084030..c3128e3c6 100644 --- a/projects/common/kcu105/kcu105_system_mig.tcl +++ b/projects/common/kcu105/kcu105_system_mig.tcl @@ -1,152 +1,144 @@ # ddr controller -set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3333}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_MemoryPart {MT40A256M16HA-083}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_MemoryVoltage {1.2V}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.Internal_Vref {true}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_BANK_COLUMN}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.Debug_Signal {Enable}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3333}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_MemoryPart {MT40A256M16HA-083}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_AxiSelection {true}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_BANK_COLUMN}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] $axi_ddr_cntrl +set_property -dict [list CONFIG.Debug_Signal {Enable}] $axi_ddr_cntrl -set_property -dict [list CONFIG.C0.DDR4_AxiDataWidth {512}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.C0.DDR4_AxiNarrowBurst {true}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl +set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl -set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_adr_0 {bank45.byte3.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_1 {bank45.byte2.pin1}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_2 {bank45.byte3.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_3 {bank45.byte2.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_4 {bank45.byte2.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_5 {bank45.byte1.pin7}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_6 {bank45.byte1.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_7 {bank45.byte2.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_8 {bank45.byte3.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_9 {bank45.byte2.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_10 {bank45.byte3.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_11 {bank45.byte3.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_12 {bank45.byte2.pin7}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_13 {bank45.byte2.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_14 {bank45.byte3.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_15 {bank45.byte2.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_adr_16 {bank45.byte3.pin3}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_adr_0 {bank45.byte3.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_1 {bank45.byte2.pin1}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_2 {bank45.byte3.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_3 {bank45.byte2.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_4 {bank45.byte2.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_5 {bank45.byte1.pin7}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_6 {bank45.byte1.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_7 {bank45.byte2.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_8 {bank45.byte3.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_9 {bank45.byte2.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_10 {bank45.byte3.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_11 {bank45.byte3.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_12 {bank45.byte2.pin7}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_13 {bank45.byte2.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_14 {bank45.byte3.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_15 {bank45.byte2.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_adr_16 {bank45.byte3.pin3}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_0 {bank44.byte0.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_1 {bank44.byte0.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_2 {bank44.byte0.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_3 {bank44.byte0.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_4 {bank44.byte0.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_5 {bank44.byte0.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_6 {bank44.byte0.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_7 {bank44.byte0.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_0 {bank44.byte0.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_0 {bank44.byte0.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_0 {bank44.byte0.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_0 {bank44.byte0.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_1 {bank44.byte0.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_2 {bank44.byte0.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_3 {bank44.byte0.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_4 {bank44.byte0.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_5 {bank44.byte0.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_6 {bank44.byte0.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_7 {bank44.byte0.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_0 {bank44.byte0.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_0 {bank44.byte0.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_0 {bank44.byte0.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_8 {bank44.byte1.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_9 {bank44.byte1.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_10 {bank44.byte1.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_11 {bank44.byte1.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_12 {bank44.byte1.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_13 {bank44.byte1.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_14 {bank44.byte1.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_15 {bank44.byte1.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_1 {bank44.byte1.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_1 {bank44.byte1.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_1 {bank44.byte1.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_8 {bank44.byte1.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_9 {bank44.byte1.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_10 {bank44.byte1.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_11 {bank44.byte1.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_12 {bank44.byte1.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_13 {bank44.byte1.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_14 {bank44.byte1.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_15 {bank44.byte1.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_1 {bank44.byte1.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_1 {bank44.byte1.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_1 {bank44.byte1.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_16 {bank44.byte2.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_17 {bank44.byte2.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_18 {bank44.byte2.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_19 {bank44.byte2.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_20 {bank44.byte2.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_21 {bank44.byte2.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_22 {bank44.byte2.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_23 {bank44.byte2.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_2 {bank44.byte2.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_2 {bank44.byte2.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_2 {bank44.byte2.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_16 {bank44.byte2.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_17 {bank44.byte2.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_18 {bank44.byte2.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_19 {bank44.byte2.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_20 {bank44.byte2.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_21 {bank44.byte2.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_22 {bank44.byte2.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_23 {bank44.byte2.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_2 {bank44.byte2.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_2 {bank44.byte2.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_2 {bank44.byte2.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_24 {bank44.byte3.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_25 {bank44.byte3.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_26 {bank44.byte3.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_27 {bank44.byte3.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_28 {bank44.byte3.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_29 {bank44.byte3.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_30 {bank44.byte3.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_31 {bank44.byte3.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_3 {bank44.byte3.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_3 {bank44.byte3.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_3 {bank44.byte3.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_24 {bank44.byte3.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_25 {bank44.byte3.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_26 {bank44.byte3.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_27 {bank44.byte3.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_28 {bank44.byte3.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_29 {bank44.byte3.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_30 {bank44.byte3.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_31 {bank44.byte3.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_3 {bank44.byte3.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_3 {bank44.byte3.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_3 {bank44.byte3.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_32 {bank46.byte0.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_33 {bank46.byte0.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_34 {bank46.byte0.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_35 {bank46.byte0.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_36 {bank46.byte0.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_37 {bank46.byte0.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_38 {bank46.byte0.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_39 {bank46.byte0.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_4 {bank46.byte0.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_4 {bank46.byte0.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_4 {bank46.byte0.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_32 {bank46.byte0.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_33 {bank46.byte0.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_34 {bank46.byte0.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_35 {bank46.byte0.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_36 {bank46.byte0.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_37 {bank46.byte0.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_38 {bank46.byte0.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_39 {bank46.byte0.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_4 {bank46.byte0.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_4 {bank46.byte0.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_4 {bank46.byte0.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_40 {bank46.byte1.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_41 {bank46.byte1.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_42 {bank46.byte1.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_43 {bank46.byte1.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_44 {bank46.byte1.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_45 {bank46.byte1.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_46 {bank46.byte1.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_47 {bank46.byte1.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_5 {bank46.byte1.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_5 {bank46.byte1.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_5 {bank46.byte1.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_40 {bank46.byte1.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_41 {bank46.byte1.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_42 {bank46.byte1.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_43 {bank46.byte1.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_44 {bank46.byte1.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_45 {bank46.byte1.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_46 {bank46.byte1.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_47 {bank46.byte1.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_5 {bank46.byte1.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_5 {bank46.byte1.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_5 {bank46.byte1.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_48 {bank46.byte2.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_49 {bank46.byte2.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_50 {bank46.byte2.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_51 {bank46.byte2.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_52 {bank46.byte2.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_53 {bank46.byte2.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_54 {bank46.byte2.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_55 {bank46.byte2.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_6 {bank46.byte2.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_6 {bank46.byte2.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_6 {bank46.byte2.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_48 {bank46.byte2.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_49 {bank46.byte2.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_50 {bank46.byte2.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_51 {bank46.byte2.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_52 {bank46.byte2.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_53 {bank46.byte2.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_54 {bank46.byte2.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_55 {bank46.byte2.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_6 {bank46.byte2.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_6 {bank46.byte2.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_6 {bank46.byte2.pin7}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_dq_56 {bank46.byte3.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_57 {bank46.byte3.pin3}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_58 {bank46.byte3.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_59 {bank46.byte3.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_60 {bank46.byte3.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_61 {bank46.byte3.pin4}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_62 {bank46.byte3.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dq_63 {bank46.byte3.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dm_dbi_n_7 {bank46.byte3.pin0}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_t_7 {bank46.byte3.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_dqs_c_7 {bank46.byte3.pin7}] $axi_ddr_cntrl -set_property -dict [list CONFIG.c0_dq_56 {bank46.byte3.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_57 {bank46.byte3.pin3}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_58 {bank46.byte3.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_59 {bank46.byte3.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_60 {bank46.byte3.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_61 {bank46.byte3.pin4}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_62 {bank46.byte3.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dq_63 {bank46.byte3.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dm_dbi_n_7 {bank46.byte3.pin0}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_t_7 {bank46.byte3.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_dqs_c_7 {bank46.byte3.pin7}] [get_bd_cells axi_ddr_cntrl] - -set_property -dict [list CONFIG.c0_ba_0 {bank45.byte3.pin9}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_ba_1 {bank45.byte1.pin5}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_bg_0 {bank45.byte2.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_cke_0 {bank45.byte3.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_cs_n_0 {bank45.byte1.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_odt_0 {bank45.byte1.pin8}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_par {bank45.byte3.pin1}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_reset_n {bank45.byte1.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_act_n {bank45.byte2.pin12}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_ck_t {bank45.byte3.pin6}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_ck_c {bank45.byte3.pin7}] [get_bd_cells axi_ddr_cntrl] - -set_property -dict [list CONFIG.c0_sys_clk_p {bank45.byte1.pin10}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_sys_clk_n {bank45.byte1.pin11}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.sys_rst {bank64.byte2.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_data_compare_error {bank65.byte3.pin2}] [get_bd_cells axi_ddr_cntrl] -set_property -dict [list CONFIG.c0_init_calib_complete {bank65.byte3.pin3}] [get_bd_cells axi_ddr_cntrl] +set_property -dict [list CONFIG.c0_ba_0 {bank45.byte3.pin9}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_ba_1 {bank45.byte1.pin5}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_bg_0 {bank45.byte2.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_cke_0 {bank45.byte3.pin11}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_cs_n_0 {bank45.byte1.pin2}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_odt_0 {bank45.byte1.pin8}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_par {bank45.byte3.pin1}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_reset_n {bank45.byte1.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_act_n {bank45.byte2.pin12}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_ck_t {bank45.byte3.pin6}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_ck_c {bank45.byte3.pin7}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_sys_clk_p {bank45.byte1.pin10}] $axi_ddr_cntrl +set_property -dict [list CONFIG.c0_sys_clk_n {bank45.byte1.pin11}] $axi_ddr_cntrl diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v index 7640b2107..d6855ea75 100644 --- a/projects/daq2/kcu105/system_top.v +++ b/projects/daq2/kcu105/system_top.v @@ -44,8 +44,6 @@ module system_top ( sys_rst, sys_clk_p, sys_clk_n, - sys_125m_clk_p, - sys_125m_clk_n, uart_sin, uart_sout, @@ -68,6 +66,8 @@ module system_top ( mdio_mdc, mdio_mdio, + phy_clk_p, + phy_clk_n, phy_rst_n, phy_rx_p, phy_rx_n, @@ -130,8 +130,6 @@ module system_top ( input sys_rst; input sys_clk_p; input sys_clk_n; - input sys_125m_clk_p; - input sys_125m_clk_n; input uart_sin; output uart_sout; @@ -154,6 +152,8 @@ module system_top ( output mdio_mdc; inout mdio_mdio; + input phy_clk_p; + input phy_clk_n; output phy_rst_n; input phy_rx_p; input phy_rx_n; @@ -486,6 +486,16 @@ module system_top ( .IO (clkd_status[0])); system_wrapper i_system_wrapper ( + .adc_clk (adc_clk), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_ddata (adc_ddata), + .adc_dsync (adc_dsync), + .adc_dwr (adc_dwr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), .c0_ddr4_act_n (ddr4_act_n), .c0_ddr4_adr (ddr4_addr), .c0_ddr4_ba (ddr4_ba), @@ -501,25 +511,6 @@ module system_top ( .c0_ddr4_odt (ddr4_odt), .c0_ddr4_par (ddr4_par), .c0_ddr4_reset_n (ddr4_reset_n), - .gpio_ctl_i (gpio_ctl_i), - .gpio_ctl_o (gpio_ctl_o), - .gpio_ctl_t (gpio_ctl_t), - .gpio_lcd_tri_io (), - .gpio_led_tri_io (gpio_led), - .gpio_status_i (gpio_status_i), - .gpio_status_o (gpio_status_o), - .gpio_status_t (gpio_status_t), - .gpio_sw_tri_io (gpio_sw), - .adc_clk (adc_clk), - .adc_data_0 (adc_data_0), - .adc_data_1 (adc_data_1), - .adc_ddata (adc_ddata), - .adc_dsync (adc_dsync), - .adc_dwr (adc_dwr), - .adc_enable_0 (adc_enable_0), - .adc_enable_1 (adc_enable_1), - .adc_valid_0 (adc_valid_0), - .adc_valid_1 (adc_valid_1), .dac_clk (dac_clk), .dac_ddata (dac_ddata), .dac_ddata_0 (dac_ddata_0), @@ -535,6 +526,15 @@ module system_top ( .dac_valid_1 (dac_valid_1), .dac_valid_2 (dac_valid_2), .dac_valid_3 (dac_valid_3), + .gpio_ctl_i (gpio_ctl_i), + .gpio_ctl_o (gpio_ctl_o), + .gpio_ctl_t (gpio_ctl_t), + .gpio_lcd_tri_io (), + .gpio_led_tri_io (gpio_led), + .gpio_status_i (gpio_status_i), + .gpio_status_o (gpio_status_o), + .gpio_status_t (gpio_status_t), + .gpio_sw_tri_io (gpio_sw), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -545,20 +545,20 @@ module system_top ( .iic_rstn (iic_rstn), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), + .phy_clk_clk_n (phy_clk_n), + .phy_clk_clk_p (phy_clk_p), .phy_rst_n (phy_rst_n), .phy_sd (1'b1), - .sgmii_rxn (phy_rx_n), - .sgmii_rxp (phy_rx_p), - .sgmii_txn (phy_tx_n), - .sgmii_txp (phy_tx_p), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), .rx_sync (rx_sync), .rx_sysref (rx_sysref), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), .spdif (spdif), - .sys_125m_clk_n (sys_125m_clk_n), - .sys_125m_clk_p (sys_125m_clk_p), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), .spi_csn_i (spi_csn), @@ -566,8 +566,8 @@ module system_top ( .spi_sdi_i (spi_miso), .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), .sys_rst (sys_rst), .tx_data_n (tx_data_n), .tx_data_p (tx_data_p),