From 6655829bc78183ab76c3be13fa39087d2b61e5e1 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 22 Jul 2019 13:25:46 +0100 Subject: [PATCH] daq2: VC707: Remove project --- projects/daq2/vc707/Makefile | 32 --- projects/daq2/vc707/system_bd.tcl | 14 -- projects/daq2/vc707/system_constr.xdc | 61 ----- projects/daq2/vc707/system_project.tcl | 16 -- projects/daq2/vc707/system_top.v | 309 ------------------------- 5 files changed, 432 deletions(-) delete mode 100644 projects/daq2/vc707/Makefile delete mode 100644 projects/daq2/vc707/system_bd.tcl delete mode 100644 projects/daq2/vc707/system_constr.xdc delete mode 100644 projects/daq2/vc707/system_project.tcl delete mode 100644 projects/daq2/vc707/system_top.v diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile deleted file mode 100644 index b6db19764..000000000 --- a/projects/daq2/vc707/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := daq2_vc707 - -M_DEPS += ../common/daq2_spi.v -M_DEPS += ../common/daq2_bd.tcl -M_DEPS += ../../common/xilinx/dacfifo_bd.tcl -M_DEPS += ../../common/xilinx/adcfifo_bd.tcl -M_DEPS += ../../common/vc707/vc707_system_mig.prj -M_DEPS += ../../common/vc707/vc707_system_constr.xdc -M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v -M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl - -LIB_DEPS += axi_ad9144 -LIB_DEPS += axi_ad9680 -LIB_DEPS += axi_dmac -LIB_DEPS += jesd204/axi_jesd204_rx -LIB_DEPS += jesd204/axi_jesd204_tx -LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += jesd204/jesd204_tx -LIB_DEPS += util_adcfifo -LIB_DEPS += util_dacfifo -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 -LIB_DEPS += xilinx/axi_adxcvr -LIB_DEPS += xilinx/util_adxcvr - -include ../../scripts/project-xilinx.mk diff --git a/projects/daq2/vc707/system_bd.tcl b/projects/daq2/vc707/system_bd.tcl deleted file mode 100644 index aa23dab6b..000000000 --- a/projects/daq2/vc707/system_bd.tcl +++ /dev/null @@ -1,14 +0,0 @@ - -## FIFO depth is 8Mb - 500k samples -set adc_fifo_address_width 17 - -## FIFO depth is 8Mb - 500k samples -set dac_fifo_address_width 16 - -## NOTE: With this configuration the #36Kb BRAM utilization is at ~68.45% - -source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl -source ../common/daq2_bd.tcl - diff --git a/projects/daq2/vc707/system_constr.xdc b/projects/daq2/vc707/system_constr.xdc deleted file mode 100644 index c667046e4..000000000 --- a/projects/daq2/vc707/system_constr.xdc +++ /dev/null @@ -1,61 +0,0 @@ - -# daq2 - -set_property -dict {PACKAGE_PIN E10} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_property -dict {PACKAGE_PIN E9 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N - -set_property -dict {PACKAGE_PIN A10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN A9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN B4} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) -set_property -dict {PACKAGE_PIN B3} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) -set_property -dict {PACKAGE_PIN E2} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) -set_property -dict {PACKAGE_PIN E1} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) -set_property -dict {PACKAGE_PIN C2} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) -set_property -dict {PACKAGE_PIN C1} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) -set_property -dict {PACKAGE_PIN D4} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) -set_property -dict {PACKAGE_PIN D3} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) -set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N - -set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P -set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N - -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVCMOS18} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P - -set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N - -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N - -# clocks - -create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] -create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] - diff --git a/projects/daq2/vc707/system_project.tcl b/projects/daq2/vc707/system_project.tcl deleted file mode 100644 index d9c0c8028..000000000 --- a/projects/daq2/vc707/system_project.tcl +++ /dev/null @@ -1,16 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project daq2_vc707 -adi_project_files daq2_vc707 [list \ - "../common/daq2_spi.v" \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] - -adi_project_run daq2_vc707 - - diff --git a/projects/daq2/vc707/system_top.v b/projects/daq2/vc707/system_top.v deleted file mode 100644 index adf8accaa..000000000 --- a/projects/daq2/vc707/system_top.v +++ /dev/null @@ -1,309 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output ddr3_reset_n, - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output ddr3_ras_n, - output ddr3_we_n, - output [ 0:0] ddr3_ck_n, - output [ 0:0] ddr3_ck_p, - output [ 0:0] ddr3_cke, - output [ 0:0] ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output [ 0:0] ddr3_odt, - - input sgmii_rxp, - input sgmii_rxn, - output sgmii_txp, - output sgmii_txn, - - output phy_rstn, - input mgt_clk_p, - input mgt_clk_n, - output mdio_mdc, - inout mdio_mdio, - - output [26:1] linear_flash_addr, - output linear_flash_adv_ldn, - output linear_flash_ce_n, - inout [15:0] linear_flash_dq_io, - output linear_flash_oen, - output linear_flash_wen, - - output fan_pwm, - - inout [ 6:0] gpio_lcd, - inout [20:0] gpio_bd, - - output iic_rstn, - inout iic_scl, - inout iic_sda, - - input rx_ref_clk_p, - input rx_ref_clk_n, - input rx_sysref_p, - input rx_sysref_n, - output rx_sync_p, - output rx_sync_n, - input [ 3:0] rx_data_p, - input [ 3:0] rx_data_n, - - input tx_ref_clk_p, - input tx_ref_clk_n, - input tx_sysref_p, - input tx_sysref_n, - input tx_sync_p, - input tx_sync_n, - output [ 3:0] tx_data_p, - output [ 3:0] tx_data_n, - - input trig_p, - input trig_n, - - inout adc_fdb, - inout adc_fda, - inout dac_irq, - inout [ 1:0] clkd_status, - - inout adc_pd, - inout dac_txen, - inout dac_reset, - inout clkd_sync, - - output spi_csn_clk, - output spi_csn_dac, - output spi_csn_adc, - output spi_clk, - inout spi_sdio, - output spi_dir); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 7:0] spi_csn; - wire spi_mosi; - wire spi_miso; - wire trig; - wire rx_ref_clk; - wire rx_sysref; - wire rx_sync; - wire tx_ref_clk; - wire tx_sysref; - wire tx_sync; - - // spi - - assign spi_csn_adc = spi_csn[2]; - assign spi_csn_dac = spi_csn[1]; - assign spi_csn_clk = spi_csn[0]; - - // default logic - - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - // instantiations - - IBUFDS_GTE2 i_ibufds_rx_ref_clk ( - .CEB (1'd0), - .I (rx_ref_clk_p), - .IB (rx_ref_clk_n), - .O (rx_ref_clk), - .ODIV2 ()); - - IBUFDS i_ibufds_rx_sysref ( - .I (rx_sysref_p), - .IB (rx_sysref_n), - .O (rx_sysref)); - - OBUFDS i_obufds_rx_sync ( - .I (rx_sync), - .O (rx_sync_p), - .OB (rx_sync_n)); - - IBUFDS_GTE2 i_ibufds_tx_ref_clk ( - .CEB (1'd0), - .I (tx_ref_clk_p), - .IB (tx_ref_clk_n), - .O (tx_ref_clk), - .ODIV2 ()); - - IBUFDS i_ibufds_tx_sysref ( - .I (tx_sysref_p), - .IB (tx_sysref_n), - .O (tx_sysref)); - - IBUFDS i_ibufds_tx_sync ( - .I (tx_sync_p), - .IB (tx_sync_n), - .O (tx_sync)); - - daq2_spi i_spi ( - .spi_csn (spi_csn[2:0]), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_sdio (spi_sdio), - .spi_dir (spi_dir)); - - IBUFDS i_ibufds_trig ( - .I (trig_p), - .IB (trig_n), - .O (trig)); - - assign gpio_i[43] = trig; - - ad_iobuf #(.DATA_WIDTH(9)) i_iobuf ( - .dio_t ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}), - .dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}), - .dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}), - .dio_p ({ adc_pd, // 42 - dac_txen, // 41 - dac_reset, // 40 - clkd_sync, // 38 - adc_fdb, // 36 - adc_fda, // 35 - dac_irq, // 34 - clkd_status})); // 33-32 - - ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( - .dio_t (gpio_t[20:0]), - .dio_i (gpio_o[20:0]), - .dio_o (gpio_i[20:0]), - .dio_p (gpio_bd)); - - assign gpio_i[63:44] = gpio_o[63:44]; - assign gpio_i[39] = gpio_o[39]; - assign gpio_i[37] = gpio_o[37]; - assign gpio_i[31:21] = gpio_o[31:21]; - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .gpio0_i (gpio_i[31:0]), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio1_i (gpio_i[63:32]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio_lcd_tri_io (gpio_lcd), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .linear_flash_addr (linear_flash_addr), - .linear_flash_adv_ldn (linear_flash_adv_ldn), - .linear_flash_ce_n (linear_flash_ce_n), - .linear_flash_dq_io (linear_flash_dq_io), - .linear_flash_oen (linear_flash_oen), - .linear_flash_wen (linear_flash_wen), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .mgt_clk_clk_n (mgt_clk_n), - .mgt_clk_clk_p (mgt_clk_p), - .phy_rstn (phy_rstn), - .phy_sd (1'b1), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), - .rx_data_2_n (rx_data_n[2]), - .rx_data_2_p (rx_data_p[2]), - .rx_data_3_n (rx_data_n[3]), - .rx_data_3_p (rx_data_p[3]), - .rx_ref_clk_0 (rx_ref_clk), - .rx_sync_0 (rx_sync), - .rx_sysref_0 (rx_sysref), - .sgmii_rxn (sgmii_rxn), - .sgmii_rxp (sgmii_rxp), - .sgmii_txn (sgmii_txn), - .sgmii_txp (sgmii_txp), - .spi_clk_i (spi_clk), - .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .tx_data_0_n (tx_data_n[0]), - .tx_data_0_p (tx_data_p[0]), - .tx_data_1_n (tx_data_n[1]), - .tx_data_1_p (tx_data_p[1]), - .tx_data_2_n (tx_data_n[2]), - .tx_data_2_p (tx_data_p[2]), - .tx_data_3_n (tx_data_n[3]), - .tx_data_3_p (tx_data_p[3]), - .tx_ref_clk_0 (tx_ref_clk), - .tx_sync_0 (tx_sync), - .tx_sysref_0 (tx_sysref), - .uart_sin (uart_sin), - .uart_sout (uart_sout)); - -endmodule - -// *************************************************************************** -// ***************************************************************************