diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v
index 2560fa22d..eabe5564e 100644
--- a/library/axi_clkgen/axi_clkgen.v
+++ b/library/axi_clkgen/axi_clkgen.v
@@ -110,6 +110,7 @@ module axi_clkgen (
   // reset and clocks
 
   wire            mmcm_rst;
+  wire            clk_sel;
   wire            up_rstn;
   wire            up_clk;
 
@@ -171,6 +172,7 @@ module axi_clkgen (
 
   up_clkgen i_up_clkgen (
     .mmcm_rst (mmcm_rst),
+    .clk_sel (clk_sel),
     .up_drp_sel (up_drp_sel_s),
     .up_drp_wr (up_drp_wr_s),
     .up_drp_addr (up_drp_addr_s),
@@ -203,6 +205,7 @@ module axi_clkgen (
     .clk (clk),
     .clk2 (clk2),
     .mmcm_rst (mmcm_rst),
+    .clk_sel(clk_sel),
     .mmcm_clk_0 (clk_0),
     .mmcm_clk_1 (clk_1),
     .up_clk (up_clk),
diff --git a/library/common/ad_mmcm_drp.v b/library/common/ad_mmcm_drp.v
index 7fe847479..e423ad03b 100644
--- a/library/common/ad_mmcm_drp.v
+++ b/library/common/ad_mmcm_drp.v
@@ -45,6 +45,7 @@ module ad_mmcm_drp (
   clk,
   clk2,
   mmcm_rst,
+  clk_sel,
   mmcm_clk_0,
   mmcm_clk_1,
 
@@ -78,6 +79,7 @@ module ad_mmcm_drp (
   input           clk;
   input           clk2;
   input           mmcm_rst;
+  input           clk_sel;
   output          mmcm_clk_0;
   output          mmcm_clk_1;
 
@@ -176,7 +178,7 @@ module ad_mmcm_drp (
     .CLKOUT5 (),
     .CLKOUT6 (),
     .CLKIN2 (clk2),
-    .CLKINSEL (1'b1),
+    .CLKINSEL (clk_sel),
     .PSCLK (1'b0),
     .PSEN (1'b0),
     .PSINCDEC (1'b0),
@@ -233,7 +235,7 @@ module ad_mmcm_drp (
     .CLKOUT5 (),
     .CLKOUT6 (),
     .CLKIN2 (clk2),
-    .CLKINSEL (1'b1),
+    .CLKINSEL (clk_sel),
     .PSCLK (1'b0),
     .PSEN (1'b0),
     .PSINCDEC (1'b0),
diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v
index 2c6d47175..5cd6619b7 100644
--- a/library/common/up_clkgen.v
+++ b/library/common/up_clkgen.v
@@ -43,6 +43,10 @@ module up_clkgen (
 
   mmcm_rst,
 
+  // clock selection
+
+  clk_sel,
+
   // drp interface
 
   up_drp_sel,
@@ -75,6 +79,10 @@ module up_clkgen (
 
   output          mmcm_rst;
 
+  // clock selection
+
+  output clk_sel;
+
   // drp interface
 
   output          up_drp_sel;
@@ -115,6 +123,7 @@ module up_clkgen (
   reg     [15:0]  up_drp_rdata_hold = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
+  reg             up_clk_sel = 'd0;
 
   // internal signals
 
@@ -126,6 +135,8 @@ module up_clkgen (
   assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
   assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
 
+  assign clk_sel = ~up_clk_sel;
+
   // processor write interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -142,6 +153,7 @@ module up_clkgen (
       up_drp_addr <= 'd0;
       up_drp_wdata <= 'd0;
       up_drp_rdata_hold <= 'd0;
+      up_clk_sel <= 'd0;
     end else begin
       up_mmcm_preset <= ~up_mmcm_resetn;
       up_wack <= up_wreq_s;
@@ -152,6 +164,9 @@ module up_clkgen (
         up_mmcm_resetn <= up_wdata[1];
         up_resetn <= up_wdata[0];
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
+        up_clk_sel <= up_wdata[0];
+      end
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
         up_drp_sel <= 1'b1;
         up_drp_wr <= ~up_wdata[28];
@@ -189,6 +204,7 @@ module up_clkgen (
           8'h01: up_rdata <= ID;
           8'h02: up_rdata <= up_scratch;
           8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
+          8'h11: up_rdata <= {31'd0, up_clk_sel};
           8'h17: up_rdata <= {31'd0, up_drp_locked};
           8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
           8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};