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library: Axi_clkgen, added register for controlling the source clock. 

Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
main
Adrian Costina 2015-11-25 11:16:32 +02:00
parent ea57b3c03c
commit 667e49fe41
3 changed files with 23 additions and 2 deletions
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3
library/axi_clkgen/axi_clkgen.v
View File

@ -110,6 +110,7 @@ module axi_clkgen (
// reset and clocks
wire mmcm_rst;
wire clk_sel;
wire up_rstn;
wire up_clk;
@ -171,6 +172,7 @@ module axi_clkgen (
up_clkgen i_up_clkgen (
.mmcm_rst (mmcm_rst),
.clk_sel (clk_sel),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
@ -203,6 +205,7 @@ module axi_clkgen (
.clk (clk),
.clk2 (clk2),
.mmcm_rst (mmcm_rst),
.clk_sel(clk_sel),
.mmcm_clk_0 (clk_0),
.mmcm_clk_1 (clk_1),
.up_clk (up_clk),

6
library/common/ad_mmcm_drp.v
View File

@ -45,6 +45,7 @@ module ad_mmcm_drp (
clk,
clk2,
mmcm_rst,
clk_sel,
mmcm_clk_0,
mmcm_clk_1,
@ -78,6 +79,7 @@ module ad_mmcm_drp (
input clk;
input clk2;
input mmcm_rst;
input clk_sel;
output mmcm_clk_0;
output mmcm_clk_1;
@ -176,7 +178,7 @@ module ad_mmcm_drp (
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (1'b1),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
@ -233,7 +235,7 @@ module ad_mmcm_drp (
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (1'b1),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),

16
library/common/up_clkgen.v
View File

@ -43,6 +43,10 @@ module up_clkgen (
mmcm_rst,
// clock selection
clk_sel,
// drp interface
up_drp_sel,
@ -75,6 +79,10 @@ module up_clkgen (
output mmcm_rst;
// clock selection
output clk_sel;
// drp interface
output up_drp_sel;
@ -115,6 +123,7 @@ module up_clkgen (
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_clk_sel = 'd0;
// internal signals
@ -126,6 +135,8 @@ module up_clkgen (
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign clk_sel = ~up_clk_sel;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
@ -142,6 +153,7 @@ module up_clkgen (
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_clk_sel <= 'd0;
end else begin
up_mmcm_preset <= ~up_mmcm_resetn;
up_wack <= up_wreq_s;
@ -152,6 +164,9 @@ module up_clkgen (
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_clk_sel <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
@ -189,6 +204,7 @@ module up_clkgen (
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {31'd0, up_clk_sel};
8'h17: up_rdata <= {31'd0, up_drp_locked};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};