Add FPGA info parameters flow

Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
main
AndreiGrozav 2019-01-11 10:54:16 +02:00 committed by AndreiGrozav
parent dffbbfd7d1
commit 66823682b6
136 changed files with 1416 additions and 248 deletions

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@ -40,6 +40,12 @@ module axi_adxcvr #(
// parameters // parameters
parameter integer ID = 0, parameter integer ID = 0,
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0,
parameter [15:0] FPGA_VOLTAGE = 0,
parameter integer XCVR_TYPE = 0,
parameter integer TX_OR_RX_N = 0, parameter integer TX_OR_RX_N = 0,
parameter integer NUM_OF_LANES = 4) ( parameter integer NUM_OF_LANES = 4) (
@ -93,6 +99,12 @@ module axi_adxcvr #(
axi_adxcvr_up #( axi_adxcvr_up #(
.ID (ID), .ID (ID),
.XCVR_TYPE (XCVR_TYPE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.FPGA_VOLTAGE (FPGA_VOLTAGE),
.TX_OR_RX_N (TX_OR_RX_N), .TX_OR_RX_N (TX_OR_RX_N),
.NUM_OF_LANES (NUM_OF_LANES)) .NUM_OF_LANES (NUM_OF_LANES))
i_up ( i_up (

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@ -1,5 +1,6 @@
package require qsys package require qsys
package require quartus::device
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
@ -10,6 +11,7 @@ set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_adxcvr set_module_property DISPLAY_NAME axi_adxcvr
set_module_property ELABORATION_CALLBACK p_axi_adxcvr set_module_property ELABORATION_CALLBACK p_axi_adxcvr
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -39,6 +41,15 @@ set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true set_parameter_property NUM_OF_LANES HDL_PARAMETER true
adi_add_auto_fpga_spec_params
adi_add_device_spec_param XCVR_TYPE
adi_add_device_spec_param FPGA_VOLTAGE
set_parameter_property FPGA_VOLTAGE DISPLAY_UNITS mV
set_parameter_property FPGA_VOLTAGE_MANUAL DISPLAY_UNITS mV
adi_add_indep_spec_params_overwrite XCVR_TYPE
adi_add_indep_spec_params_overwrite FPGA_VOLTAGE
# axi4 slave interface # axi4 slave interface
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12

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@ -40,6 +40,12 @@ module axi_adxcvr_up #(
// parameters // parameters
parameter integer ID = 0, parameter integer ID = 0,
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0,
parameter [15:0] FPGA_VOLTAGE = 0,
parameter integer XCVR_TYPE = 0,
parameter integer TX_OR_RX_N = 0, parameter integer TX_OR_RX_N = 0,
parameter integer NUM_OF_LANES = 4) ( parameter integer NUM_OF_LANES = 4) (
@ -136,7 +142,8 @@ module axi_adxcvr_up #(
// Specific to Altera // Specific to Altera
assign up_rparam_s[31:24] = 8'd0; assign up_rparam_s[31:28] = 8'd0;
assign up_rparam_s[27:24] = XCVR_TYPE[3:0];
// Specific to Xilinx // Specific to Xilinx
@ -168,6 +175,7 @@ module axi_adxcvr_up #(
10'h005: up_rdata_d <= {31'd0, up_status_int}; 10'h005: up_rdata_d <= {31'd0, up_status_int};
10'h006: up_rdata_d <= up_status_32_s; 10'h006: up_rdata_d <= up_status_32_s;
10'h009: up_rdata_d <= up_rparam_s; 10'h009: up_rdata_d <= up_rparam_s;
10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV
default: up_rdata_d <= 32'd0; default: up_rdata_d <= 32'd0;
endcase endcase
end else begin end else begin

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@ -37,6 +37,10 @@
module axi_ad5766 #( module axi_ad5766 #(
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter ASYNC_SPI_CLK = 0, parameter ASYNC_SPI_CLK = 0,
parameter CMD_MEM_ADDRESS_WIDTH = 4, parameter CMD_MEM_ADDRESS_WIDTH = 4,
parameter SDO_MEM_ADDRESS_WIDTH = 4)( parameter SDO_MEM_ADDRESS_WIDTH = 4)(
@ -343,6 +347,10 @@ module axi_ad5766 #(
up_dac_common #( up_dac_common #(
.COMMON_ID (0), .COMMON_ID (0),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.CLK_EDGE_SEL (0), .CLK_EDGE_SEL (0),
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),

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@ -13,10 +13,13 @@ adi_ip_files axi_ad5766 [list \
"$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/util_pulse_gen.v" \ "$ad_hdl_dir/library/common/util_pulse_gen.v" \
"up_ad5766_sequencer.v" \ "up_ad5766_sequencer.v" \
"axi_ad5766.v" ] "axi_ad5766.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad5766 adi_ip_properties axi_ad5766
adi_ip_bd axi_ad5766 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_ip_add_core_dependencies { \ adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \ analog.com:user:util_cdc:1.0 \
} }
@ -54,5 +57,8 @@ adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
adi_add_bus_clock "dma_clk" "dma_fifo_tx" adi_add_bus_clock "dma_clk" "dma_fifo_tx"
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,7 +38,11 @@
module axi_ad6676 #( module axi_ad6676 #(
parameter ID = 0, parameter ID = 0,
parameter NUM_LANES = 2) ( parameter NUM_LANES = 2,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -88,6 +92,10 @@ module axi_ad6676 #(
ad_ip_jesd204_tpl_adc #( ad_ip_jesd204_tpl_adc #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES (NUM_LANES), .NUM_LANES (NUM_LANES),
.NUM_CHANNELS (2), .NUM_CHANNELS (2),
.SAMPLES_PER_FRAME (1), .SAMPLES_PER_FRAME (1),

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@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad6676 adi_ip_create axi_ad6676
adi_ip_files axi_ad6676 [list \ adi_ip_files axi_ad6676 [list \
"axi_ad6676.v" ] "axi_ad6676.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad6676 adi_ip_properties axi_ad6676
adi_ip_bd axi_ad6676 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_ip_add_core_dependencies { \ adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
} }
@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,7 +38,10 @@
module axi_ad9122 #( module axi_ad9122 #(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter SERDES_OR_DDR_N = 1, parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1, parameter MMCM_OR_BUFIO_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667, parameter MMCM_CLKIN_PERIOD = 1.667,
@ -154,7 +157,7 @@ module axi_ad9122 #(
// device interface // device interface
axi_ad9122_if #( axi_ad9122_if #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N), .SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N), .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
@ -206,6 +209,10 @@ module axi_ad9122 #(
axi_ad9122_core #( axi_ad9122_core #(
.ID(ID), .ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),

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@ -113,9 +113,9 @@ module axi_ad9122_channel #(
.CLK_RATIO (4)) .CLK_RATIO (4))
i_dds ( i_dds (
.clk (dac_clk), .clk (dac_clk),
.rst (dac_rst),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
.dac_valid (1'b1),
.tone_1_scale (dac_dds_scale_1_s), .tone_1_scale (dac_dds_scale_1_s),
.tone_2_scale (dac_dds_scale_2_s), .tone_2_scale (dac_dds_scale_2_s),
.tone_1_init_offset (dac_dds_init_1_s), .tone_1_init_offset (dac_dds_init_1_s),

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@ -38,6 +38,10 @@
module axi_ad9122_core #( module axi_ad9122_core #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
@ -210,6 +214,10 @@ module axi_ad9122_core #(
up_dac_common #( up_dac_common #(
.ID(ID), .ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.CLK_EDGE_SEL (0), .CLK_EDGE_SEL (0),
.COMMON_ID (6'h10), .COMMON_ID (6'h10),

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@ -1,9 +1,12 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
ad_ip_create axi_ad9122 {AXI AD9122 Interface} ad_ip_create axi_ad9122 {AXI AD9122 Interface}
set_module_property VALIDATION_CALLBACK info_param_validate
ad_ip_files axi_ad9122 [list \ ad_ip_files axi_ad9122 [list \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \ $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
@ -40,12 +43,14 @@ set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0 add_parameter FPGA_TECHNOLOGY INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY
set_parameter_property DEVICE_TYPE TYPE INTEGER set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None set_parameter_property FPGA_TECHNOLOGY UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave

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@ -39,7 +39,7 @@
module axi_ad9122_if #( module axi_ad9122_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter SERDES_OR_DDR_N = 1, parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1, parameter MMCM_OR_BUFIO_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667, parameter MMCM_CLKIN_PERIOD = 1.667,
@ -128,7 +128,7 @@ module axi_ad9122_if #(
// dac data output serdes(s) & buffers // dac data output serdes(s) & buffers
ad_serdes_out #( ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (16)) .DATA_WIDTH (16))
i_serdes_out_data ( i_serdes_out_data (
@ -151,7 +151,7 @@ module axi_ad9122_if #(
// dac frame output serdes & buffer // dac frame output serdes & buffer
ad_serdes_out #( ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1)) .DATA_WIDTH (1))
i_serdes_out_frame ( i_serdes_out_frame (
@ -174,7 +174,7 @@ module axi_ad9122_if #(
// dac clock output serdes & buffer // dac clock output serdes & buffer
ad_serdes_out #( ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1)) .DATA_WIDTH (1))
i_serdes_out_clk ( i_serdes_out_clk (
@ -199,7 +199,7 @@ module axi_ad9122_if #(
ad_serdes_clk #( ad_serdes_clk #(
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N), .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV), .MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL), .MMCM_VCO_MUL (MMCM_VCO_MUL),

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@ -30,10 +30,13 @@ adi_ip_files axi_ad9122 [list \
"axi_ad9122_core.v" \ "axi_ad9122_core.v" \
"axi_ad9122_if.v" \ "axi_ad9122_if.v" \
"axi_ad9122_constr.xdc" \ "axi_ad9122_constr.xdc" \
"axi_ad9122.v" ] "axi_ad9122.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9122 adi_ip_properties axi_ad9122
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
@ -43,5 +46,9 @@ ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::cur
ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,6 +38,10 @@
module axi_ad9144 #( module axi_ad9144 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter QUAD_OR_DUAL_N = 1, parameter QUAD_OR_DUAL_N = 1,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_DW = 20,
@ -130,6 +134,10 @@ module axi_ad9144 #(
ad_ip_jesd204_tpl_dac #( ad_ip_jesd204_tpl_dac #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES (NUM_CHANNELS * 2), .NUM_LANES (NUM_CHANNELS * 2),
.NUM_CHANNELS (NUM_CHANNELS), .NUM_CHANNELS (NUM_CHANNELS),
.CONVERTER_RESOLUTION (16), .CONVERTER_RESOLUTION (16),

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@ -1,6 +1,7 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -10,6 +11,7 @@ set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9144 set_module_property DISPLAY_NAME axi_ad9144
set_module_property ELABORATION_CALLBACK p_axi_ad9144 set_module_property ELABORATION_CALLBACK p_axi_ad9144
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -61,6 +63,8 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
set_parameter_property QUAD_OR_DUAL_N UNITS None set_parameter_property QUAD_OR_DUAL_N UNITS None
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12

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@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9144 adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \ adi_ip_files axi_ad9144 [list \
"axi_ad9144.v" ] "axi_ad9144.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9144 adi_ip_properties axi_ad9144
adi_ip_bd axi_ad9144 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_ip_add_core_dependencies { \ adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
} }
@ -25,5 +28,8 @@ set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,6 +38,10 @@
module axi_ad9152 #( module axi_ad9152 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
@ -90,6 +94,10 @@ module axi_ad9152 #(
ad_ip_jesd204_tpl_dac #( ad_ip_jesd204_tpl_dac #(
.ID(ID), .ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES(4), .NUM_LANES(4),
.NUM_CHANNELS(2), .NUM_CHANNELS(2),
.CONVERTER_RESOLUTION (16), .CONVERTER_RESOLUTION (16),

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@ -1,6 +1,8 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9152 Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9152 set_module_property DISPLAY_NAME axi_ad9152
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -53,6 +56,8 @@ set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true set_parameter_property ID HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12

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@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9152 adi_ip_create axi_ad9152
adi_ip_files axi_ad9152 [list \ adi_ip_files axi_ad9152 [list \
"axi_ad9152.v" ] "axi_ad9152.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9152 adi_ip_properties axi_ad9152
adi_ip_bd axi_ad9152 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_ip_add_core_dependencies { \ adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
} }
@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,6 +38,10 @@
module axi_ad9162 #( module axi_ad9162 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
@ -123,6 +127,10 @@ module axi_ad9162 #(
axi_ad9162_core #( axi_ad9162_core #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),

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@ -38,6 +38,10 @@
module axi_ad9162_core #( module axi_ad9162_core #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
@ -129,6 +133,10 @@ module axi_ad9162_core #(
up_dac_common #( up_dac_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.CLK_EDGE_SEL (1'b0), .CLK_EDGE_SEL (1'b0),
.COMMON_ID (6'h10), .COMMON_ID (6'h10),

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@ -25,13 +25,19 @@ adi_ip_files axi_ad9162 [list \
"axi_ad9162_channel.v" \ "axi_ad9162_channel.v" \
"axi_ad9162_core.v" \ "axi_ad9162_core.v" \
"axi_ad9162_if.v" \ "axi_ad9162_if.v" \
"axi_ad9162.v" ] "axi_ad9162.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9162 adi_ip_properties axi_ad9162
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -36,7 +36,11 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_ad9250 #( module axi_ad9250 #(
parameter ID = 0 parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0
) ( ) (
// jesd interface // jesd interface
@ -87,6 +91,10 @@ module axi_ad9250 #(
ad_ip_jesd204_tpl_adc #( ad_ip_jesd204_tpl_adc #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES (2), .NUM_LANES (2),
.NUM_CHANNELS (2), .NUM_CHANNELS (2),
.SAMPLES_PER_FRAME (1), .SAMPLES_PER_FRAME (1),

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@ -1,6 +1,8 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9250 Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9250 set_module_property DISPLAY_NAME axi_ad9250
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -48,6 +51,8 @@ set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true set_parameter_property ID HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn

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@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9250 adi_ip_create axi_ad9250
adi_ip_files axi_ad9250 [list \ adi_ip_files axi_ad9250 [list \
"axi_ad9250.v" ] "axi_ad9250.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9250 adi_ip_properties axi_ad9250
adi_ip_bd axi_ad9250 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_ip_add_core_dependencies { \ adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
} }
@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,7 +38,10 @@
module axi_ad9265 #( module axi_ad9265 #(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter ADC_DATAPATH_DISABLE = 0, parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") ( parameter IO_DELAY_GROUP = "adc_if_delay_group") (
@ -180,7 +183,7 @@ module axi_ad9265 #(
// main (device interface) // main (device interface)
axi_ad9265_if #( axi_ad9265_if #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if ( i_if (
.adc_clk_in_p (adc_clk_in_p), .adc_clk_in_p (adc_clk_in_p),
@ -224,7 +227,11 @@ module axi_ad9265 #(
// common processor control // common processor control
up_adc_common #( up_adc_common #(
.ID(ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.COMMON_ID (6'h00), .COMMON_ID (6'h00),
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),

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@ -39,7 +39,7 @@
module axi_ad9265_if #( module axi_ad9265_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") ( parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
@ -98,7 +98,7 @@ module axi_ad9265_if #(
generate generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_data_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_data ( i_adc_data (
@ -120,7 +120,7 @@ module axi_ad9265_if #(
// over-range interface // over-range interface
ad_data_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_or ( i_adc_or (
@ -139,8 +139,7 @@ module axi_ad9265_if #(
// clock // clock
ad_data_clk #( ad_data_clk
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk ( i_adc_clk (
.rst (1'b0), .rst (1'b0),
.locked (), .locked (),

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@ -25,10 +25,13 @@ adi_ip_files axi_ad9265 [list \
"axi_ad9265_pnmon.v" \ "axi_ad9265_pnmon.v" \
"axi_ad9265_if.v" \ "axi_ad9265_if.v" \
"axi_ad9265_channel.v" \ "axi_ad9265_channel.v" \
"axi_ad9265.v"] "axi_ad9265.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9265 adi_ip_properties axi_ad9265
adi_ip_bd axi_ad9265 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
@ -37,4 +40,7 @@ ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::curr
ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -37,7 +37,7 @@
module axi_ad9361_cmos_if #( module axi_ad9361_cmos_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0, parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (

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@ -37,7 +37,7 @@
module axi_ad9361_lvds_if #( module axi_ad9361_lvds_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0, parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
@ -178,8 +178,8 @@ module axi_ad9361_lvds_if #(
// local parameters // local parameters
localparam ARRIA10 = 0; localparam CYCLONE5 = 'h10;
localparam CYCLONE5 = 1; localparam ARRIA10 = 'h12;
// unused interface signals // unused interface signals
@ -431,7 +431,7 @@ module axi_ad9361_lvds_if #(
end end
generate generate
if (DEVICE_TYPE == CYCLONE5) begin if (FPGA_TECHNOLOGY == CYCLONE5) begin
axi_ad9361_lvds_if_c5 i_axi_ad9361_lvds_if_c5 ( axi_ad9361_lvds_if_c5 i_axi_ad9361_lvds_if_c5 (
.rx_clk_in_p (rx_clk_in_p), .rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n), .rx_clk_in_n (rx_clk_in_n),
@ -467,7 +467,7 @@ module axi_ad9361_lvds_if #(
endgenerate endgenerate
generate generate
if (DEVICE_TYPE == ARRIA10) begin if (FPGA_TECHNOLOGY == ARRIA10) begin
axi_ad9361_lvds_if_10 i_axi_ad9361_lvds_if_10 ( axi_ad9361_lvds_if_10 i_axi_ad9361_lvds_if_10 (
.rx_clk_in_p (rx_clk_in_p), .rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n), .rx_clk_in_n (rx_clk_in_n),

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@ -41,7 +41,10 @@ module axi_ad9361 #(
parameter ID = 0, parameter ID = 0,
parameter MODE_1R1T = 0, parameter MODE_1R1T = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter TDD_DISABLE = 0, parameter TDD_DISABLE = 0,
parameter PPS_RECEIVER_ENABLE = 0, parameter PPS_RECEIVER_ENABLE = 0,
parameter CMOS_OR_LVDS_N = 0, parameter CMOS_OR_LVDS_N = 0,
@ -324,7 +327,7 @@ module axi_ad9361 #(
assign tx_data_out_n = 6'h3f; assign tx_data_out_n = 6'h3f;
axi_ad9361_cmos_if #( axi_ad9361_cmos_if #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))
i_dev_if ( i_dev_if (
@ -385,7 +388,7 @@ module axi_ad9361 #(
assign up_dac_drdata_s[79:50] = 30'd0; assign up_dac_drdata_s[79:50] = 30'd0;
axi_ad9361_lvds_if #( axi_ad9361_lvds_if #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))
i_dev_if ( i_dev_if (
@ -566,6 +569,10 @@ module axi_ad9361 #(
axi_ad9361_rx #( axi_ad9361_rx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.MODE_1R1T (MODE_1R1T), .MODE_1R1T (MODE_1R1T),
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE), .PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
@ -631,6 +638,10 @@ module axi_ad9361 #(
axi_ad9361_tx #( axi_ad9361_tx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.MODE_1R1T (MODE_1R1T), .MODE_1R1T (MODE_1R1T),
.CLK_EDGE_SEL (DAC_CLK_EDGE_SEL), .CLK_EDGE_SEL (DAC_CLK_EDGE_SEL),
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),

View File

@ -1,9 +1,13 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
set_module_property VALIDATION_CALLBACK info_param_validate
ad_ip_files axi_ad9361 [list\ ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/altera/common/ad_mul.v \ $ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/altera/common/ad_dcfilter.v \ $ad_hdl_dir/library/altera/common/ad_dcfilter.v \
@ -50,10 +54,8 @@ ad_ip_files axi_ad9361 [list\
# parameters # parameters
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter ID INTEGER 0 ad_ip_parameter ID INTEGER 0
ad_ip_parameter MODE_1R1T INTEGER 0 ad_ip_parameter MODE_1R1T INTEGER 0
ad_ip_parameter DEVICE_TYPE INTEGER 0
ad_ip_parameter TDD_DISABLE INTEGER 0 ad_ip_parameter TDD_DISABLE INTEGER 0
ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0 ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0
ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0 ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0
@ -68,6 +70,8 @@ ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0
ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0 ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group} ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
adi_add_auto_fpga_spec_params
# interfaces # interfaces
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
@ -165,27 +169,27 @@ ad_alt_intf signal up_adc_gpio_out output 32
proc axi_ad9361_elab {} { proc axi_ad9361_elab {} {
set m_device_family [get_parameter_value "DEVICE_FAMILY"] set m_fpga_technology [get_parameter_value "FPGA_TECHNOLOGY"]
set m_cmos_or_lvds_n [get_parameter_value "CMOS_OR_LVDS_N"] set m_cmos_or_lvds_n [get_parameter_value "CMOS_OR_LVDS_N"]
if {$m_device_family eq "Arria 10"} { if {$m_fpga_technology eq "Arria 10"} {
add_hdl_instance axi_ad9361_serdes_clk alt_serdes add_hdl_instance axi_ad9361_serdes_clk alt_serdes
set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} $m_device_family set_instance_parameter_value axi_ad9361_serdes_clk {FPGA_TECHNOLOGY} $m_fpga_technology
set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK} set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK}
set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0} set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_in alt_serdes add_hdl_instance axi_ad9361_serdes_in alt_serdes
set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} $m_device_family set_instance_parameter_value axi_ad9361_serdes_in {FPGA_TECHNOLOGY} $m_fpga_technology
set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN} set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN}
set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0} set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_out alt_serdes add_hdl_instance axi_ad9361_serdes_out alt_serdes
set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} $m_device_family set_instance_parameter_value axi_ad9361_serdes_out {FPGA_TECHNOLOGY} $m_fpga_technology
set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT} set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT}
set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4}

View File

@ -48,11 +48,14 @@ adi_ip_files axi_ad9361 [list \
"axi_ad9361_tx.v" \ "axi_ad9361_tx.v" \
"axi_ad9361_tdd.v" \ "axi_ad9361_tdd.v" \
"axi_ad9361_tdd_if.v" \ "axi_ad9361_tdd_if.v" \
"axi_ad9361.v" ] "axi_ad9361.v" \
"bd/bd.tcl"]
adi_ip_properties axi_ad9361 adi_ip_properties axi_ad9361
adi_ip_ttcl axi_ad9361 "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" adi_ip_ttcl axi_ad9361 "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl"
adi_ip_bd axi_ad9361 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]]
@ -99,5 +102,8 @@ set_property value "ACTIVE_HIGH" $reset_polarity
ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

View File

@ -41,6 +41,10 @@ module axi_ad9361_rx #(
// parameters // parameters
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter MODE_1R1T = 0, parameter MODE_1R1T = 0,
parameter CMOS_OR_LVDS_N = 0, parameter CMOS_OR_LVDS_N = 0,
parameter PPS_RECEIVER_ENABLE = 0, parameter PPS_RECEIVER_ENABLE = 0,
@ -333,6 +337,10 @@ module axi_ad9361_rx #(
up_adc_common #( up_adc_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (CONFIG), .CONFIG (CONFIG),
.DRP_DISABLE (1), .DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),

View File

@ -40,6 +40,10 @@ module axi_ad9361_tx #(
// parameters // parameters
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter MODE_1R1T = 0, parameter MODE_1R1T = 0,
parameter CLK_EDGE_SEL = 0, parameter CLK_EDGE_SEL = 0,
parameter CMOS_OR_LVDS_N = 0, parameter CMOS_OR_LVDS_N = 0,
@ -354,6 +358,10 @@ module axi_ad9361_tx #(
up_dac_common #( up_dac_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (CONFIG), .CONFIG (CONFIG),
.CLK_EDGE_SEL (CLK_EDGE_SEL), .CLK_EDGE_SEL (CLK_EDGE_SEL),
.DRP_DISABLE (1), .DRP_DISABLE (1),

View File

@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -37,7 +37,7 @@
module axi_ad9361_cmos_if #( module axi_ad9361_cmos_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0, parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
@ -366,7 +366,7 @@ module axi_ad9361_cmos_if #(
for (i = 0; i < 12; i = i + 1) begin: g_rx_data for (i = 0; i < 12; i = i + 1) begin: g_rx_data
ad_data_in #( ad_data_in #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data ( i_rx_data (
@ -389,7 +389,7 @@ module axi_ad9361_cmos_if #(
ad_data_in #( ad_data_in #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame ( i_rx_frame (
@ -412,7 +412,7 @@ module axi_ad9361_cmos_if #(
for (i = 0; i < 12; i = i + 1) begin: g_tx_data for (i = 0; i < 12; i = i + 1) begin: g_tx_data
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -436,7 +436,7 @@ module axi_ad9361_cmos_if #(
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -458,7 +458,7 @@ module axi_ad9361_cmos_if #(
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -480,7 +480,7 @@ module axi_ad9361_cmos_if #(
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -502,7 +502,7 @@ module axi_ad9361_cmos_if #(
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -523,8 +523,7 @@ module axi_ad9361_cmos_if #(
// device clock interface (receive clock) // device clock interface (receive clock)
ad_data_clk #( ad_data_clk #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1))
.DEVICE_TYPE (DEVICE_TYPE))
i_clk ( i_clk (
.rst (1'd0), .rst (1'd0),
.locked (), .locked (),

View File

@ -37,7 +37,7 @@
module axi_ad9361_lvds_if #( module axi_ad9361_lvds_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0, parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
@ -472,7 +472,7 @@ module axi_ad9361_lvds_if #(
generate generate
for (i = 0; i < 6; i = i + 1) begin: g_rx_data for (i = 0; i < 6; i = i + 1) begin: g_rx_data
ad_data_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data ( i_rx_data (
@ -494,7 +494,7 @@ module axi_ad9361_lvds_if #(
// receive frame interface, ibuf -> idelay -> iddr // receive frame interface, ibuf -> idelay -> iddr
ad_data_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame ( i_rx_frame (
@ -516,7 +516,7 @@ module axi_ad9361_lvds_if #(
generate generate
for (i = 0; i < 6; i = i + 1) begin: g_tx_data for (i = 0; i < 6; i = i + 1) begin: g_tx_data
ad_data_out #( ad_data_out #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -539,7 +539,7 @@ module axi_ad9361_lvds_if #(
// transmit frame interface, oddr -> obuf // transmit frame interface, oddr -> obuf
ad_data_out #( ad_data_out #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -560,7 +560,7 @@ module axi_ad9361_lvds_if #(
// transmit clock interface, oddr -> obuf // transmit clock interface, oddr -> obuf
ad_data_out #( ad_data_out #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -582,7 +582,7 @@ module axi_ad9361_lvds_if #(
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -604,7 +604,7 @@ module axi_ad9361_lvds_if #(
ad_data_out #( ad_data_out #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -624,8 +624,7 @@ module axi_ad9361_lvds_if #(
// device clock interface (receive clock) // device clock interface (receive clock)
ad_data_clk #( ad_data_clk
.DEVICE_TYPE (DEVICE_TYPE))
i_clk ( i_clk (
.rst (1'd0), .rst (1'd0),
.locked (), .locked (),

View File

@ -38,6 +38,10 @@
module axi_ad9371 #( module axi_ad9371 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18, parameter DAC_DDS_CORDIC_PHASE_DW = 18,
@ -203,6 +207,10 @@ module axi_ad9371 #(
axi_ad9371_rx #( axi_ad9371_rx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx ( i_rx (
.adc_rst (adc_rst), .adc_rst (adc_rst),
@ -236,6 +244,10 @@ module axi_ad9371 #(
axi_ad9371_rx_os #( axi_ad9371_rx_os #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx_os ( i_rx_os (
.adc_os_rst (adc_os_rst), .adc_os_rst (adc_os_rst),
@ -264,6 +276,10 @@ module axi_ad9371 #(
axi_ad9371_tx #( axi_ad9371_tx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),

View File

@ -1,6 +1,8 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9371 Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9371 set_module_property DISPLAY_NAME axi_ad9371
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -69,6 +72,8 @@ set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property ADC_DATAPATH_DISABLE UNITS None set_parameter_property ADC_DATAPATH_DISABLE UNITS None
set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn

View File

@ -35,15 +35,21 @@ adi_ip_files axi_ad9371 [list \
"axi_ad9371_rx_os.v" \ "axi_ad9371_rx_os.v" \
"axi_ad9371_tx_channel.v" \ "axi_ad9371_tx_channel.v" \
"axi_ad9371_tx.v" \ "axi_ad9371_tx.v" \
"axi_ad9371.v" ] "axi_ad9371.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9371 adi_ip_properties axi_ad9371
adi_ip_bd axi_ad9371 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -37,8 +37,12 @@
module axi_ad9371_rx #( module axi_ad9371_rx #(
parameter DATAPATH_DISABLE = 0, parameter ID = 0,
parameter ID = 0) ( parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DATAPATH_DISABLE = 0) (
// adc interface // adc interface
@ -255,6 +259,10 @@ module axi_ad9371_rx #(
up_adc_common #( up_adc_common #(
.COMMON_ID ('h00), .COMMON_ID ('h00),
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.DRP_DISABLE (0), .DRP_DISABLE (0),
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),

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@ -37,8 +37,12 @@
module axi_ad9371_rx_os #( module axi_ad9371_rx_os #(
parameter DATAPATH_DISABLE = 0, parameter ID = 0,
parameter ID = 0) ( parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DATAPATH_DISABLE = 0) (
// adc interface // adc interface
@ -176,8 +180,12 @@ module axi_ad9371_rx_os #(
up_adc_common #( up_adc_common #(
.COMMON_ID ('h20), .COMMON_ID ('h20),
.ID (ID)) .ID (ID),
i_up_adc_common ( .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)
) i_up_adc_common (
.mmcm_rst (), .mmcm_rst (),
.adc_clk (adc_os_clk), .adc_clk (adc_os_clk),
.adc_rst (adc_os_rst), .adc_rst (adc_os_rst),

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@ -38,6 +38,10 @@
module axi_ad9371_tx #( module axi_ad9371_tx #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
@ -255,7 +259,13 @@ module axi_ad9371_tx #(
// dac common processor interface // dac common processor interface
up_dac_common #(.ID (ID)) i_up_dac_common ( up_dac_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)
) i_up_dac_common (
.mmcm_rst (), .mmcm_rst (),
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -39,8 +39,10 @@ module axi_ad9434 #(
parameter ID = 0, parameter ID = 0,
// set to 0 for Xilinx 7 Series or 1 for 6 Series parameter FPGA_TECHNOLOGY = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface // physical interface
@ -128,7 +130,7 @@ module axi_ad9434 #(
assign up_rstn = s_axi_aresetn; assign up_rstn = s_axi_aresetn;
axi_ad9434_if #( axi_ad9434_if #(
.DEVICE_TYPE(DEVICE_TYPE), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IO_DELAY_GROUP(IO_DELAY_GROUP)) .IO_DELAY_GROUP(IO_DELAY_GROUP))
i_if( i_if(
.adc_clk_in_p(adc_clk_in_p), .adc_clk_in_p(adc_clk_in_p),
@ -160,8 +162,13 @@ module axi_ad9434 #(
.up_drp_locked(up_drp_locked_s)); .up_drp_locked(up_drp_locked_s));
// common processor control // common processor control
axi_ad9434_core #(.ID(ID)) axi_ad9434_core #(
i_core ( .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)
) i_core (
.adc_clk(adc_clk), .adc_clk(adc_clk),
.adc_data(adc_data_if_s), .adc_data(adc_data_if_s),
.adc_or(adc_or_if_s), .adc_or(adc_or_if_s),

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@ -37,7 +37,11 @@
module axi_ad9434_core #( module axi_ad9434_core #(
parameter ID = 0) ( parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
// device interface // device interface
@ -148,6 +152,10 @@ module axi_ad9434_core #(
up_adc_common #( up_adc_common #(
.ID(ID), .ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(0), .CONFIG(0),
.COMMON_ID(0), .COMMON_ID(0),
.DRP_DISABLE(0), .DRP_DISABLE(0),

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@ -37,7 +37,7 @@
module axi_ad9434_if #( module axi_ad9434_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// device interface // device interface
@ -100,7 +100,7 @@ module axi_ad9434_if #(
// data interface // data interface
ad_serdes_in #( ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IODELAY_CTRL(0), .IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
@ -133,7 +133,7 @@ module axi_ad9434_if #(
// over-range interface // over-range interface
ad_serdes_in #( ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IODELAY_CTRL(1), .IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
@ -166,7 +166,7 @@ module axi_ad9434_if #(
// clock input buffers and MMCM_OR_BUFR_N // clock input buffers and MMCM_OR_BUFR_N
ad_serdes_clk #( ad_serdes_clk #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.CLKIN_DS_OR_SE_N (1), .CLKIN_DS_OR_SE_N (1),
.MMCM_OR_BUFR_N (1), .MMCM_OR_BUFR_N (1),
.MMCM_CLKIN_PERIOD (2), .MMCM_CLKIN_PERIOD (2),

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@ -26,14 +26,20 @@ adi_ip_files axi_ad9434 [list \
"axi_ad9434_pnmon.v" \ "axi_ad9434_pnmon.v" \
"axi_ad9434_core.v" \ "axi_ad9434_core.v" \
"axi_ad9434_constr.xdc" \ "axi_ad9434_constr.xdc" \
"axi_ad9434.v" ] "axi_ad9434.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9434 adi_ip_properties axi_ad9434
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,7 +38,10 @@
module axi_ad9467#( module axi_ad9467#(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface // physical interface
@ -144,7 +147,7 @@ module axi_ad9467#(
// main (device interface) // main (device interface)
axi_ad9467_if #( axi_ad9467_if #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if ( i_if (
.adc_clk_in_p (adc_clk_in_p), .adc_clk_in_p (adc_clk_in_p),
@ -211,7 +214,11 @@ module axi_ad9467#(
// common processor control // common processor control
up_adc_common #( up_adc_common #(
.ID(ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.COMMON_ID (6'h00), .COMMON_ID (6'h00),
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),

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@ -38,7 +38,7 @@
module axi_ad9467_if #( module axi_ad9467_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
@ -128,7 +128,7 @@ module axi_ad9467_if #(
generate generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_data_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_data ( i_adc_data (
@ -150,7 +150,7 @@ module axi_ad9467_if #(
// over-range interface // over-range interface
ad_data_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_adc_or ( i_adc_or (
@ -169,8 +169,7 @@ module axi_ad9467_if #(
// clock // clock
ad_data_clk #( ad_data_clk
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk ( i_adc_clk (
.rst (1'b0), .rst (1'b0),
.locked (), .locked (),

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@ -24,10 +24,13 @@ adi_ip_files axi_ad9467 [list \
"axi_ad9467_pnmon.v" \ "axi_ad9467_pnmon.v" \
"axi_ad9467_if.v" \ "axi_ad9467_if.v" \
"axi_ad9467_channel.v" \ "axi_ad9467_channel.v" \
"axi_ad9467.v"] "axi_ad9467.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9467 adi_ip_properties axi_ad9467
adi_ip_bd axi_ad9467 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
@ -35,4 +38,7 @@ ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current
ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -37,7 +37,11 @@
module axi_ad9625 #( module axi_ad9625 #(
parameter ID = 0) ( parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -180,6 +184,10 @@ module axi_ad9625 #(
up_adc_common #( up_adc_common #(
.ID(ID), .ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(0), .CONFIG(0),
.COMMON_ID(6'h0), .COMMON_ID(6'h0),
.DRP_DISABLE(1), .DRP_DISABLE(1),

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@ -23,10 +23,13 @@ adi_ip_files axi_ad9625 [list \
"axi_ad9625_pnmon.v" \ "axi_ad9625_pnmon.v" \
"axi_ad9625_channel.v" \ "axi_ad9625_channel.v" \
"axi_ad9625_if.v" \ "axi_ad9625_if.v" \
"axi_ad9625.v" ] "axi_ad9625.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9625 adi_ip_properties axi_ad9625
adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
@ -36,5 +39,8 @@ ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_co
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,50 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,6 +38,10 @@
module axi_ad9671 #( module axi_ad9671 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter QUAD_OR_DUAL_N = 1) ( parameter QUAD_OR_DUAL_N = 1) (
// jesd interface // jesd interface
@ -220,7 +224,13 @@ module axi_ad9671 #(
// common processor control // common processor control
up_adc_common #(.ID (ID)) i_up_adc_common ( up_adc_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)
) i_up_adc_common (
.mmcm_rst (), .mmcm_rst (),
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),

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@ -1,6 +1,8 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9671 Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9671 set_module_property DISPLAY_NAME axi_ad9671
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -50,6 +53,8 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
set_parameter_property QUAD_OR_DUAL_N UNITS None set_parameter_property QUAD_OR_DUAL_N UNITS None
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn

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@ -23,14 +23,20 @@ adi_ip_files axi_ad9671 [list \
"axi_ad9671_pnmon.v" \ "axi_ad9671_pnmon.v" \
"axi_ad9671_channel.v" \ "axi_ad9671_channel.v" \
"axi_ad9671_if.v" \ "axi_ad9671_if.v" \
"axi_ad9671.v" ] "axi_ad9671.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9671 adi_ip_properties axi_ad9671
adi_ip_bd axi_ad9371 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,50 @@
## ***************************************************************************
## ***************************************************************************
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
##
## In this HDL repository, there are many different and unique modules, consisting
## of various HDL (Verilog or VHDL) components. The individual modules are
## developed independently, and may be accompanied by separate and unique license
## terms.
##
## The user should read each of these license terms, and understand the
## freedoms and responsibilities that he or she has by using this source/core.
##
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
## A PARTICULAR PURPOSE.
##
## Redistribution and use of source or resulting binaries, with or without modification
## of this file, are permitted under one of the following two license terms:
##
## 1. The GNU General Public License version 2 as published by the
## Free Software Foundation, which can be found in the top level directory
## of this repository (LICENSE_GPL2), and also online at:
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
##
## OR
##
## 2. An ADI specific BSD license, which can be found in the top level directory
## of this repository (LICENSE_ADIBSD), and also on-line at:
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
## This will allow to generate bit files and not release the source code,
## as long as it attaches to an ADI device.
##
## ***************************************************************************
## ***************************************************************************
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -37,7 +37,11 @@
module axi_ad9680 #( module axi_ad9680 #(
parameter ID = 0) ( parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -87,6 +91,10 @@ module axi_ad9680 #(
ad_ip_jesd204_tpl_adc #( ad_ip_jesd204_tpl_adc #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_LANES (4), .NUM_LANES (4),
.NUM_CHANNELS (2), .NUM_CHANNELS (2),
.SAMPLES_PER_FRAME (1), .SAMPLES_PER_FRAME (1),

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@ -1,6 +1,8 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9680 Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9680 set_module_property DISPLAY_NAME axi_ad9680
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -48,6 +51,8 @@ set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true set_parameter_property ID HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn

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@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9680 adi_ip_create axi_ad9680
adi_ip_files axi_ad9680 [list \ adi_ip_files axi_ad9680 [list \
"axi_ad9680.v" ] "axi_ad9680.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9680 adi_ip_properties axi_ad9680
adi_ip_bd axi_ad9680 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
adi_ip_add_core_dependencies { \ adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
} }
@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,7 +38,10 @@
module axi_ad9684 #( module axi_ad9684 #(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 1) ( parameter OR_STATUS = 1) (
@ -163,7 +166,7 @@ module axi_ad9684 #(
// device interface instance // device interface instance
axi_ad9684_if #( axi_ad9684_if #(
.DEVICE_TYPE(DEVICE_TYPE), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IO_DELAY_GROUP(IO_DELAY_GROUP), .IO_DELAY_GROUP(IO_DELAY_GROUP),
.OR_STATUS (OR_STATUS)) .OR_STATUS (OR_STATUS))
i_ad9684_if ( i_ad9684_if (
@ -204,7 +207,11 @@ module axi_ad9684 #(
assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1]; assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1];
up_adc_common #( up_adc_common #(
.ID(ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.COMMON_ID (6'h00), .COMMON_ID (6'h00),
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),

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@ -1,9 +1,13 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab
set_module_property VALIDATION_CALLBACK info_param_validate
ad_ip_files axi_ad9684 [list \ ad_ip_files axi_ad9684 [list \
$ad_hdl_dir/library/common/ad_rst.v \ $ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/ad_datafmt.v \ $ad_hdl_dir/library/common/ad_datafmt.v \
@ -36,13 +40,13 @@ set_parameter_property ID DESCRIPTION "Instance ID"
set_parameter_property ID UNITS None set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0 add_parameter FPGA_TECHNOLOGY INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY
set_parameter_property DEVICE_TYPE TYPE INTEGER set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER
set_parameter_property DEVICE_TYPE DESCRIPTION "Specify the FPGA device type" set_parameter_property FPGA_TECHNOLOGY DESCRIPTION "Specify the FPGA device type"
set_parameter_property DEVICE_TYPE UNITS None set_parameter_property FPGA_TECHNOLOGY UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true
add_parameter OR_STATUS INTEGER 1 add_parameter OR_STATUS INTEGER 1
set_parameter_property OR_STATUS DEFAULT_VALUE 1 set_parameter_property OR_STATUS DEFAULT_VALUE 1
@ -52,6 +56,8 @@ set_parameter_property OR_STATUS DESCRIPTION "This parameter enables the OVER RA
set_parameter_property OR_STATUS UNITS None set_parameter_property OR_STATUS UNITS None
set_parameter_property OR_STATUS HDL_PARAMETER true set_parameter_property OR_STATUS HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn

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@ -37,7 +37,7 @@
module axi_ad9684_if #( module axi_ad9684_if #(
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 0) ( parameter OR_STATUS = 0) (
@ -106,7 +106,7 @@ module axi_ad9684_if #(
// data interface // data interface
ad_serdes_in #( ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IODELAY_CTRL(1), .IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N), .DDR_OR_SDR_N(DDR_OR_SDR_N),
@ -139,7 +139,7 @@ module axi_ad9684_if #(
generate if (OR_STATUS == 1) begin generate if (OR_STATUS == 1) begin
ad_serdes_in #( ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IODELAY_CTRL(0), .IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N), .DDR_OR_SDR_N(DDR_OR_SDR_N),
@ -183,7 +183,7 @@ module axi_ad9684_if #(
// clock input buffers and MMCM_OR_BUFR_N // clock input buffers and MMCM_OR_BUFR_N
ad_serdes_clk #( ad_serdes_clk #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.MMCM_CLKIN_PERIOD (2), .MMCM_CLKIN_PERIOD (2),
.MMCM_VCO_DIV (6), .MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12), .MMCM_VCO_MUL (12),

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@ -27,10 +27,13 @@ adi_ip_files axi_ad9684 [list \
"axi_ad9684_if.v" \ "axi_ad9684_if.v" \
"axi_ad9684_channel.v" \ "axi_ad9684_channel.v" \
"axi_ad9684_constr.xdc" \ "axi_ad9684_constr.xdc" \
"axi_ad9684.v"] "axi_ad9684.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9684 adi_ip_properties axi_ad9684
adi_ip_bd axi_ad9684 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
@ -39,4 +42,7 @@ ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -38,7 +38,10 @@
module axi_ad9739a #( module axi_ad9739a #(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter SERDES_OR_DDR_N = 1, parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1, parameter MMCM_OR_BUFIO_N = 1,
parameter DAC_DDS_TYPE = 2, parameter DAC_DDS_TYPE = 2,
@ -132,7 +135,7 @@ module axi_ad9739a #(
// device interface // device interface
axi_ad9739a_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( axi_ad9739a_if #(.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_if (
.dac_clk_in_p (dac_clk_in_p), .dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n), .dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p), .dac_clk_out_p (dac_clk_out_p),
@ -166,6 +169,10 @@ module axi_ad9739a #(
axi_ad9739a_core #( axi_ad9739a_core #(
.ID(ID), .ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),

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@ -38,6 +38,10 @@
module axi_ad9739a_core #( module axi_ad9739a_core #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
@ -161,7 +165,13 @@ module axi_ad9739a_core #(
// dac common processor interface // dac common processor interface
up_dac_common #(.ID(ID)) i_up_dac_common ( up_dac_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)
) i_up_dac_common (
.mmcm_rst (), .mmcm_rst (),
.dac_clk (dac_div_clk), .dac_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),

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@ -39,7 +39,7 @@
module axi_ad9739a_if #( module axi_ad9739a_if #(
parameter DEVICE_TYPE = 0) ( parameter FPGA_TECHNOLOGY = 0) (
// dac interface // dac interface
@ -102,7 +102,7 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(14), .DATA_WIDTH(14),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.DEVICE_TYPE (DEVICE_TYPE)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_data_a ( i_serdes_out_data_a (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
@ -126,7 +126,7 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(14), .DATA_WIDTH(14),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.DEVICE_TYPE (DEVICE_TYPE)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_data_b ( i_serdes_out_data_b (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
@ -150,7 +150,7 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(1), .DATA_WIDTH(1),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.DEVICE_TYPE (DEVICE_TYPE)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_clk ( i_serdes_out_clk (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),

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@ -27,11 +27,17 @@ adi_ip_files axi_ad9739a [list \
"axi_ad9739a_channel.v" \ "axi_ad9739a_channel.v" \
"axi_ad9739a_core.v" \ "axi_ad9739a_core.v" \
"axi_ad9739a_if.v" \ "axi_ad9739a_if.v" \
"axi_ad9739a.v" ] "axi_ad9739a.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9739a adi_ip_properties axi_ad9739a
adi_ip_bd axi_ad9739a "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

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@ -40,7 +40,10 @@ module axi_ad9963 #(
// parameters // parameters
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter ADC_IODELAY_ENABLE = 0, parameter ADC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_ENABLE = 0, parameter IODELAY_ENABLE = 0,
@ -177,7 +180,7 @@ module axi_ad9963 #(
// device interface // device interface
axi_ad9963_if #( axi_ad9963_if #(
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE), .ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))
i_dev_if ( i_dev_if (
@ -210,6 +213,10 @@ module axi_ad9963 #(
axi_ad9963_rx #( axi_ad9963_rx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE), .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE),
@ -251,6 +258,10 @@ module axi_ad9963 #(
axi_ad9963_tx #( axi_ad9963_tx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),

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@ -39,7 +39,7 @@ module axi_ad9963_if #(
// this parameter controls the buffer type based on the target device. // this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter ADC_IODELAY_ENABLE = 0, parameter ADC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
@ -153,7 +153,7 @@ module axi_ad9963_if #(
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
ad_data_in #( ad_data_in #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -177,7 +177,7 @@ module axi_ad9963_if #(
ad_data_in #( ad_data_in #(
.SINGLE_ENDED (1), .SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))

View File

@ -38,10 +38,13 @@ adi_ip_files axi_ad9963 [list \
"axi_ad9963_rx.v" \ "axi_ad9963_rx.v" \
"axi_ad9963_tx_channel.v" \ "axi_ad9963_tx_channel.v" \
"axi_ad9963_tx.v" \ "axi_ad9963_tx.v" \
"axi_ad9963.v" ] "axi_ad9963.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_ad9963 adi_ip_properties axi_ad9963
adi_ip_bd axi_ad9963 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
@ -59,5 +62,8 @@ ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_c
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

View File

@ -45,7 +45,11 @@ module axi_ad9963_rx #(
parameter IQCORRECTION_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0,
parameter SCALECORRECTION_ONLY = 1, parameter SCALECORRECTION_ONLY = 1,
parameter IODELAY_ENABLE = 0, parameter IODELAY_ENABLE = 0,
parameter ID = 0) ( parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
// adc interface // adc interface
@ -209,6 +213,10 @@ module axi_ad9963_rx #(
up_adc_common #( up_adc_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (CONFIG), .CONFIG (CONFIG),
.COMMON_ID(6'h00), .COMMON_ID(6'h00),
.DRP_DISABLE (1), .DRP_DISABLE (1),

View File

@ -40,6 +40,10 @@ module axi_ad9963_tx #(
// parameters // parameters
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14, parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter DAC_DDS_CORDIC_PHASE_DW = 13,
@ -186,6 +190,10 @@ module axi_ad9963_tx #(
up_dac_common #( up_dac_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(0), .CONFIG(0),
.CLK_EDGE_SEL(0), .CLK_EDGE_SEL(0),
.COMMON_ID(6'h10), .COMMON_ID(6'h10),

View File

@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

View File

@ -38,6 +38,10 @@
module axi_adrv9009 #( module axi_adrv9009 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter ADC_DATAPATH_DISABLE = 0, parameter ADC_DATAPATH_DISABLE = 0,
parameter ADC_DATAFORMAT_DISABLE = 0, parameter ADC_DATAFORMAT_DISABLE = 0,
parameter ADC_DCFILTER_DISABLE = 0, parameter ADC_DCFILTER_DISABLE = 0,
@ -230,6 +234,10 @@ module axi_adrv9009 #(
axi_adrv9009_rx #( axi_adrv9009_rx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)) .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
@ -265,6 +273,10 @@ module axi_adrv9009 #(
axi_adrv9009_rx_os #( axi_adrv9009_rx_os #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)) .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
@ -302,6 +314,10 @@ module axi_adrv9009 #(
axi_adrv9009_tx #( axi_adrv9009_tx #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DDS_DISABLE (DAC_DDS_DISABLE_INT), .DDS_DISABLE (DAC_DDS_DISABLE_INT),
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT), .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),

View File

@ -1,6 +1,8 @@
package require qsys package require qsys
package require quartus::device
source ../scripts/adi_env.tcl source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl source ../scripts/adi_ip_alt.tcl
@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI adrv9009 Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_adrv9009 set_module_property DISPLAY_NAME axi_adrv9009
set_module_property VALIDATION_CALLBACK info_param_validate
# files # files
@ -132,6 +135,8 @@ set_parameter_property DAC_IQCORRECTION_DISABLE TYPE INTEGER
set_parameter_property DAC_IQCORRECTION_DISABLE UNITS None set_parameter_property DAC_IQCORRECTION_DISABLE UNITS None
set_parameter_property DAC_IQCORRECTION_DISABLE HDL_PARAMETER true set_parameter_property DAC_IQCORRECTION_DISABLE HDL_PARAMETER true
adi_add_auto_fpga_spec_params
# axi4 slave # axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn

View File

@ -35,10 +35,13 @@ adi_ip_files axi_adrv9009 [list \
"axi_adrv9009_rx_os.v" \ "axi_adrv9009_rx_os.v" \
"axi_adrv9009_tx_channel.v" \ "axi_adrv9009_tx_channel.v" \
"axi_adrv9009_tx.v" \ "axi_adrv9009_tx.v" \
"axi_adrv9009.v" ] "axi_adrv9009.v" \
"bd/bd.tcl" ]
adi_ip_properties axi_adrv9009 adi_ip_properties axi_adrv9009
adi_ip_bd axi_adrv9009 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
@ -50,5 +53,8 @@ ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_c
ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

View File

@ -38,6 +38,10 @@
module axi_adrv9009_rx #( module axi_adrv9009_rx #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DATAFORMAT_DISABLE = 0, parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0, parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0) (
@ -272,6 +276,10 @@ module axi_adrv9009_rx #(
up_adc_common #( up_adc_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.COMMON_ID (6'h00), .COMMON_ID (6'h00),
.CONFIG(CONFIG), .CONFIG(CONFIG),
.DRP_DISABLE(1), .DRP_DISABLE(1),

View File

@ -38,6 +38,10 @@
module axi_adrv9009_rx_os #( module axi_adrv9009_rx_os #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DATAFORMAT_DISABLE = 0, parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0, parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0) (
@ -262,6 +266,10 @@ module axi_adrv9009_rx_os #(
up_adc_common #( up_adc_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.COMMON_ID ('h20), .COMMON_ID ('h20),
.CONFIG (CONFIG), .CONFIG (CONFIG),
.DRP_DISABLE (1), .DRP_DISABLE (1),

View File

@ -38,6 +38,10 @@
module axi_adrv9009_tx #( module axi_adrv9009_tx #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DISABLE = 0, parameter DISABLE = 0,
parameter DDS_DISABLE = 0, parameter DDS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0,
@ -269,6 +273,10 @@ module axi_adrv9009_tx #(
up_dac_common #( up_dac_common #(
.ID (ID), .ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(CONFIG), .CONFIG(CONFIG),
.CLK_EDGE_SEL(0), .CLK_EDGE_SEL(0),
.COMMON_ID(6'h10), .COMMON_ID(6'h10),

View File

@ -0,0 +1,16 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
}

View File

@ -39,7 +39,11 @@
module axi_clkgen #( module axi_clkgen #(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter FPGA_VOLTAGE = 0,
parameter CLKSEL_EN = 0, parameter CLKSEL_EN = 0,
parameter real CLKIN_PERIOD = 5.000, parameter real CLKIN_PERIOD = 5.000,
parameter real CLKIN2_PERIOD = 5.000, parameter real CLKIN2_PERIOD = 5.000,
@ -147,7 +151,12 @@ module axi_clkgen #(
// processor interface // processor interface
up_clkgen #( up_clkgen #(
.ID(ID) .ID(ID),
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.FPGA_FAMILY(FPGA_FAMILY),
.SPEED_GRADE(SPEED_GRADE),
.DEV_PACKAGE(DEV_PACKAGE),
.FPGA_VOLTAGE(FPGA_VOLTAGE)
) i_up_clkgen ( ) i_up_clkgen (
.mmcm_rst (mmcm_rst), .mmcm_rst (mmcm_rst),
.clk_sel (up_clk_sel_s), .clk_sel (up_clk_sel_s),
@ -182,7 +191,7 @@ module axi_clkgen #(
// mmcm instantiations // mmcm instantiations
ad_mmcm_drp #( ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (DEVICE_TYPE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.MMCM_CLKIN_PERIOD (CLKIN_PERIOD), .MMCM_CLKIN_PERIOD (CLKIN_PERIOD),
.MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD), .MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD),
.MMCM_VCO_DIV (VCO_DIV), .MMCM_VCO_DIV (VCO_DIV),

View File

@ -9,11 +9,13 @@ adi_ip_files axi_clkgen [list \
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_clkgen.v" \ "$ad_hdl_dir/library/common/up_clkgen.v" \
"$ad_hdl_dir/library/scripts/common_bd.tcl" \
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
"bd/bd.tcl" \ "bd/bd.tcl" \
"axi_clkgen.v" ] "axi_clkgen.v" ]
adi_ip_properties axi_clkgen adi_ip_properties axi_clkgen
adi_ip_bd axi_clkgen "bd/bd.tcl" adi_ip_bd axi_clkgen "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
@ -41,6 +43,9 @@ set_property -dict [list \
widget {checkBox} \ widget {checkBox} \
] $param ] $param
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc] set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc]
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc] set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc]
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc] set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc]

View File

@ -1,8 +1,23 @@
proc init {cellpath otherInfo} { proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath] set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip \ bd::mark_propagate_override $ip \
"CLKIN_PERIOD CLKIN2_PERIOD" "CLKIN_PERIOD \
CLKIN2_PERIOD \
FPGA_VOLTAGE"
bd::mark_propagate_only $ip \
"FPGA_TECHNOLOGY \
FPGA_FAMILY \
SPEED_GRADE \
DEV_PACKAGE \
FPGA_VOLTAGE"
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
source ${ip_path}../scripts/common_bd.tcl
adi_auto_assign_device_spec $cellpath
} }
proc axi_clkgen_get_infer_period {ip param clk_name} { proc axi_clkgen_get_infer_period {ip param clk_name} {

View File

@ -38,7 +38,13 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_fmcadc5_sync #(parameter integer ID = 0) ( module axi_fmcadc5_sync #(
parameter integer ID = 0,
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0) (
// receive interface // receive interface
@ -575,6 +581,7 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
14'h0001: up_rdata <= ID; 14'h0001: up_rdata <= ID;
14'h0002: up_rdata <= up_scratch; 14'h0002: up_rdata <= up_scratch;
14'h0003: up_rdata <= up_timer; 14'h0003: up_rdata <= up_timer;
14'h0007: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
14'h0010: up_rdata <= {31'd0, up_spi_req}; 14'h0010: up_rdata <= {31'd0, up_spi_req};
14'h0011: up_rdata <= {31'd0, up_spi_gnt}; 14'h0011: up_rdata <= {31'd0, up_spi_gnt};
14'h0012: up_rdata <= {24'd0, up_spi_csn}; 14'h0012: up_rdata <= {24'd0, up_spi_csn};
@ -757,7 +764,7 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
assign rx_sysref = rx_sysref_i; assign rx_sysref = rx_sysref_i;
ad_data_out #( ad_data_out #(
.DEVICE_TYPE (0), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.SINGLE_ENDED (0), .SINGLE_ENDED (0),
.IODELAY_ENABLE (1), .IODELAY_ENABLE (1),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),

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