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ad_tdd_control: Avoid single pulses if tx_only or rx_only

main
Laszlo Nagy 2020-10-14 11:11:12 +01:00 committed by Laszlo Nagy
parent 843c2565f7
commit 669217db8b
1 changed files with 8 additions and 8 deletions
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16
library/common/ad_tdd_control.v
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@ -779,10 +779,10 @@ module ad_tdd_control#(
tdd_rx_rf_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
tdd_rx_rf_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
tdd_rx_rf_en <= 1'b1;
end else begin
tdd_rx_rf_en <= tdd_rx_rf_en;
end
@ -793,10 +793,10 @@ module ad_tdd_control#(
tdd_tx_rf_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
tdd_tx_rf_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
tdd_tx_rf_en <= 1'b1;
end else begin
tdd_tx_rf_en <= tdd_tx_rf_en;
end
@ -807,10 +807,10 @@ module ad_tdd_control#(
tdd_tx_dp_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
tdd_tx_dp_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
tdd_tx_dp_en <= 1'b1;
end else begin
tdd_tx_dp_en <= tdd_tx_dp_en;
end
@ -821,10 +821,10 @@ module ad_tdd_control#(
tdd_rx_dp_en <= 1'b0;
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin
tdd_rx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin
tdd_rx_dp_en <= 1'b1;
end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin
tdd_rx_dp_en <= 1'b0;
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin
tdd_rx_dp_en <= 1'b1;
end else begin
tdd_rx_dp_en <= tdd_rx_dp_en;
end