From 66e6c1cc21b46f25e4d2123ba389bc4243a5e598 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 4 Apr 2014 11:38:46 +0200 Subject: [PATCH] axi_dmac: axi_register_slice: Remove reset "latch" from datapath Move the datapath updates out of the else branch of the reset condition. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_register_slice.v | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/library/axi_dmac/axi_register_slice.v b/library/axi_dmac/axi_register_slice.v index 7cf5d7b22..9543ceef5 100644 --- a/library/axi_dmac/axi_register_slice.v +++ b/library/axi_dmac/axi_register_slice.v @@ -78,12 +78,15 @@ assign fwd_ready_s = ~fwd_valid | m_axi_ready; assign fwd_valid_s = fwd_valid; assign fwd_data_s = fwd_data; +always @(posedge clk) begin + if (~fwd_valid | m_axi_ready) + fwd_data <= bwd_data_s; +end + always @(posedge clk) begin if (resetn == 1'b0) begin fwd_valid <= 1'b0; end else begin - if (~fwd_valid | m_axi_ready) - fwd_data <= bwd_data_s; if (bwd_valid_s) fwd_valid <= 1'b1; else if (m_axi_ready) @@ -107,12 +110,15 @@ assign bwd_valid_s = ~bwd_ready | s_axi_valid; assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data; assign bwd_ready_s = bwd_ready; +always @(posedge clk) begin + if (bwd_ready) + bwd_data <= s_axi_data; +end + always @(posedge clk) begin if (resetn == 1'b0) begin bwd_ready <= 1'b1; end else begin - if (bwd_ready) - bwd_data <= s_axi_data; if (fwd_ready_s) bwd_ready <= 1'b1; else if (s_axi_valid)