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axi_dmac: axi_register_slice: Remove reset "latch" from datapath 

Move the datapath updates out of the else branch of the reset condition.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-04-04 11:38:46 +02:00
parent 799d2384d8
commit 66e6c1cc21
1 changed files with 10 additions and 4 deletions
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14
library/axi_dmac/axi_register_slice.v
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@ -78,12 +78,15 @@ assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid; assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data; assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (resetn == 1'b0) begin
fwd_valid <= 1'b0; fwd_valid <= 1'b0;
end else begin end else begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
if (bwd_valid_s) if (bwd_valid_s)
fwd_valid <= 1'b1; fwd_valid <= 1'b1;
else if (m_axi_ready) else if (m_axi_ready)
@ -107,12 +110,15 @@ assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data; assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready; assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (bwd_ready)
bwd_data <= s_axi_data;
end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (resetn == 1'b0) begin
bwd_ready <= 1'b1; bwd_ready <= 1'b1;
end else begin end else begin
if (bwd_ready)
bwd_data <= s_axi_data;
if (fwd_ready_s) if (fwd_ready_s)
bwd_ready <= 1'b1; bwd_ready <= 1'b1;
else if (s_axi_valid) else if (s_axi_valid)