diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys
index 70d709650..046dcd128 100755
--- a/projects/daq2/a10gx/system_bd.qsys
+++ b/projects/daq2/a10gx/system_bd.qsys
@@ -13,11 +13,27 @@
    {
       datum _originalDeviceFamily
       {
-         value = "Arria V";
+         value = "Arria 10";
          type = "String";
       }
    }
-   element axi_ad9250_0
+   element axi_ad9144_core
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element axi_ad9144_core.s_axi
+   {
+      datum baseAddress
+      {
+         value = "2149580800";
+         type = "String";
+      }
+   }
+   element axi_ad9144_dma
    {
       datum _sortIndex
       {
@@ -30,61 +46,35 @@
          type = "boolean";
       }
    }
-   element axi_ad9250_0.s_axi
+   element axi_ad9144_dma.s_axi
    {
       datum baseAddress
       {
-         value = "287326208";
+         value = "2149711872";
          type = "String";
       }
    }
-   element axi_ad9250_1
-   {
-      datum _sortIndex
-      {
-         value = "17";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element axi_ad9250_1.s_axi
-   {
-      datum baseAddress
-      {
-         value = "287358976";
-         type = "String";
-      }
-   }
-   element axi_dmac_0
+   element axi_ad9680_core
    {
       datum _sortIndex
       {
          value = "16";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
    }
-   element axi_dmac_0.s_axi
+   element axi_ad9680_core.s_axi
    {
       datum baseAddress
       {
-         value = "287342592";
+         value = "2149646336";
          type = "String";
       }
    }
-   element axi_dmac_1
+   element axi_ad9680_dma
    {
       datum _sortIndex
       {
-         value = "18";
+         value = "14";
          type = "int";
       }
       datum sopceditor_expanded
@@ -93,11 +83,11 @@
          type = "boolean";
       }
    }
-   element axi_dmac_1.s_axi
+   element axi_ad9680_dma.s_axi
    {
       datum baseAddress
       {
-         value = "287309824";
+         value = "2149728256";
          type = "String";
       }
    }
@@ -113,7 +103,7 @@
    {
       datum _sortIndex
       {
-         value = "2";
+         value = "1";
          type = "int";
       }
       datum sopceditor_expanded
@@ -126,7 +116,7 @@
    {
       datum baseAddress
       {
-         value = "287381504";
+         value = "2149750784";
          type = "String";
       }
    }
@@ -134,7 +124,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "4";
          type = "int";
       }
    }
@@ -146,32 +136,11 @@
          type = "String";
       }
    }
-   element sys_ddr3_dmaconnect
-   {
-      datum _sortIndex
-      {
-         value = "14";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_ddr3_dmaconnect.s0
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
    element sys_ethernet
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "5";
          type = "int";
       }
       datum sopceditor_expanded
@@ -184,7 +153,7 @@
    {
       datum baseAddress
       {
-         value = "287383552";
+         value = "2149752832";
          type = "String";
       }
    }
@@ -192,7 +161,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "6";
          type = "int";
       }
    }
@@ -200,7 +169,7 @@
    {
       datum baseAddress
       {
-         value = "287384704";
+         value = "2149753984";
          type = "String";
       }
    }
@@ -208,7 +177,7 @@
    {
       datum baseAddress
       {
-         value = "287384672";
+         value = "2149753952";
          type = "String";
       }
    }
@@ -216,7 +185,7 @@
    {
       datum baseAddress
       {
-         value = "287384784";
+         value = "2149754080";
          type = "String";
       }
    }
@@ -224,7 +193,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "7";
          type = "int";
       }
    }
@@ -232,7 +201,7 @@
    {
       datum baseAddress
       {
-         value = "287384736";
+         value = "2149754016";
          type = "String";
       }
    }
@@ -240,7 +209,7 @@
    {
       datum baseAddress
       {
-         value = "287384640";
+         value = "2149753920";
          type = "String";
       }
    }
@@ -251,21 +220,16 @@
          value = "12";
          type = "int";
       }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
    }
    element sys_gpio.s1
    {
       datum baseAddress
       {
-         value = "287384768";
+         value = "2149754048";
          type = "String";
       }
    }
-   element sys_id
+   element sys_gpio_bd
    {
       datum _sortIndex
       {
@@ -278,11 +242,32 @@
          type = "boolean";
       }
    }
+   element sys_gpio_bd.s1
+   {
+      datum baseAddress
+      {
+         value = "2149754064";
+         type = "String";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
    element sys_id.control_slave
    {
       datum baseAddress
       {
-         value = "287384792";
+         value = "2149754088";
          type = "String";
       }
    }
@@ -290,7 +275,7 @@
    {
       datum _sortIndex
       {
-         value = "3";
+         value = "2";
          type = "int";
       }
       datum sopceditor_expanded
@@ -308,7 +293,7 @@
       }
       datum baseAddress
       {
-         value = "285212672";
+         value = "2147483648";
          type = "String";
       }
    }
@@ -321,94 +306,10 @@
       }
       datum baseAddress
       {
-         value = "285212672";
+         value = "2147483648";
          type = "String";
       }
    }
-   element sys_jesd204b_s1
-   {
-      datum _sortIndex
-      {
-         value = "23";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_jesd204b_s1.jesd204_rx_avs
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element sys_jesd204b_s1_connect
-   {
-      datum _sortIndex
-      {
-         value = "22";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_jesd204b_s1_connect.s0
-   {
-      datum baseAddress
-      {
-         value = "268435456";
-         type = "String";
-      }
-   }
-   element sys_jesd204b_s1_pll
-   {
-      datum _sortIndex
-      {
-         value = "20";
-         type = "int";
-      }
-   }
-   element sys_jesd204b_s1_ref_clk
-   {
-      datum _sortIndex
-      {
-         value = "19";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_jesd204b_s1_rx_clk
-   {
-      datum _sortIndex
-      {
-         value = "21";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_pll
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
    element sys_spi
    {
       datum _sortIndex
@@ -426,7 +327,7 @@
    {
       datum baseAddress
       {
-         value = "287384576";
+         value = "2149753856";
          type = "String";
       }
    }
@@ -434,7 +335,7 @@
    {
       datum _sortIndex
       {
-         value = "4";
+         value = "3";
          type = "int";
       }
    }
@@ -442,7 +343,7 @@
    {
       datum baseAddress
       {
-         value = "287375360";
+         value = "2149744640";
          type = "String";
       }
    }
@@ -450,32 +351,11 @@
    {
       datum baseAddress
       {
-         value = "287375360";
+         value = "2149744640";
          type = "String";
       }
    }
    element sys_timer
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_timer.s1
-   {
-      datum baseAddress
-      {
-         value = "287384608";
-         type = "String";
-      }
-   }
-   element sys_uart
    {
       datum _sortIndex
       {
@@ -488,11 +368,104 @@
          type = "boolean";
       }
    }
+   element sys_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "2149753888";
+         type = "String";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
    element sys_uart.avalon_jtag_slave
    {
       datum baseAddress
       {
-         value = "287384800";
+         value = "2149754096";
+         type = "String";
+      }
+   }
+   element sys_xcvr
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element sys_xcvr.jesd204_rx_avs
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_xcvr_rstcntrl
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element sys_xcvr_rx_clk
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element sys_xcvr_rx_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element sys_xcvr_tx_clk
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element sys_xcvr_tx_pll
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element sys_xcvr_tx_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
          type = "String";
       }
    }
@@ -516,83 +489,10 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
- <interface
-   name="axi_ad9250_0_adc_clock"
-   internal="axi_ad9250_0.adc_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="axi_ad9250_0_adc_dma_if"
-   internal="axi_ad9250_0.adc_dma_if"
-   type="conduit"
-   dir="end" />
- <interface name="axi_ad9250_0_adc_mon_if" internal="axi_ad9250_0.adc_mon_if" />
- <interface
-   name="axi_ad9250_0_xcvr_clk"
-   internal="axi_ad9250_0.xcvr_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9250_0_xcvr_data"
-   internal="axi_ad9250_0.xcvr_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_ad9250_1_adc_clock"
-   internal="axi_ad9250_1.adc_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="axi_ad9250_1_adc_dma_if"
-   internal="axi_ad9250_1.adc_dma_if"
-   type="conduit"
-   dir="end" />
- <interface name="axi_ad9250_1_adc_mon_if" internal="axi_ad9250_1.adc_mon_if" />
- <interface
-   name="axi_ad9250_1_xcvr_clk"
-   internal="axi_ad9250_1.xcvr_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_ad9250_1_xcvr_data"
-   internal="axi_ad9250_1.xcvr_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="axi_dmac_0_fifo_wr_clock"
-   internal="axi_dmac_0.fifo_wr_clock"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_dmac_0_fifo_wr_if"
-   internal="axi_dmac_0.fifo_wr_if"
-   type="conduit"
-   dir="end" />
  <interface
    name="axi_dmac_1_fifo_wr_clock"
-   internal="axi_dmac_1.fifo_wr_clock"
-   type="clock"
-   dir="end" />
- <interface
-   name="axi_dmac_1_fifo_wr_if"
-   internal="axi_dmac_1.fifo_wr_if"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_125m_clk"
-   internal="sys_pll.outclk2"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_25m_clk"
-   internal="sys_pll.outclk3"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_2m5_clk"
-   internal="sys_pll.outclk4"
-   type="clock"
-   dir="start" />
+   internal="axi_ad9144_dma.fifo_wr_clock" />
+ <interface name="axi_dmac_1_fifo_wr_if" internal="axi_ad9144_dma.fifo_wr_if" />
  <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
  <interface
    name="sys_ddr3_cntrl_mem_conduit_end"
@@ -604,6 +504,11 @@
    internal="sys_ddr3_cntrl.oct_conduit_end"
    type="conduit"
    dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_ref_clk"
+   internal="sys_ddr3_cntrl.pll_ref_clk_clock_sink"
+   type="clock"
+   dir="end" />
  <interface
    name="sys_ddr3_cntrl_status_conduit_end"
    internal="sys_ddr3_cntrl.status_conduit_end"
@@ -615,108 +520,35 @@
    type="conduit"
    dir="end" />
  <interface
-   name="sys_ethernet_rgmii"
-   internal="sys_ethernet.mac_rgmii_connection"
-   type="conduit"
+   name="sys_ethernet_ref_clk"
+   internal="sys_ethernet.pcs_ref_clk_clock_connection"
+   type="clock"
    dir="end" />
+ <interface
+   name="sys_ethernet_rgmii"
+   internal="sys_ethernet.mac_rgmii_connection" />
  <interface
    name="sys_ethernet_rx_clk"
-   internal="sys_ethernet.pcs_mac_rx_clock_connection"
-   type="clock"
+   internal="sys_ethernet.pcs_mac_rx_clock_connection" />
+ <interface
+   name="sys_ethernet_sgmii"
+   internal="sys_ethernet.serial_connection"
+   type="conduit"
    dir="end" />
  <interface
    name="sys_ethernet_status"
-   internal="sys_ethernet.mac_status_connection"
-   type="conduit"
-   dir="end" />
+   internal="sys_ethernet.mac_status_connection" />
  <interface
    name="sys_ethernet_tx_clk"
-   internal="sys_ethernet.pcs_mac_tx_clock_connection"
-   type="clock"
-   dir="end" />
+   internal="sys_ethernet.pcs_mac_tx_clock_connection" />
  <interface
    name="sys_gpio"
    internal="sys_gpio.external_connection"
    type="conduit"
    dir="end" />
  <interface
-   name="sys_jesd204b_s1_lane_aligned"
-   internal="sys_jesd204b_s1.dev_lane_aligned"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_lane_aligned_all"
-   internal="sys_jesd204b_s1.alldev_lane_aligned"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_locked"
-   internal="sys_jesd204b_s1.rx_islockedtodata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_pll_locked"
-   internal="sys_jesd204b_s1_pll.locked"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_ref_clk"
-   internal="sys_jesd204b_s1_ref_clk.in_clk"
-   type="clock"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_analogreset"
-   internal="sys_jesd204b_s1.rx_analogreset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_cal_busy"
-   internal="sys_jesd204b_s1.rx_cal_busy"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_clk"
-   internal="sys_jesd204b_s1_rx_clk.out_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="sys_jesd204b_s1_rx_digitalreset"
-   internal="sys_jesd204b_s1.rx_digitalreset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_ferr"
-   internal="sys_jesd204b_s1.jesd204_rx_frame_error"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_link"
-   internal="sys_jesd204b_s1.jesd204_rx_link"
-   type="avalon_streaming"
-   dir="start" />
- <interface
-   name="sys_jesd204b_s1_rx_sof"
-   internal="sys_jesd204b_s1.sof"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_rx_xcvr_data"
-   internal="sys_jesd204b_s1.rx_serial_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_sync_n"
-   internal="sys_jesd204b_s1.dev_sync_n"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_jesd204b_s1_sysref"
-   internal="sys_jesd204b_s1.sysref"
-   type="conduit"
-   dir="end" />
- <interface
-   name="sys_pll_locked"
-   internal="sys_pll.locked"
+   name="sys_gpio_bd"
+   internal="sys_gpio_bd.external_connection"
    type="conduit"
    dir="end" />
  <interface
@@ -725,17 +557,90 @@
    type="reset"
    dir="end" />
  <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="axi_ad9250_0" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="PCORE_AXI_ID_WIDTH" value="5" />
-  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+ <interface
+   name="sys_xcvr_rx_data"
+   internal="sys_xcvr.jesd204_rx_link"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="sys_xcvr_rx_ferr"
+   internal="sys_xcvr.jesd204_rx_frame_error"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_rx_ref_clk"
+   internal="sys_xcvr_rx_ref_clk.clk_in"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_xcvr_rx_sof"
+   internal="sys_xcvr.rx_sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_rx_sync_n"
+   internal="sys_xcvr.rx_dev_sync_n"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_rx_sysref"
+   internal="sys_xcvr.rx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_rxd"
+   internal="sys_xcvr.rx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_tx_data"
+   internal="sys_xcvr.jesd204_tx_link"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="sys_xcvr_tx_ref_clk"
+   internal="sys_xcvr_tx_ref_clk.clk_in"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_xcvr_tx_sync_n"
+   internal="sys_xcvr.sync_n"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_tx_sysref"
+   internal="sys_xcvr.tx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_xcvr_txd"
+   internal="sys_xcvr.tx_serial_data"
+   type="conduit"
+   dir="end" />
+ <module name="axi_ad9144_core" kind="axi_ad9144" version="1.0" enabled="1">
   <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_QUAD_DUAL_N" value="0" />
  </module>
- <module name="axi_ad9250_1" kind="axi_ad9250" version="1.0" enabled="1">
-  <parameter name="PCORE_AXI_ID_WIDTH" value="5" />
-  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+ <module name="axi_ad9144_dma" kind="axi_dmac" version="1.0" enabled="1">
+  <parameter name="C_2D_TRANSFER" value="1" />
+  <parameter name="C_AXI_SLICE_DEST" value="0" />
+  <parameter name="C_AXI_SLICE_SRC" value="0" />
+  <parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
+  <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
+  <parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
+  <parameter name="C_CYCLIC" value="1" />
+  <parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="C_DMA_LENGTH_WIDTH" value="14" />
+  <parameter name="C_DMA_TYPE_DEST" value="2" />
+  <parameter name="C_DMA_TYPE_SRC" value="0" />
+  <parameter name="C_SYNC_TRANSFER_START" value="0" />
   <parameter name="PCORE_ID" value="1" />
  </module>
- <module name="axi_dmac_0" kind="axi_dmac" version="1.0" enabled="1">
+ <module name="axi_ad9680_core" kind="axi_ad9680" version="1.0" enabled="1">
+  <parameter name="PCORE_ID" value="0" />
+ </module>
+ <module name="axi_ad9680_dma" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="C_2D_TRANSFER" value="1" />
   <parameter name="C_AXI_SLICE_DEST" value="0" />
   <parameter name="C_AXI_SLICE_SRC" value="0" />
@@ -751,31 +656,15 @@
   <parameter name="C_SYNC_TRANSFER_START" value="0" />
   <parameter name="PCORE_ID" value="0" />
  </module>
- <module name="axi_dmac_1" kind="axi_dmac" version="1.0" enabled="1">
-  <parameter name="C_2D_TRANSFER" value="1" />
-  <parameter name="C_AXI_SLICE_DEST" value="0" />
-  <parameter name="C_AXI_SLICE_SRC" value="0" />
-  <parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
-  <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
-  <parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
-  <parameter name="C_CYCLIC" value="1" />
-  <parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
-  <parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="C_DMA_LENGTH_WIDTH" value="14" />
-  <parameter name="C_DMA_TYPE_DEST" value="0" />
-  <parameter name="C_DMA_TYPE_SRC" value="2" />
-  <parameter name="C_SYNC_TRANSFER_START" value="0" />
-  <parameter name="PCORE_ID" value="1" />
- </module>
  <module name="sys_clk" kind="clock_source" version="14.1" enabled="1">
-  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequency" value="100000000" />
   <parameter name="clockFrequencyKnown" value="true" />
   <parameter name="inputClockFrequency" value="0" />
   <parameter name="resetSynchronousEdges" value="NONE" />
  </module>
  <module name="sys_cpu" kind="altera_nios2_gen2" version="14.1" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="19" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="19" />
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="bht_ramBlockType" value="Automatic" />
@@ -790,10 +679,10 @@
   <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
   <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
   <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataAddrWidth" value="32" />
   <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_avalon_slave_0' start='0x0' end='0x10000000' /><slave name='sys_jesd204b_s1.jesd204_rx_avs' start='0x10000000' end='0x10000400' /><slave name='sys_int_mem.s1' start='0x11000000' end='0x11180000' /><slave name='axi_dmac_1.s_axi' start='0x11200000' end='0x11204000' /><slave name='axi_ad9250_0.s_axi' start='0x11204000' end='0x11208000' /><slave name='axi_dmac_0.s_axi' start='0x11208000' end='0x1120C000' /><slave name='axi_ad9250_1.s_axi' start='0x1120C000' end='0x11210000' /><slave name='sys_cpu.debug_mem_slave' start='0x11211800' end='0x11212000' /><slave name='sys_ethernet.control_port' start='0x11212000' end='0x11212400' /><slave name='sys_spi.spi_control_port' start='0x11212400' end='0x11212420' /><slave name='sys_timer.s1' start='0x11212420' end='0x11212440' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x11212440' end='0x11212460' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x11212460' end='0x11212480' /><slave name='sys_ethernet_dma_rx.csr' start='0x11212480' end='0x112124A0' /><slave name='sys_ethernet_dma_tx.csr' start='0x112124A0' end='0x112124C0' /><slave name='sys_gpio.s1' start='0x112124C0' end='0x112124D0' /><slave name='sys_ethernet_dma_rx.response' start='0x112124D0' end='0x112124D8' /><slave name='sys_id.control_slave' start='0x112124D8' end='0x112124E0' /><slave name='sys_uart.avalon_jtag_slave' start='0x112124E0' end='0x112124E8' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_avalon_slave_0' start='0x0' end='0x80000000' /><slave name='sys_int_mem.s1' start='0x80000000' end='0x80180000' /><slave name='axi_ad9144_core.s_axi' start='0x80200000' end='0x80210000' /><slave name='axi_ad9680_core.s_axi' start='0x80210000' end='0x80220000' /><slave name='axi_ad9144_dma.s_axi' start='0x80220000' end='0x80224000' /><slave name='axi_ad9680_dma.s_axi' start='0x80224000' end='0x80228000' /><slave name='sys_cpu.debug_mem_slave' start='0x80229800' end='0x8022A000' /><slave name='sys_ethernet.control_port' start='0x8022A000' end='0x8022A400' /><slave name='sys_spi.spi_control_port' start='0x8022A400' end='0x8022A420' /><slave name='sys_timer.s1' start='0x8022A420' end='0x8022A440' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x8022A440' end='0x8022A460' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x8022A460' end='0x8022A480' /><slave name='sys_ethernet_dma_rx.csr' start='0x8022A480' end='0x8022A4A0' /><slave name='sys_ethernet_dma_tx.csr' start='0x8022A4A0' end='0x8022A4C0' /><slave name='sys_gpio.s1' start='0x8022A4C0' end='0x8022A4D0' /><slave name='sys_gpio_bd.s1' start='0x8022A4D0' end='0x8022A4E0' /><slave name='sys_ethernet_dma_rx.response' start='0x8022A4E0' end='0x8022A4E8' /><slave name='sys_id.control_slave' start='0x8022A4E8' end='0x8022A4F0' /><slave name='sys_uart.avalon_jtag_slave' start='0x8022A4F0' end='0x8022A4F8' /></address-map>]]></parameter>
   <parameter name="data_master_high_performance_paddr_base" value="0" />
   <parameter name="data_master_high_performance_paddr_size" value="0" />
   <parameter name="data_master_paddr_base" value="0" />
@@ -831,22 +720,22 @@
   <parameter name="icache_size" value="32768" />
   <parameter name="icache_tagramBlockType" value="Automatic" />
   <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_avalon_slave_0' start='0x0' end='0x10000000' /><slave name='sys_int_mem.s2' start='0x11000000' end='0x11180000' /><slave name='sys_cpu.debug_mem_slave' start='0x11211800' end='0x11212000' /></address-map>]]></parameter>
+  <parameter name="instAddrWidth" value="32" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_avalon_slave_0' start='0x0' end='0x80000000' /><slave name='sys_int_mem.s2' start='0x80000000' end='0x80180000' /><slave name='sys_cpu.debug_mem_slave' start='0x80229800' end='0x8022A000' /></address-map>]]></parameter>
   <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="instructionMasterHighPerformanceMapParam" value="" />
   <parameter name="instruction_master_high_performance_paddr_base" value="0" />
   <parameter name="instruction_master_high_performance_paddr_size" value="0" />
   <parameter name="instruction_master_paddr_base" value="0" />
   <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="255" />
+  <parameter name="internalIrqMaskSystemInfo" value="511" />
   <parameter name="io_regionbase" value="0" />
   <parameter name="io_regionsize" value="0" />
   <parameter name="master_addr_map" value="false" />
   <parameter name="mmu_TLBMissExcOffset" value="4096" />
   <parameter name="mmu_TLBMissExcSlave" value="sys_int_mem.s2" />
   <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="true" />
+  <parameter name="mmu_enabled" value="false" />
   <parameter name="mmu_processIDNumBits" value="8" />
   <parameter name="mmu_ramBlockType" value="Automatic" />
   <parameter name="mmu_tlbNumWays" value="16" />
@@ -910,19 +799,19 @@
   <parameter name="setting_shadowRegisterSets" value="0" />
   <parameter name="setting_showInternalSettings" value="false" />
   <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter name="setting_support31bitdcachebypass" value="false" />
   <parameter name="setting_usedesignware" value="false" />
   <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x11210000' end='0x11211000' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="32" />
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x80228000' end='0x80229000' /></address-map>]]></parameter>
   <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
   <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
   <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x11210000' end='0x11211000' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="32" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x80228000' end='0x80229000' /></address-map>]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
   <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
@@ -1180,9 +1069,9 @@
   <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="11" />
   <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
   <parameter name="MEM_DDR3_DLL_EN" value="true" />
-  <parameter name="MEM_DDR3_DM_EN" value="false" />
-  <parameter name="MEM_DDR3_DQ_PER_DQS" value="4" />
-  <parameter name="MEM_DDR3_DQ_WIDTH" value="8" />
+  <parameter name="MEM_DDR3_DM_EN" value="true" />
+  <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DDR3_DQ_WIDTH" value="64" />
   <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
   <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_DISCRETE" />
   <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="0x0" />
@@ -1457,9 +1346,9 @@
   <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
   <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
   <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="true" />
   <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="400.0" />
+  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="533.0" />
   <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
   <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
   <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
@@ -1471,7 +1360,7 @@
   <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
   <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
   <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="50.0" />
+  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="100.0" />
   <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
   <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
   <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
@@ -1575,30 +1464,10 @@
   <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
  </module>
- <module
-   name="sys_ddr3_dmaconnect"
-   kind="altera_avalon_mm_clock_crossing_bridge"
-   version="14.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="31" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="COMMAND_FIFO_DEPTH" value="4" />
-  <parameter name="DATA_WIDTH" value="512" />
-  <parameter name="MASTER_SYNC_DEPTH" value="2" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="RESPONSE_FIFO_DEPTH" value="4" />
-  <parameter name="SLAVE_SYNC_DEPTH" value="2" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
- </module>
  <module name="sys_ethernet" kind="altera_eth_tse" version="14.1" enabled="1">
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="core_variation" value="MAC_PCS" />
   <parameter name="deviceFamilyName" value="Arria 10" />
   <parameter name="eg_addr" value="11" />
   <parameter name="ena_hash" value="false" />
@@ -1606,7 +1475,7 @@
   <parameter name="enable_ecc" value="false" />
   <parameter name="enable_ena" value="32" />
   <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_hd_logic" value="false" />
   <parameter name="enable_mac_flow_ctrl" value="true" />
   <parameter name="enable_mac_vlan" value="false" />
   <parameter name="enable_magic_detect" value="true" />
@@ -1618,7 +1487,7 @@
   <parameter name="enable_use_internal_fifo" value="true" />
   <parameter name="export_pwrdn" value="false" />
   <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="ifGMII" value="MII_GMII" />
   <parameter name="ing_addr" value="11" />
   <parameter name="max_channels" value="1" />
   <parameter name="mdio_clk_div" value="30" />
@@ -1630,7 +1499,7 @@
   <parameter name="phyip_pma_bonding_mode" value="x1" />
   <parameter name="starting_channel_number" value="0" />
   <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="transceiver_type" value="LVDS_IO" />
   <parameter name="tstamp_fp_width" value="4" />
   <parameter name="useMDIO" value="true" />
   <parameter name="use_misc_ports" value="true" />
@@ -1705,6 +1574,24 @@
   <parameter name="simDrivenValue" value="0" />
   <parameter name="width" value="32" />
  </module>
+ <module
+   name="sys_gpio_bd"
+   kind="altera_avalon_pio"
+   version="14.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
  <module
    name="sys_id"
    kind="altera_avalon_sysid_qsys"
@@ -1743,11 +1630,86 @@
   <parameter name="useShallowMemBlocks" value="false" />
   <parameter name="writable" value="true" />
  </module>
+ <module name="sys_spi" kind="altera_avalon_spi" version="14.1" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="100000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="8" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="128000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
  <module
-   name="sys_jesd204b_s1"
-   kind="altera_jesd204"
+   name="sys_tcm_mem"
+   kind="altera_avalon_onchip_memory2"
    version="14.1"
    enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Arria 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="4096" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   name="sys_timer"
+   kind="altera_avalon_timer"
+   version="14.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+ </module>
+ <module
+   name="sys_uart"
+   kind="altera_avalon_jtag_uart"
+   version="14.1"
+   enabled="1">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clkFreq" value="100000000" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module name="sys_xcvr" kind="altera_jesd204" version="14.1" enabled="1">
   <parameter name="ADJCNT" value="0" />
   <parameter name="ADJDIR" value="0" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
@@ -1755,12 +1717,12 @@
   <parameter name="BID" value="0" />
   <parameter name="CF" value="0" />
   <parameter name="CS" value="0" />
-  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="DATA_PATH" value="RX_TX" />
   <parameter name="DEVICE_FAMILY" value="Arria 10" />
   <parameter name="DID" value="0" />
   <parameter name="DLB_TEST" value="0" />
   <parameter name="ECC_EN" value="0" />
-  <parameter name="HD" value="0" />
+  <parameter name="HD" value="1" />
   <parameter name="JESDV" value="1" />
   <parameter name="K" value="32" />
   <parameter name="L" value="4" />
@@ -1772,13 +1734,13 @@
   <parameter name="LID5" value="5" />
   <parameter name="LID6" value="6" />
   <parameter name="LID7" value="7" />
-  <parameter name="M" value="4" />
+  <parameter name="M" value="2" />
   <parameter name="N" value="16" />
   <parameter name="N_PRIME" value="16" />
   <parameter name="OPTIMIZE" value="0" />
-  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG2" />
   <parameter name="PHADJ" value="0" />
-  <parameter name="REFCLK_FREQ" value="250.0" />
+  <parameter name="REFCLK_FREQ" value="500.0" />
   <parameter name="RES1" value="0" />
   <parameter name="RES2" value="0" />
   <parameter name="S" value="1" />
@@ -1787,8 +1749,8 @@
   <parameter name="TERMINATE_RECONFIG_EN" value="false" />
   <parameter name="TEST_COMPONENTS_EN" value="false" />
   <parameter name="bitrev_en" value="false" />
-  <parameter name="bonded_mode" value="bonded" />
-  <parameter name="lane_rate" value="5000.0" />
+  <parameter name="bonded_mode" value="non_bonded" />
+  <parameter name="lane_rate" value="10000.0" />
   <parameter name="part_trait_bd" value="NIGHTFURY5ES2" />
   <parameter name="part_trait_dp" value="10AX115S3F45I2SGE2" />
   <parameter name="pll_reconfig_enable" value="false" />
@@ -1798,30 +1760,33 @@
   <parameter name="wrapper_opt" value="base_phy" />
  </module>
  <module
-   name="sys_jesd204b_s1_connect"
-   kind="altera_avalon_mm_clock_crossing_bridge"
+   name="sys_xcvr_rstcntrl"
+   kind="altera_xcvr_reset_control"
    version="14.1"
    enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="10" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="COMMAND_FIFO_DEPTH" value="4" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="MASTER_SYNC_DEPTH" value="2" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="RESPONSE_FIFO_DEPTH" value="4" />
-  <parameter name="SLAVE_SYNC_DEPTH" value="2" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="CHANNELS" value="4" />
+  <parameter name="PLLS" value="1" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
+  <parameter name="RX_ENABLE" value="1" />
+  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+  <parameter name="SYNCHRONIZE_RESET" value="1" />
+  <parameter name="SYS_CLK_IN_MHZ" value="100" />
+  <parameter name="TX_ENABLE" value="1" />
+  <parameter name="TX_PER_CHANNEL" value="0" />
+  <parameter name="TX_PLL_ENABLE" value="1" />
+  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_POWERDOWN" value="1000" />
+  <parameter name="T_RX_ANALOGRESET" value="40" />
+  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_DIGITALRESET" value="20" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_pll_cal_busy" value="0" />
+  <parameter name="gui_rx_auto_reset" value="0" />
+  <parameter name="gui_split_interfaces" value="0" />
+  <parameter name="gui_tx_auto_reset" value="0" />
  </module>
- <module
-   name="sys_jesd204b_s1_pll"
-   kind="altera_iopll"
-   version="14.1"
-   enabled="1">
+ <module name="sys_xcvr_rx_clk" kind="altera_iopll" version="14.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
   <parameter name="gui_actual_duty_cycle0" value="50.0" />
   <parameter name="gui_actual_duty_cycle1" value="50.0" />
@@ -2014,7 +1979,7 @@
   <parameter name="gui_multiply_factor" value="6" />
   <parameter name="gui_number_of_clocks" value="1" />
   <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="100.0" />
+  <parameter name="gui_output_clock_frequency0" value="250.0" />
   <parameter name="gui_output_clock_frequency1" value="100.0" />
   <parameter name="gui_output_clock_frequency10" value="100.0" />
   <parameter name="gui_output_clock_frequency11" value="100.0" />
@@ -2093,7 +2058,7 @@
   <parameter name="gui_ps_units9" value="ps" />
   <parameter name="gui_refclk1_frequency" value="100.0" />
   <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="100.0" />
+  <parameter name="gui_reference_clock_frequency" value="500.0" />
   <parameter name="gui_switchover_delay" value="0" />
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
   <parameter name="gui_use_locked" value="true" />
@@ -2103,24 +2068,16 @@
   <parameter name="system_part_trait_speed_grade" value="2" />
  </module>
  <module
-   name="sys_jesd204b_s1_ref_clk"
-   kind="altera_clock_bridge"
+   name="sys_xcvr_rx_ref_clk"
+   kind="clock_source"
    version="14.1"
    enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="0" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+  <parameter name="clockFrequency" value="500000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
  </module>
- <module
-   name="sys_jesd204b_s1_rx_clk"
-   kind="altera_clock_bridge"
-   version="14.1"
-   enabled="1">
-  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
-  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
-  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
- <module name="sys_pll" kind="altera_iopll" version="14.1" enabled="1">
+ <module name="sys_xcvr_tx_clk" kind="altera_iopll" version="14.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
   <parameter name="gui_actual_duty_cycle0" value="50.0" />
   <parameter name="gui_actual_duty_cycle1" value="50.0" />
@@ -2311,10 +2268,10 @@
   <parameter name="gui_fractional_cout" value="32" />
   <parameter name="gui_mif_generate" value="false" />
   <parameter name="gui_multiply_factor" value="6" />
-  <parameter name="gui_number_of_clocks" value="5" />
+  <parameter name="gui_number_of_clocks" value="1" />
   <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_output_clock_frequency1" value="166.0" />
+  <parameter name="gui_output_clock_frequency0" value="250.0" />
+  <parameter name="gui_output_clock_frequency1" value="100.0" />
   <parameter name="gui_output_clock_frequency10" value="100.0" />
   <parameter name="gui_output_clock_frequency11" value="100.0" />
   <parameter name="gui_output_clock_frequency12" value="100.0" />
@@ -2323,9 +2280,9 @@
   <parameter name="gui_output_clock_frequency15" value="100.0" />
   <parameter name="gui_output_clock_frequency16" value="100.0" />
   <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_output_clock_frequency2" value="125.0" />
-  <parameter name="gui_output_clock_frequency3" value="25.0" />
-  <parameter name="gui_output_clock_frequency4" value="2.5" />
+  <parameter name="gui_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
   <parameter name="gui_output_clock_frequency5" value="100.0" />
   <parameter name="gui_output_clock_frequency6" value="100.0" />
   <parameter name="gui_output_clock_frequency7" value="100.0" />
@@ -2392,7 +2349,7 @@
   <parameter name="gui_ps_units9" value="ps" />
   <parameter name="gui_refclk1_frequency" value="100.0" />
   <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_reference_clock_frequency" value="100.0" />
+  <parameter name="gui_reference_clock_frequency" value="500.0" />
   <parameter name="gui_switchover_delay" value="0" />
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
   <parameter name="gui_use_locked" value="true" />
@@ -2401,84 +2358,79 @@
   <parameter name="system_info_device_speed_grade" value="2" />
   <parameter name="system_part_trait_speed_grade" value="2" />
  </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="14.1" enabled="1">
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clockPhase" value="0" />
-  <parameter name="clockPolarity" value="0" />
-  <parameter name="dataWidth" value="8" />
-  <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="100000000" />
-  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
-  <parameter name="insertSync" value="false" />
-  <parameter name="lsbOrderedFirst" value="false" />
-  <parameter name="masterSPI" value="true" />
-  <parameter name="numberOfSlaves" value="1" />
-  <parameter name="syncRegDepth" value="2" />
-  <parameter name="targetClockRate" value="128000" />
-  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
- </module>
  <module
-   name="sys_tcm_mem"
-   kind="altera_avalon_onchip_memory2"
+   name="sys_xcvr_tx_pll"
+   kind="altera_xcvr_atx_pll_a10"
    version="14.1"
    enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="dualPort" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="4096" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
+  <parameter name="base_device" value="NIGHTFURY5ES2" />
+  <parameter name="bw_sel" value="medium" />
+  <parameter name="device" value="10AX115S3F45I2SGE2" />
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="enable_16G_path" value="0" />
+  <parameter name="enable_8G_path" value="1" />
+  <parameter name="enable_bonding_clks" value="0" />
+  <parameter name="enable_cascade_out" value="0" />
+  <parameter name="enable_debug_ports_parameters" value="0" />
+  <parameter name="enable_fb_comp_bonding" value="0" />
+  <parameter name="enable_fractional" value="0" />
+  <parameter name="enable_hfreq_clk" value="0" />
+  <parameter name="enable_hip_cal_done_port" value="0" />
+  <parameter name="enable_mcgb" value="0" />
+  <parameter name="enable_mcgb_pcie_clksw" value="0" />
+  <parameter name="enable_pcie_clk" value="0" />
+  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+  <parameter name="enable_pll_reconfig" value="0" />
+  <parameter name="generate_add_hdl_instance_example" value="0" />
+  <parameter name="generate_docs" value="1" />
+  <parameter name="mcgb_aux_clkin_cnt" value="0" />
+  <parameter name="mcgb_div" value="1" />
+  <parameter name="message_level" value="error" />
+  <parameter name="pma_width" value="64" />
+  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+  <parameter name="prot_mode" value="Basic" />
+  <parameter name="rcfg_debug" value="0" />
+  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+  <parameter name="rcfg_h_file_enable" value="0" />
+  <parameter name="rcfg_jtag_enable" value="0" />
+  <parameter name="rcfg_mif_file_enable" value="0" />
+  <parameter name="rcfg_multi_enable" value="0" />
+  <parameter name="rcfg_param_vals1" value="" />
+  <parameter name="rcfg_param_vals2" value="" />
+  <parameter name="rcfg_profile_cnt" value="2" />
+  <parameter name="rcfg_profile_select" value="1" />
+  <parameter name="rcfg_sv_file_enable" value="0" />
+  <parameter name="rcfg_txt_file_enable" value="0" />
+  <parameter name="refclk_cnt" value="1" />
+  <parameter name="refclk_index" value="0" />
+  <parameter name="select_manual_config" value="0" />
+  <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+  <parameter name="set_auto_reference_clock_frequency" value="500.0" />
+  <parameter name="set_capability_reg_enable" value="0" />
+  <parameter name="set_csr_soft_logic_enable" value="0" />
+  <parameter name="set_fref_clock_frequency" value="100.0" />
+  <parameter name="set_hip_cal_en" value="0" />
+  <parameter name="set_k_counter" value="1" />
+  <parameter name="set_l_counter" value="2" />
+  <parameter name="set_m_counter" value="1" />
+  <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+  <parameter name="set_output_clock_frequency" value="5000.0" />
+  <parameter name="set_ref_clk_div" value="1" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="silicon_rev" value="false" />
+  <parameter name="support_mode" value="user_mode" />
+  <parameter name="test_mode" value="0" />
  </module>
  <module
-   name="sys_timer"
-   kind="altera_avalon_timer"
+   name="sys_xcvr_tx_ref_clk"
+   kind="clock_source"
    version="14.1"
    enabled="1">
-  <parameter name="alwaysRun" value="false" />
-  <parameter name="counterSize" value="32" />
-  <parameter name="fixedPeriod" value="false" />
-  <parameter name="period" value="1" />
-  <parameter name="periodUnits" value="MSEC" />
-  <parameter name="resetOutput" value="false" />
-  <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="100000000" />
-  <parameter name="timeoutPulseOutput" value="false" />
- </module>
- <module
-   name="sys_uart"
-   kind="altera_avalon_jtag_uart"
-   version="14.1"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="false" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="100000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
+  <parameter name="clockFrequency" value="500000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
  </module>
  <connection
    kind="avalon"
@@ -2486,7 +2438,7 @@
    start="sys_cpu.data_master"
    end="sys_uart.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x112124e0" />
+  <parameter name="baseAddress" value="0x8022a4f0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2495,7 +2447,7 @@
    start="sys_cpu.data_master"
    end="sys_ethernet.control_port">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11212000" />
+  <parameter name="baseAddress" value="0x8022a000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2504,7 +2456,7 @@
    start="sys_cpu.data_master"
    end="sys_id.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x112124d8" />
+  <parameter name="baseAddress" value="0x8022a4e8" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2513,7 +2465,7 @@
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_tx.csr">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x112124a0" />
+  <parameter name="baseAddress" value="0x8022a4a0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2522,7 +2474,7 @@
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.csr">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11212480" />
+  <parameter name="baseAddress" value="0x8022a480" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2540,7 +2492,7 @@
    start="sys_cpu.data_master"
    end="sys_cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11211800" />
+  <parameter name="baseAddress" value="0x80229800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2549,7 +2501,7 @@
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.descriptor_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11212460" />
+  <parameter name="baseAddress" value="0x8022a460" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2558,7 +2510,7 @@
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_tx.descriptor_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11212440" />
+  <parameter name="baseAddress" value="0x8022a440" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2567,16 +2519,7 @@
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.response">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x112124d0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="sys_cpu.data_master"
-   end="sys_jesd204b_s1_connect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="baseAddress" value="0x8022a4e0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2585,16 +2528,16 @@
    start="sys_cpu.data_master"
    end="sys_int_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11000000" />
+  <parameter name="baseAddress" value="0x80000000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="14.1"
    start="sys_cpu.data_master"
-   end="sys_gpio.s1">
+   end="sys_gpio_bd.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x112124c0" />
+  <parameter name="baseAddress" value="0x8022a4d0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2603,43 +2546,52 @@
    start="sys_cpu.data_master"
    end="sys_timer.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11212420" />
+  <parameter name="baseAddress" value="0x8022a420" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="14.1"
    start="sys_cpu.data_master"
-   end="axi_ad9250_1.s_axi">
+   end="sys_gpio.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x1120c000" />
+  <parameter name="baseAddress" value="0x8022a4c0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="14.1"
    start="sys_cpu.data_master"
-   end="axi_dmac_0.s_axi">
+   end="axi_ad9680_dma.s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11208000" />
+  <parameter name="baseAddress" value="0x80224000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="14.1"
    start="sys_cpu.data_master"
-   end="axi_ad9250_0.s_axi">
+   end="axi_ad9144_dma.s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11204000" />
+  <parameter name="baseAddress" value="0x80220000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="14.1"
    start="sys_cpu.data_master"
-   end="axi_dmac_1.s_axi">
+   end="axi_ad9680_core.s_axi">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11200000" />
+  <parameter name="baseAddress" value="0x80210000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.1"
+   start="sys_cpu.data_master"
+   end="axi_ad9144_core.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x80200000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2648,7 +2600,7 @@
    start="sys_cpu.data_master"
    end="sys_spi.spi_control_port">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11212400" />
+  <parameter name="baseAddress" value="0x8022a400" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2666,7 +2618,7 @@
    start="sys_cpu.instruction_master"
    end="sys_cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11211800" />
+  <parameter name="baseAddress" value="0x80229800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2675,13 +2627,13 @@
    start="sys_cpu.instruction_master"
    end="sys_int_mem.s2">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11000000" />
+  <parameter name="baseAddress" value="0x80000000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="14.1"
-   start="sys_ddr3_dmaconnect.m0"
+   start="axi_ad9680_dma.m_dest_axi"
    end="sys_ddr3_cntrl.ctrl_amm_avalon_slave_0">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
@@ -2690,26 +2642,8 @@
  <connection
    kind="avalon"
    version="14.1"
-   start="sys_jesd204b_s1_connect.m0"
-   end="sys_jesd204b_s1.jesd204_rx_avs">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="axi_dmac_0.m_dest_axi"
-   end="sys_ddr3_dmaconnect.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.1"
-   start="axi_dmac_1.m_dest_axi"
-   end="sys_ddr3_dmaconnect.s0">
+   start="axi_ad9144_dma.m_src_axi"
+   end="sys_ddr3_cntrl.ctrl_amm_avalon_slave_0">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
@@ -2738,7 +2672,7 @@
    start="sys_cpu.tightly_coupled_data_master_0"
    end="sys_tcm_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11210000" />
+  <parameter name="baseAddress" value="0x80228000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2747,7 +2681,7 @@
    start="sys_cpu.tightly_coupled_instruction_master_0"
    end="sys_tcm_mem.s2">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x11210000" />
+  <parameter name="baseAddress" value="0x80228000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -2760,150 +2694,272 @@
    version="14.1"
    start="sys_ethernet_dma_tx.st_source"
    end="sys_ethernet.transmit" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="axi_ad9680_core.adc_clock"
+   end="axi_ad9680_dma.fifo_wr_clock" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_cpu.clk" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_uart.clk" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_timer.clk" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_id.clk" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_gpio.clk" />
+ <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_spi.clk" />
  <connection
    kind="clock"
    version="14.1"
    start="sys_clk.clk"
-   end="sys_ddr3_cntrl.pll_ref_clk_clock_sink" />
- <connection kind="clock" version="14.1" start="sys_clk.clk" end="sys_pll.refclk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_ddr3_cntrl.emif_usr_clk_clock_source"
-   end="sys_ddr3_dmaconnect.m0_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_jesd204b_s1_ref_clk.out_clk"
-   end="sys_jesd204b_s1.pll_ref_clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_jesd204b_s1_ref_clk.out_clk"
-   end="sys_jesd204b_s1_pll.refclk" />
- <connection kind="clock" version="14.1" start="sys_pll.outclk0" end="sys_cpu.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_uart.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_timer.clk" />
- <connection kind="clock" version="14.1" start="sys_pll.outclk0" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_gpio.clk" />
- <connection kind="clock" version="14.1" start="sys_pll.outclk0" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
    end="sys_int_mem.clk1" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
    end="sys_tcm_mem.clk1" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
    end="sys_int_mem.clk2" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
    end="sys_tcm_mem.clk2" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
    end="sys_ethernet_dma_tx.clock" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
+   end="sys_ethernet_dma_rx.clock" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_clk.clk"
+   end="sys_xcvr_rstcntrl.clock" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_clk.clk"
    end="sys_ethernet.control_port_clock_connection" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_jesd204b_s1_pll.outclk0"
-   end="sys_jesd204b_s1_rx_clk.in_clk" />
+   start="sys_clk.clk"
+   end="sys_xcvr.jesd204_rx_avs_clk" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_jesd204b_s1_pll.outclk0"
-   end="sys_jesd204b_s1.jesd204_rx_avs_clk" />
+   start="sys_clk.clk"
+   end="sys_xcvr.jesd204_tx_avs_clk" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_jesd204b_s1_pll.outclk0"
-   end="sys_jesd204b_s1_connect.m0_clk" />
+   start="sys_xcvr_tx_ref_clk.clk"
+   end="sys_xcvr_tx_pll.pll_refclk0" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
-   end="axi_dmac_0.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
-   end="axi_dmac_1.m_dest_axi_clock" />
- <connection
-   kind="clock"
-   version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
    end="sys_ethernet.receive_clock_connection" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_jesd204b_s1_pll.outclk0"
-   end="sys_jesd204b_s1.rxlink_clk" />
+   start="sys_xcvr_tx_ref_clk.clk"
+   end="sys_xcvr_tx_clk.refclk" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_ddr3_dmaconnect.s0_clk" />
+   start="sys_xcvr_rx_ref_clk.clk"
+   end="sys_xcvr_rx_clk.refclk" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
-   end="sys_jesd204b_s1_connect.s0_clk" />
+   start="sys_xcvr_rx_ref_clk.clk"
+   end="sys_xcvr.rx_pll_ref_clk" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk0"
+   start="sys_clk.clk"
+   end="axi_ad9680_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_clk.clk"
+   end="axi_ad9144_dma.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_clk.clk"
+   end="axi_ad9680_core.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_clk.clk"
+   end="axi_ad9144_core.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_clk.clk"
    end="sys_ethernet.transmit_clock_connection" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk1"
-   end="axi_ad9250_0.s_axi_clock" />
+   start="axi_ad9144_core.dac_clock"
+   end="axi_ad9144_dma.fifo_rd_clock" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk1"
-   end="axi_dmac_0.s_axi_clock" />
+   start="sys_ddr3_cntrl.emif_usr_clk_clock_source"
+   end="axi_ad9680_dma.m_dest_axi_clock" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk1"
-   end="axi_ad9250_1.s_axi_clock" />
+   start="sys_ddr3_cntrl.emif_usr_clk_clock_source"
+   end="axi_ad9144_dma.m_src_axi_clock" />
  <connection
    kind="clock"
    version="14.1"
-   start="sys_pll.outclk1"
-   end="axi_dmac_1.s_axi_clock" />
+   start="sys_xcvr_rx_clk.outclk0"
+   end="sys_xcvr.rxlink_clk" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_xcvr_tx_clk.outclk0"
+   end="sys_xcvr.txlink_clk" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_xcvr_tx_clk.outclk0"
+   end="axi_ad9144_core.xcvr_clk" />
+ <connection
+   kind="clock"
+   version="14.1"
+   start="sys_xcvr_rx_clk.outclk0"
+   end="axi_ad9680_core.xcvr_clk" />
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr.dev_lane_aligned"
+   end="sys_xcvr.alldev_lane_aligned">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr_tx_pll.pll_powerdown"
+   end="sys_xcvr_rstcntrl.pll_powerdown">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr.rx_analogreset"
+   end="sys_xcvr_rstcntrl.rx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr.rx_cal_busy"
+   end="sys_xcvr_rstcntrl.rx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr.rx_digitalreset"
+   end="sys_xcvr_rstcntrl.rx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr_rstcntrl.rx_is_lockedtodata"
+   end="sys_xcvr.rx_islockedtodata">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr_rstcntrl.tx_analogreset"
+   end="sys_xcvr.tx_analogreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr_rstcntrl.tx_cal_busy"
+   end="sys_xcvr.tx_cal_busy">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="conduit"
+   version="14.1"
+   start="sys_xcvr.tx_digitalreset"
+   end="sys_xcvr_rstcntrl.tx_digitalreset">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
+ <connection
+   kind="hssi_serial_clock"
+   version="14.1"
+   start="sys_xcvr_tx_pll.tx_serial_clk"
+   end="sys_xcvr.tx_serial_clk0_ch0" />
+ <connection
+   kind="hssi_serial_clock"
+   version="14.1"
+   start="sys_xcvr_tx_pll.tx_serial_clk"
+   end="sys_xcvr.tx_serial_clk0_ch1" />
+ <connection
+   kind="hssi_serial_clock"
+   version="14.1"
+   start="sys_xcvr_tx_pll.tx_serial_clk"
+   end="sys_xcvr.tx_serial_clk0_ch2" />
+ <connection
+   kind="hssi_serial_clock"
+   version="14.1"
+   start="sys_xcvr_tx_pll.tx_serial_clk"
+   end="sys_xcvr.tx_serial_clk0_ch3" />
  <connection
    kind="interrupt"
    version="14.1"
@@ -2922,14 +2978,14 @@
    kind="interrupt"
    version="14.1"
    start="sys_cpu.irq"
-   end="axi_dmac_0.interrupt_sender">
+   end="axi_ad9680_dma.interrupt_sender">
   <parameter name="irqNumber" value="6" />
  </connection>
  <connection
    kind="interrupt"
    version="14.1"
    start="sys_cpu.irq"
-   end="axi_dmac_1.interrupt_sender">
+   end="axi_ad9144_dma.interrupt_sender">
   <parameter name="irqNumber" value="7" />
  </connection>
  <connection
@@ -2953,9 +3009,26 @@
    kind="interrupt"
    version="14.1"
    start="sys_cpu.irq"
-   end="sys_gpio.irq">
+   end="sys_gpio_bd.irq">
   <parameter name="irqNumber" value="5" />
  </connection>
+ <connection
+   kind="interrupt"
+   version="14.1"
+   start="sys_cpu.irq"
+   end="sys_gpio.irq">
+  <parameter name="irqNumber" value="8" />
+ </connection>
+ <connection
+   kind="reset"
+   version="14.1"
+   start="sys_clk.clk_reset"
+   end="sys_xcvr_tx_ref_clk.clk_in_reset" />
+ <connection
+   kind="reset"
+   version="14.1"
+   start="sys_clk.clk_reset"
+   end="sys_xcvr_rx_ref_clk.clk_in_reset" />
  <connection
    kind="reset"
    version="14.1"
@@ -2965,17 +3038,22 @@
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1.jesd204_rx_avs_rst_n" />
+   end="sys_xcvr.jesd204_rx_avs_rst_n" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1_connect.m0_reset" />
+   end="sys_xcvr.jesd204_tx_avs_rst_n" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="axi_dmac_0.m_dest_axi_reset" />
+   end="axi_ad9680_dma.m_dest_axi_reset" />
+ <connection
+   kind="reset"
+   version="14.1"
+   start="sys_clk.clk_reset"
+   end="axi_ad9144_dma.m_src_axi_reset" />
  <connection
    kind="reset"
    version="14.1"
@@ -3000,7 +3078,7 @@
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_gpio.reset" />
+   end="sys_gpio_bd.reset" />
  <connection
    kind="reset"
    version="14.1"
@@ -3010,12 +3088,22 @@
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_pll.reset" />
+   end="sys_gpio.reset" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1_pll.reset" />
+   end="sys_xcvr_rstcntrl.reset" />
+ <connection
+   kind="reset"
+   version="14.1"
+   start="sys_clk.clk_reset"
+   end="sys_xcvr_tx_clk.reset" />
+ <connection
+   kind="reset"
+   version="14.1"
+   start="sys_clk.clk_reset"
+   end="sys_xcvr_rx_clk.reset" />
  <connection
    kind="reset"
    version="14.1"
@@ -3055,37 +3143,32 @@
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1.rxlink_rst_n" />
+   end="sys_xcvr.rxlink_rst_n" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_ddr3_dmaconnect.s0_reset" />
+   end="axi_ad9680_dma.s_axi_reset" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="sys_jesd204b_s1_connect.s0_reset" />
+   end="axi_ad9144_dma.s_axi_reset" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="axi_ad9250_0.s_axi_reset" />
+   end="axi_ad9680_core.s_axi_reset" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="axi_dmac_0.s_axi_reset" />
+   end="axi_ad9144_core.s_axi_reset" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_clk.clk_reset"
-   end="axi_ad9250_1.s_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_clk.clk_reset"
-   end="axi_dmac_1.s_axi_reset" />
+   end="sys_xcvr.txlink_rst_n" />
  <connection
    kind="reset"
    version="14.1"
@@ -3095,17 +3178,12 @@
    kind="reset"
    version="14.1"
    start="sys_ddr3_cntrl.emif_usr_reset_reset_source"
-   end="sys_ddr3_dmaconnect.m0_reset" />
+   end="axi_ad9680_dma.m_dest_axi_reset" />
  <connection
    kind="reset"
    version="14.1"
    start="sys_ddr3_cntrl.emif_usr_reset_reset_source"
-   end="axi_dmac_0.m_dest_axi_reset" />
- <connection
-   kind="reset"
-   version="14.1"
-   start="sys_ddr3_cntrl.emif_usr_reset_reset_source"
-   end="axi_dmac_1.m_dest_axi_reset" />
+   end="axi_ad9144_dma.m_src_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />