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common- dac data path split

main
Rejeesh Kutty 2016-09-23 16:13:24 -04:00
parent 6837143110
commit 6735333aea
4 changed files with 446 additions and 389 deletions
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54
library/common/ad_dds.v
View File

@ -34,63 +34,59 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
module ad_dds ( module ad_dds #(
// data path disable
parameter DISABLE = 0) (
// interface // interface
clk, input clk,
dds_format, input dds_format,
dds_phase_0, input [15:0] dds_phase_0,
dds_scale_0, input [15:0] dds_scale_0,
dds_phase_1, input [15:0] dds_phase_1,
dds_scale_1, input [15:0] dds_scale_1,
dds_data); output [15:0] dds_data);
// interface
input clk;
input dds_format;
input [15:0] dds_phase_0;
input [15:0] dds_scale_0;
input [15:0] dds_phase_1;
input [15:0] dds_scale_1;
output [15:0] dds_data;
// internal registers // internal registers
reg [15:0] dds_data_int = 'd0; reg [15:0] dds_data_int = 'd0;
reg [15:0] dds_data = 'd0; reg [15:0] dds_data_out = 'd0;
reg [15:0] dds_scale_0_d = 'd0;
reg [15:0] dds_scale_1_d = 'd0;
reg [15:0] dds_scale_0_r = 'd0;
reg [15:0] dds_scale_1_r = 'd0;
// internal signals // internal signals
wire [15:0] dds_data_0_s; wire [15:0] dds_data_0_s;
wire [15:0] dds_data_1_s; wire [15:0] dds_data_1_s;
// disable
assign dds_data = (DISABLE == 1) ? 16'd0 : dds_data_out;
// dds channel output // dds channel output
always @(posedge clk) begin always @(posedge clk) begin
dds_data_int <= dds_data_0_s + dds_data_1_s; dds_data_int <= dds_data_0_s + dds_data_1_s;
dds_data[15:15] <= dds_data_int[15] ^ dds_format; dds_data_out[15:15] <= dds_data_int[15] ^ dds_format;
dds_data[14: 0] <= dds_data_int[14:0]; dds_data_out[14: 0] <= dds_data_int[14:0];
end end
always @(posedge clk) begin always @(posedge clk) begin
dds_scale_0_r <= dds_scale_0; dds_scale_0_d <= dds_scale_0;
dds_scale_1_r <= dds_scale_1; dds_scale_1_d <= dds_scale_1;
end end
// dds-1 // dds-1
ad_dds_1 i_dds_1_0 ( ad_dds_1 i_dds_1_0 (
.clk (clk), .clk (clk),
.angle (dds_phase_0), .angle (dds_phase_0),
.scale (dds_scale_0_r), .scale (dds_scale_0_d),
.dds_data (dds_data_0_s)); .dds_data (dds_data_0_s));
// dds-2 // dds-2
@ -98,7 +94,7 @@ module ad_dds (
ad_dds_1 i_dds_1_1 ( ad_dds_1 i_dds_1_1 (
.clk (clk), .clk (clk),
.angle (dds_phase_1), .angle (dds_phase_1),
.scale (dds_scale_1_r), .scale (dds_scale_1_d),
.dds_data (dds_data_1_s)); .dds_data (dds_data_1_s));
endmodule endmodule

346
library/common/up_dac_channel.v
View File

@ -37,112 +37,67 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module up_dac_channel ( module up_dac_channel #(
// dac interface
dac_clk,
dac_rst,
dac_dds_scale_1,
dac_dds_init_1,
dac_dds_incr_1,
dac_dds_scale_2,
dac_dds_init_2,
dac_dds_incr_2,
dac_pat_data_1,
dac_pat_data_2,
dac_data_sel,
dac_iq_mode,
dac_iqcor_enb,
dac_iqcor_coeff_1,
dac_iqcor_coeff_2,
// user controls
up_usr_datatype_be,
up_usr_datatype_signed,
up_usr_datatype_shift,
up_usr_datatype_total_bits,
up_usr_datatype_bits,
up_usr_interpolation_m,
up_usr_interpolation_n,
dac_usr_datatype_be,
dac_usr_datatype_signed,
dac_usr_datatype_shift,
dac_usr_datatype_total_bits,
dac_usr_datatype_bits,
dac_usr_interpolation_m,
dac_usr_interpolation_n,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters // parameters
parameter DAC_COMMON_ID = 6'h11; parameter COMMON_ID = 6'h11,
parameter DAC_CHANNEL_ID = 4'h0; parameter CHANNEL_ID = 4'h0,
parameter DDS_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// dac interface // dac interface
input dac_clk; input dac_clk,
input dac_rst; input dac_rst,
output [15:0] dac_dds_scale_1; output [15:0] dac_dds_scale_1,
output [15:0] dac_dds_init_1; output [15:0] dac_dds_init_1,
output [15:0] dac_dds_incr_1; output [15:0] dac_dds_incr_1,
output [15:0] dac_dds_scale_2; output [15:0] dac_dds_scale_2,
output [15:0] dac_dds_init_2; output [15:0] dac_dds_init_2,
output [15:0] dac_dds_incr_2; output [15:0] dac_dds_incr_2,
output [15:0] dac_pat_data_1; output [15:0] dac_pat_data_1,
output [15:0] dac_pat_data_2; output [15:0] dac_pat_data_2,
output [ 3:0] dac_data_sel; output [ 3:0] dac_data_sel,
output dac_iq_mode; output dac_iq_mode,
output dac_iqcor_enb; output dac_iqcor_enb,
output [15:0] dac_iqcor_coeff_1; output [15:0] dac_iqcor_coeff_1,
output [15:0] dac_iqcor_coeff_2; output [15:0] dac_iqcor_coeff_2,
// user controls // user controls
output up_usr_datatype_be; output up_usr_datatype_be,
output up_usr_datatype_signed; output up_usr_datatype_signed,
output [ 7:0] up_usr_datatype_shift; output [ 7:0] up_usr_datatype_shift,
output [ 7:0] up_usr_datatype_total_bits; output [ 7:0] up_usr_datatype_total_bits,
output [ 7:0] up_usr_datatype_bits; output [ 7:0] up_usr_datatype_bits,
output [15:0] up_usr_interpolation_m; output [15:0] up_usr_interpolation_m,
output [15:0] up_usr_interpolation_n; output [15:0] up_usr_interpolation_n,
input dac_usr_datatype_be; input dac_usr_datatype_be,
input dac_usr_datatype_signed; input dac_usr_datatype_signed,
input [ 7:0] dac_usr_datatype_shift; input [ 7:0] dac_usr_datatype_shift,
input [ 7:0] dac_usr_datatype_total_bits; input [ 7:0] dac_usr_datatype_total_bits,
input [ 7:0] dac_usr_datatype_bits; input [ 7:0] dac_usr_datatype_bits,
input [15:0] dac_usr_interpolation_m; input [15:0] dac_usr_interpolation_m,
input [15:0] dac_usr_interpolation_n; input [15:0] dac_usr_interpolation_n,
// bus interface // bus interface
input up_rstn; input up_rstn,
input up_clk; input up_clk,
input up_wreq; input up_wreq,
input [13:0] up_waddr; input [13:0] up_waddr,
input [31:0] up_wdata; input [31:0] up_wdata,
output up_wack; output up_wack,
input up_rreq; input up_rreq,
input [13:0] up_raddr; input [13:0] up_raddr,
output [31:0] up_rdata; output [31:0] up_rdata,
output up_rack; output up_rack);
// internal registers // internal registers
reg up_wack = 'd0; reg up_wack_int = 'd0;
reg [15:0] up_dac_dds_scale_1 = 'd0; reg [15:0] up_dac_dds_scale_1 = 'd0;
reg [15:0] up_dac_dds_init_1 = 'd0; reg [15:0] up_dac_dds_init_1 = 'd0;
reg [15:0] up_dac_dds_incr_1 = 'd0; reg [15:0] up_dac_dds_incr_1 = 'd0;
@ -157,16 +112,16 @@ module up_dac_channel (
reg [ 3:0] up_dac_data_sel = 'd0; reg [ 3:0] up_dac_data_sel = 'd0;
reg [15:0] up_dac_iqcor_coeff_1 = 'd0; reg [15:0] up_dac_iqcor_coeff_1 = 'd0;
reg [15:0] up_dac_iqcor_coeff_2 = 'd0; reg [15:0] up_dac_iqcor_coeff_2 = 'd0;
reg up_usr_datatype_be = 'd0; reg up_usr_datatype_be_int = 'd0;
reg up_usr_datatype_signed = 'd0; reg up_usr_datatype_signed_int = 'd0;
reg [ 7:0] up_usr_datatype_shift = 'd0; reg [ 7:0] up_usr_datatype_shift_int = 'd0;
reg [ 7:0] up_usr_datatype_total_bits = 'd0; reg [ 7:0] up_usr_datatype_total_bits_int = 'd0;
reg [ 7:0] up_usr_datatype_bits = 'd0; reg [ 7:0] up_usr_datatype_bits_int = 'd0;
reg [15:0] up_usr_interpolation_m = 'd0; reg [15:0] up_usr_interpolation_m_int = 'd0;
reg [15:0] up_usr_interpolation_n = 'd0; reg [15:0] up_usr_interpolation_n_int = 'd0;
reg up_dac_iq_mode = 'd0; reg up_dac_iq_mode = 'd0;
reg up_rack = 'd0; reg up_rack_int = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata_int = 'd0;
reg [15:0] up_dac_dds_scale_tc_1 = 'd0; reg [15:0] up_dac_dds_scale_tc_1 = 'd0;
reg [15:0] up_dac_dds_scale_tc_2 = 'd0; reg [15:0] up_dac_dds_scale_tc_2 = 'd0;
reg [15:0] up_dac_iqcor_coeff_tc_1 = 'd0; reg [15:0] up_dac_iqcor_coeff_tc_1 = 'd0;
@ -195,38 +150,41 @@ module up_dac_channel (
// decode block select // decode block select
assign up_wreq_s = ((up_waddr[13:8] == DAC_COMMON_ID) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0; assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:8] == DAC_COMMON_ID) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0; assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0;
// processor write interface // processor write interface
assign up_wack = up_wack_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack_int <= 'd0;
end else begin
up_wack_int <= up_wreq_s;
end
end
generate
if (DDS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_dac_dds_scale_1 <= 'd0;
up_dac_dds_init_1 <= 'd0;
up_dac_dds_incr_1 <= 'd0;
up_dac_dds_scale_2 <= 'd0;
up_dac_dds_init_2 <= 'd0;
up_dac_dds_incr_2 <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_wack <= 'd0;
up_dac_dds_scale_1 <= 'd0; up_dac_dds_scale_1 <= 'd0;
up_dac_dds_init_1 <= 'd0; up_dac_dds_init_1 <= 'd0;
up_dac_dds_incr_1 <= 'd0; up_dac_dds_incr_1 <= 'd0;
up_dac_dds_scale_2 <= 'd0; up_dac_dds_scale_2 <= 'd0;
up_dac_dds_init_2 <= 'd0; up_dac_dds_init_2 <= 'd0;
up_dac_dds_incr_2 <= 'd0; up_dac_dds_incr_2 <= 'd0;
up_dac_pat_data_2 <= 'd0;
up_dac_pat_data_1 <= 'd0;
up_dac_iqcor_enb <= 'd0;
up_dac_lb_enb <= 'd0;
up_dac_pn_enb <= 'd0;
up_dac_data_sel <= 'd0;
up_dac_iqcor_coeff_1 <= 'd0;
up_dac_iqcor_coeff_2 <= 'd0;
up_usr_datatype_be <= 'd0;
up_usr_datatype_signed <= 'd0;
up_usr_datatype_shift <= 'd0;
up_usr_datatype_total_bits <= 'd0;
up_usr_datatype_bits <= 'd0;
up_usr_interpolation_m <= 'd0;
up_usr_interpolation_n <= 'd0;
up_dac_iq_mode <= 'd0;
end else begin end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_dac_dds_scale_1 <= up_wdata[15:0]; up_dac_dds_scale_1 <= up_wdata[15:0];
end end
@ -241,33 +199,128 @@ module up_dac_channel (
up_dac_dds_init_2 <= up_wdata[31:16]; up_dac_dds_init_2 <= up_wdata[31:16];
up_dac_dds_incr_2 <= up_wdata[15:0]; up_dac_dds_incr_2 <= up_wdata[15:0];
end end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_pat_data_2 <= 'd0;
up_dac_pat_data_1 <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
up_dac_pat_data_2 <= up_wdata[31:16]; up_dac_pat_data_2 <= up_wdata[31:16];
up_dac_pat_data_1 <= up_wdata[15:0]; up_dac_pat_data_1 <= up_wdata[15:0];
end end
end
end
generate
if (IQCORRECTION_DISABLE == 1) begin
always @(posedge up_clk) begin
up_dac_iqcor_enb <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_iqcor_enb <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
up_dac_iqcor_enb <= up_wdata[2]; up_dac_iqcor_enb <= up_wdata[2];
end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_lb_enb <= 'd0;
up_dac_pn_enb <= 'd0;
up_dac_data_sel <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
up_dac_lb_enb <= up_wdata[1]; up_dac_lb_enb <= up_wdata[1];
up_dac_pn_enb <= up_wdata[0]; up_dac_pn_enb <= up_wdata[0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
up_dac_data_sel <= up_wdata[3:0]; up_dac_data_sel <= up_wdata[3:0];
end end
end
end
generate
if (IQCORRECTION_DISABLE == 1) begin
always @(posedge up_clk) begin
up_dac_iqcor_coeff_1 <= 'd0;
up_dac_iqcor_coeff_2 <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_iqcor_coeff_1 <= 'd0;
up_dac_iqcor_coeff_2 <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin
up_dac_iqcor_coeff_1 <= up_wdata[31:16]; up_dac_iqcor_coeff_1 <= up_wdata[31:16];
up_dac_iqcor_coeff_2 <= up_wdata[15:0]; up_dac_iqcor_coeff_2 <= up_wdata[15:0];
end end
end
end
end
endgenerate
assign up_usr_datatype_be = up_usr_datatype_be_int;
assign up_usr_datatype_signed = up_usr_datatype_signed_int;
assign up_usr_datatype_shift = up_usr_datatype_shift_int;
assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int;
assign up_usr_datatype_bits = up_usr_datatype_bits_int;
assign up_usr_interpolation_m = up_usr_interpolation_m_int;
assign up_usr_interpolation_n = up_usr_interpolation_n_int;
generate
if (USERPORTS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_usr_datatype_be_int <= 'd0;
up_usr_datatype_signed_int <= 'd0;
up_usr_datatype_shift_int <= 'd0;
up_usr_datatype_total_bits_int <= 'd0;
up_usr_datatype_bits_int <= 'd0;
up_usr_interpolation_m_int <= 'd0;
up_usr_interpolation_n_int <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_datatype_be_int <= 'd0;
up_usr_datatype_signed_int <= 'd0;
up_usr_datatype_shift_int <= 'd0;
up_usr_datatype_total_bits_int <= 'd0;
up_usr_datatype_bits_int <= 'd0;
up_usr_interpolation_m_int <= 'd0;
up_usr_interpolation_n_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
up_usr_datatype_be <= up_wdata[25]; up_usr_datatype_be_int <= up_wdata[25];
up_usr_datatype_signed <= up_wdata[24]; up_usr_datatype_signed_int <= up_wdata[24];
up_usr_datatype_shift <= up_wdata[23:16]; up_usr_datatype_shift_int <= up_wdata[23:16];
up_usr_datatype_total_bits <= up_wdata[15:8]; up_usr_datatype_total_bits_int <= up_wdata[15:8];
up_usr_datatype_bits <= up_wdata[7:0]; up_usr_datatype_bits_int <= up_wdata[7:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
up_usr_interpolation_m <= up_wdata[31:16]; up_usr_interpolation_m_int <= up_wdata[31:16];
up_usr_interpolation_n <= up_wdata[15:0]; up_usr_interpolation_n_int <= up_wdata[15:0];
end end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_iq_mode <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin
up_dac_iq_mode <= up_wdata[0]; up_dac_iq_mode <= up_wdata[0];
end end
@ -276,31 +329,34 @@ module up_dac_channel (
// processor read interface // processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_rack <= 'd0; up_rack_int <= 'd0;
up_rdata <= 'd0; up_rdata_int <= 'd0;
end else begin end else begin
up_rack <= up_rreq_s; up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0]) case (up_raddr[3:0])
4'h0: up_rdata <= {16'd0, up_dac_dds_scale_1}; 4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1};
4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1}; 4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1};
4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2}; 4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2};
4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2}; 4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2};
4'h4: up_rdata <= {up_dac_pat_data_2, up_dac_pat_data_1}; 4'h4: up_rdata_int <= { up_dac_pat_data_2, up_dac_pat_data_1};
4'h5: up_rdata <= {29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb}; 4'h5: up_rdata_int <= { 29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb};
4'h6: up_rdata <= {28'd0, up_dac_data_sel_m}; 4'h6: up_rdata_int <= { 28'd0, up_dac_data_sel_m};
4'h7: up_rdata <= {up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2}; 4'h7: up_rdata_int <= { up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2};
4'h8: up_rdata <= {6'd0, dac_usr_datatype_be, dac_usr_datatype_signed, 4'h8: up_rdata_int <= { 6'd0, dac_usr_datatype_be, dac_usr_datatype_signed,
dac_usr_datatype_shift, dac_usr_datatype_total_bits, dac_usr_datatype_shift, dac_usr_datatype_total_bits,
dac_usr_datatype_bits}; dac_usr_datatype_bits};
4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n}; 4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n};
4'ha: up_rdata <= {31'd0, up_dac_iq_mode}; 4'ha: up_rdata_int <= { 31'd0, up_dac_iq_mode};
default: up_rdata <= 0; default: up_rdata_int <= 0;
endcase endcase
end else begin end else begin
up_rdata <= 32'd0; up_rdata_int <= 32'd0;
end end
end end
end end

323
library/common/up_dac_common.v
View File

@ -37,121 +37,76 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module up_dac_common ( module up_dac_common #(
// mmcm reset
mmcm_rst,
// dac interface
dac_clk,
dac_rst,
dac_sync,
dac_frame,
dac_clksel,
dac_par_type,
dac_par_enb,
dac_r1_mode,
dac_datafmt,
dac_datarate,
dac_status,
dac_status_ovf,
dac_status_unf,
dac_clk_ratio,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// user channel control
up_usr_chanmax,
dac_usr_chanmax,
up_dac_gpio_in,
up_dac_gpio_out,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters // parameters
localparam PCORE_VERSION = 32'h00080062; parameter ID = 0,
parameter ID = 0; parameter CONFIG = 0,
parameter DAC_COMMON_ID = 6'h10; parameter COMMON_ID = 6'h10,
parameter DRP_DISABLE = 6'h00,
parameter USERPORTS_DISABLE = 0) (
// mmcm reset // mmcm reset
output mmcm_rst; output mmcm_rst,
// dac interface // dac interface
input dac_clk; input dac_clk,
output dac_rst; output dac_rst,
output dac_sync; output dac_sync,
output dac_frame; output dac_frame,
output dac_clksel; output dac_clksel,
output dac_par_type; output dac_par_type,
output dac_par_enb; output dac_par_enb,
output dac_r1_mode; output dac_r1_mode,
output dac_datafmt; output dac_datafmt,
output [ 7:0] dac_datarate; output [ 7:0] dac_datarate,
input dac_status; input dac_status,
input dac_status_ovf; input dac_status_ovf,
input dac_status_unf; input dac_status_unf,
input [31:0] dac_clk_ratio; input [31:0] dac_clk_ratio,
// drp interface // drp interface
output up_drp_sel; output up_drp_sel,
output up_drp_wr; output up_drp_wr,
output [11:0] up_drp_addr; output [11:0] up_drp_addr,
output [31:0] up_drp_wdata; output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata; input [31:0] up_drp_rdata,
input up_drp_ready; input up_drp_ready,
input up_drp_locked; input up_drp_locked,
// user channel control // user channel control
output [ 7:0] up_usr_chanmax; output [ 7:0] up_usr_chanmax,
input [ 7:0] dac_usr_chanmax; input [ 7:0] dac_usr_chanmax,
input [31:0] up_dac_gpio_in; input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out; output [31:0] up_dac_gpio_out,
// bus interface // bus interface
input up_rstn; input up_rstn,
input up_clk; input up_clk,
input up_wreq; input up_wreq,
input [13:0] up_waddr; input [13:0] up_waddr,
input [31:0] up_wdata; input [31:0] up_wdata,
output up_wack; output up_wack,
input up_rreq; input up_rreq,
input [13:0] up_raddr; input [13:0] up_raddr,
output [31:0] up_rdata; output [31:0] up_rdata,
output up_rack; output up_rack);
// parameters
localparam VERSION = 32'h00090062;
// internal registers // internal registers
reg up_core_preset = 'd0; reg up_core_preset = 'd0;
reg up_mmcm_preset = 'd0; reg up_mmcm_preset = 'd0;
reg up_wack = 'd0; reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0; reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0; reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0; reg up_resetn = 'd0;
@ -163,26 +118,26 @@ module up_dac_common (
reg [ 7:0] up_dac_datarate = 'd0; reg [ 7:0] up_dac_datarate = 'd0;
reg up_dac_frame = 'd0; reg up_dac_frame = 'd0;
reg up_dac_clksel = 'd0; reg up_dac_clksel = 'd0;
reg up_drp_sel = 'd0; reg up_drp_sel_int = 'd0;
reg up_drp_wr = 'd0; reg up_drp_wr_int = 'd0;
reg up_drp_status = 'd0; reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0; reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0; reg [11:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata = 'd0; reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_hold = 'd0; reg [31:0] up_drp_rdata_hold = 'd0;
reg up_status_ovf = 'd0; reg up_status_ovf = 'd0;
reg up_status_unf = 'd0; reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0; reg [ 7:0] up_usr_chanmax_int = 'd0;
reg [31:0] up_dac_gpio_out = 'd0; reg [31:0] up_dac_gpio_out_int = 'd0;
reg up_rack = 'd0; reg up_rack_int = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata_int = 'd0;
reg dac_sync_d = 'd0; reg dac_sync_d = 'd0;
reg dac_sync_2d = 'd0; reg dac_sync_2d = 'd0;
reg [ 5:0] dac_sync_count = 'd0; reg [ 5:0] dac_sync_count = 'd0;
reg dac_sync = 'd0; reg dac_sync_int = 'd0;
reg dac_frame_d = 'd0; reg dac_frame_d = 'd0;
reg dac_frame_2d = 'd0; reg dac_frame_2d = 'd0;
reg dac_frame = 'd0; reg dac_frame_int = 'd0;
// internal signals // internal signals
@ -198,16 +153,18 @@ module up_dac_common (
// decode block select // decode block select
assign up_wreq_s = (up_waddr[13:8] == DAC_COMMON_ID) ? up_wreq : 1'b0; assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == DAC_COMMON_ID) ? up_rreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
// processor write interface // processor write interface
assign up_wack = up_wack_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_core_preset <= 1'd1; up_core_preset <= 1'd1;
up_mmcm_preset <= 1'd1; up_mmcm_preset <= 1'd1;
up_wack <= 'd0; up_wack_int <= 'd0;
up_scratch <= 'd0; up_scratch <= 'd0;
up_mmcm_resetn <= 'd0; up_mmcm_resetn <= 'd0;
up_resetn <= 'd0; up_resetn <= 'd0;
@ -219,21 +176,10 @@ module up_dac_common (
up_dac_datarate <= 'd0; up_dac_datarate <= 'd0;
up_dac_frame <= 'd0; up_dac_frame <= 'd0;
up_dac_clksel <= 'd0; up_dac_clksel <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_dac_gpio_out <= 'd0;
end else begin end else begin
up_core_preset <= ~up_resetn; up_core_preset <= ~up_resetn;
up_mmcm_preset <= ~up_mmcm_resetn; up_mmcm_preset <= ~up_mmcm_resetn;
up_wack <= up_wreq_s; up_wack_int <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata; up_scratch <= up_wdata;
end end
@ -267,12 +213,42 @@ module up_dac_common (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
up_dac_clksel <= up_wdata[0]; up_dac_clksel <= up_wdata[0];
end end
end
end
assign up_drp_sel = up_drp_sel_int;
assign up_drp_wr = up_drp_wr_int;
assign up_drp_addr = up_drp_addr_int;
assign up_drp_wdata = up_drp_wdata_int;
generate
if (DRP_DISABLE == 1) begin
always @(posedge up_clk) begin
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel <= 1'b1; up_drp_sel_int <= 1'b1;
up_drp_wr <= ~up_wdata[28]; up_drp_wr_int <= ~up_wdata[28];
end else begin end else begin
up_drp_sel <= 1'b0; up_drp_sel_int <= 1'b0;
up_drp_wr <= 1'b0; up_drp_wr_int <= 1'b0;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1; up_drp_status <= 1'b1;
@ -281,14 +257,24 @@ module up_dac_common (
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28]; up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16]; up_drp_addr_int <= up_wdata[27:16];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
up_drp_wdata <= up_wdata; up_drp_wdata_int <= up_wdata;
end end
if (up_drp_ready == 1'b1) begin if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata; up_drp_rdata_hold <= up_drp_rdata;
end end
end
end
end
endgenerate
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
end else begin
if (up_status_ovf_s == 1'b1) begin if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1; up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@ -299,50 +285,80 @@ module up_dac_common (
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[0]; up_status_unf <= up_status_unf & ~up_wdata[0];
end end
end
end
assign up_usr_chanmax = up_usr_chanmax_int;
generate
if (USERPORTS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_usr_chanmax_int <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_chanmax_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0]; up_usr_chanmax_int <= up_wdata[7:0];
end end
end
end
end
endgenerate
assign up_dac_gpio_out = up_dac_gpio_out_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_gpio_out_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_dac_gpio_out <= up_wdata; up_dac_gpio_out_int <= up_wdata;
end end
end end
end end
// processor read interface // processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_rack <= 'd0; up_rack_int <= 'd0;
up_rdata <= 'd0; up_rdata_int <= 'd0;
end else begin end else begin
up_rack <= up_rreq_s; up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0]) case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION; 8'h00: up_rdata_int <= VERSION;
8'h01: up_rdata <= ID; 8'h01: up_rdata_int <= ID;
8'h02: up_rdata <= up_scratch; 8'h02: up_rdata_int <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h03: up_rdata_int <= CONFIG;
8'h11: up_rdata <= {31'd0, up_dac_sync}; 8'h10: up_rdata_int <= {30'd0, up_mmcm_resetn, up_resetn};
8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, 8'h11: up_rdata_int <= {31'd0, up_dac_sync};
8'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
up_dac_datafmt, 4'd0}; up_dac_datafmt, 4'd0};
8'h13: up_rdata <= {24'd0, up_dac_datarate}; 8'h13: up_rdata_int <= {24'd0, up_dac_datarate};
8'h14: up_rdata <= {31'd0, up_dac_frame}; 8'h14: up_rdata_int <= {31'd0, up_dac_frame};
8'h15: up_rdata <= up_dac_clk_count_s; 8'h15: up_rdata_int <= up_dac_clk_count_s;
8'h16: up_rdata <= dac_clk_ratio; 8'h16: up_rdata_int <= dac_clk_ratio;
8'h17: up_rdata <= {31'd0, up_status_s}; 8'h17: up_rdata_int <= {31'd0, up_status_s};
8'h18: up_rdata <= {31'd0, up_dac_clksel}; 8'h18: up_rdata_int <= {31'd0, up_dac_clksel};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, 16'b0}; 8'h1c: up_rdata_int <= {3'd0, up_drp_rwn, up_drp_addr_int, 16'b0};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, 16'b0}; 8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status, 16'b0};
8'h1e: up_rdata <= up_drp_wdata; 8'h1e: up_rdata_int <= up_drp_wdata_int;
8'h1f: up_rdata <= up_drp_rdata_hold; 8'h1f: up_rdata_int <= up_drp_rdata_hold;
8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf}; 8'h22: up_rdata_int <= {30'd0, up_status_ovf, up_status_unf};
8'h28: up_rdata <= {24'd0, dac_usr_chanmax}; 8'h28: up_rdata_int <= {24'd0, dac_usr_chanmax};
8'h2e: up_rdata <= up_dac_gpio_in; 8'h2e: up_rdata_int <= up_dac_gpio_in;
8'h2f: up_rdata <= up_dac_gpio_out; 8'h2f: up_rdata_int <= up_dac_gpio_out_int;
default: up_rdata <= 0; default: up_rdata_int <= 0;
endcase endcase
end else begin end else begin
up_rdata <= 32'd0; up_rdata_int <= 32'd0;
end end
end end
end end
@ -391,6 +407,9 @@ module up_dac_common (
// generate frame and enable // generate frame and enable
assign dac_sync = dac_sync_int;
assign dac_frame = dac_frame_int;
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
dac_sync_d <= dac_sync_s; dac_sync_d <= dac_sync_s;
dac_sync_2d <= dac_sync_d; dac_sync_2d <= dac_sync_d;
@ -399,10 +418,10 @@ module up_dac_common (
end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin
dac_sync_count <= 6'h20; dac_sync_count <= 6'h20;
end end
dac_sync <= dac_sync_count[5]; dac_sync_int <= dac_sync_count[5];
dac_frame_d <= dac_frame_s; dac_frame_d <= dac_frame_s;
dac_frame_2d <= dac_frame_d; dac_frame_2d <= dac_frame_d;
dac_frame <= dac_frame_d & ~dac_frame_2d; dac_frame_int <= dac_frame_d & ~dac_frame_2d;
end end
// dac clock monitor // dac clock monitor

112
library/common/up_delay_cntrl.v
View File

@ -37,73 +37,49 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module up_delay_cntrl ( module up_delay_cntrl #(
// delay interface
delay_clk,
delay_rst,
delay_locked,
// io interface
up_dld,
up_dwdata,
up_drdata,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters // parameters
parameter DATA_WIDTH = 8; parameter DISABLE = 0,
parameter BASE_ADDRESS = 6'h02; parameter DATA_WIDTH = 8,
parameter BASE_ADDRESS = 6'h02) (
// delay interface // delay interface
input delay_clk; input delay_clk,
output delay_rst; output delay_rst,
input delay_locked; input delay_locked,
// io interface // io interface
output [(DATA_WIDTH-1):0] up_dld; output [(DATA_WIDTH-1):0] up_dld,
output [((DATA_WIDTH*5)-1):0] up_dwdata; output [((DATA_WIDTH*5)-1):0] up_dwdata,
input [((DATA_WIDTH*5)-1):0] up_drdata; input [((DATA_WIDTH*5)-1):0] up_drdata,
// processor interface // processor interface
input up_rstn; input up_rstn,
input up_clk; input up_clk,
input up_wreq; input up_wreq,
input [13:0] up_waddr; input [13:0] up_waddr,
input [31:0] up_wdata; input [31:0] up_wdata,
output up_wack; output up_wack,
input up_rreq; input up_rreq,
input [13:0] up_raddr; input [13:0] up_raddr,
output [31:0] up_rdata; output [31:0] up_rdata,
output up_rack; output up_rack);
// internal registers // internal registers
reg up_preset = 'd0; reg up_preset = 'd0;
reg up_wack = 'd0; reg up_wack_int = 'd0;
reg up_rack = 'd0; reg up_rack_int = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata_int = 'd0;
reg up_dlocked_m1 = 'd0; reg up_dlocked_m1 = 'd0;
reg up_dlocked = 'd0; reg up_dlocked = 'd0;
reg [(DATA_WIDTH-1):0] up_dld = 'd0; reg [(DATA_WIDTH-1):0] up_dld_int = 'd0;
reg [((DATA_WIDTH*5)-1):0] up_dwdata = 'd0; reg [((DATA_WIDTH*5)-1):0] up_dwdata_int = 'd0;
// internal signals // internal signals
@ -117,6 +93,7 @@ module up_delay_cntrl (
wire [(DATA_WIDTH-1):0] up_drdata0_s; wire [(DATA_WIDTH-1):0] up_drdata0_s;
wire [(DATA_WIDTH-1):0] up_dld_s; wire [(DATA_WIDTH-1):0] up_dld_s;
wire [((DATA_WIDTH*5)-1):0] up_dwdata_s; wire [((DATA_WIDTH*5)-1):0] up_dwdata_s;
wire delay_rst_s;
// variables // variables
@ -144,26 +121,30 @@ module up_delay_cntrl (
// processor interface // processor interface
assign up_wack = (DISABLE == 1) ? 1'd0 : up_wack_int;
assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_int;
assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_preset <= 1'd1; up_preset <= 1'd1;
up_wack <= 'd0; up_wack_int <= 'd0;
up_rack <= 'd0; up_rack_int <= 'd0;
up_rdata <= 'd0; up_rdata_int <= 'd0;
up_dlocked_m1 <= 'd0; up_dlocked_m1 <= 'd0;
up_dlocked <= 'd0; up_dlocked <= 'd0;
end else begin end else begin
up_preset <= 1'd0; up_preset <= 1'd0;
up_wack <= up_wreq_s; up_wack_int <= up_wreq_s;
up_rack <= up_rreq_s; up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin if (up_rreq_s == 1'b1) begin
if (up_dlocked == 1'b0) begin if (up_dlocked == 1'b0) begin
up_rdata <= 32'hffffffff; up_rdata_int <= 32'hffffffff;
end else begin end else begin
up_rdata <= {27'd0, up_rdata_s}; up_rdata_int <= {27'd0, up_rdata_s};
end end
end else begin end else begin
up_rdata <= 32'd0; up_rdata_int <= 32'd0;
end end
up_dlocked_m1 <= delay_locked; up_dlocked_m1 <= delay_locked;
up_dlocked <= up_dlocked_m1; up_dlocked <= up_dlocked_m1;
@ -176,28 +157,33 @@ module up_delay_cntrl (
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0; assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ? assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ?
up_wdata[4:0] : up_dwdata[((n*5)+4):(n*5)]; up_wdata[4:0] : up_dwdata_int[((n*5)+4):(n*5)];
end end
endgenerate endgenerate
assign up_dld = (DISABLE == 1) ? 'd0 : up_dld_int;
assign up_dwdata = (DISABLE == 1) ? 'd0 : up_dwdata_int;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_dld <= 'd0; up_dld_int <= 'd0;
up_dwdata <= 'd0; up_dwdata_int <= 'd0;
end else begin end else begin
up_dld <= up_dld_s; up_dld_int <= up_dld_s;
if (up_wreq_s == 1'b1) begin if (up_wreq_s == 1'b1) begin
up_dwdata <= up_dwdata_s; up_dwdata_int <= up_dwdata_s;
end end
end end
end end
// resets // resets
assign delay_rst = (DISABLE == 1) ? 1'd0 : delay_rst_s;
ad_rst i_delay_rst_reg ( ad_rst i_delay_rst_reg (
.preset (up_preset), .preset (up_preset),
.clk (delay_clk), .clk (delay_clk),
.rst (delay_rst)); .rst (delay_rst_s));
endmodule endmodule