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ad6676evb: Update projects with ad_sysref_gen

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Istvan Csomortani 2016-12-19 10:52:25 +00:00
parent a228c05bd3
commit 67390c2a95
9 changed files with 28 additions and 4 deletions
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2
projects/ad6676evb/common/ad6676evb_bd.tcl
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@ -44,6 +44,7 @@ set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad6676_
# reference clocks & resets
create_bd_port -dir I rx_ref_clk_0
create_bd_port -dir O rx_core_clk
ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_*
@ -56,6 +57,7 @@ ad_connect sys_cpu_clk util_ad6676_xcvr/up_clk
ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
ad_connect util_ad6676_xcvr/rx_out_clk_0 rx_core_clk
ad_connect axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof
ad_connect axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk

1
projects/ad6676evb/vc707/Makefile
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@ -17,6 +17,7 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj
M_DEPS += ../../common/vc707/vc707_system_constr.xdc
M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr

3
projects/ad6676evb/vc707/system_constr.xdc
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@ -35,3 +35,6 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]

1
projects/ad6676evb/vc707/system_project.tcl
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@ -10,6 +10,7 @@ adi_project_files ad6676evb_vc707 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
adi_project_run ad6676evb_vc707

8
projects/ad6676evb/vc707/system_top.v
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@ -200,6 +200,7 @@ module system_top (
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire rx_clk;
// default logic
@ -219,7 +220,6 @@ module system_top (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
assign rx_sysref = gpio_o[48]
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
@ -247,6 +247,11 @@ module system_top (
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[48]),
.sysref_out (rx_sysref));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
@ -297,6 +302,7 @@ module system_top (
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.rx_core_clk (rx_clk),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),

2
projects/ad6676evb/zc706/Makefile
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@ -16,6 +16,8 @@ M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr

3
projects/ad6676evb/zc706/system_constr.xdc
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@ -35,3 +35,6 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]

1
projects/ad6676evb/zc706/system_project.tcl
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@ -10,6 +10,7 @@ adi_project_files ad6676evb_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run ad6676evb_zc706

11
projects/ad6676evb/zc706/system_top.v
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@ -177,8 +177,9 @@ module system_top (
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire rx_sysref;
wire rx_clk;
// instantiations
@ -193,8 +194,6 @@ module system_top (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
assign rx_sysref = gpio_o[48];
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
@ -227,6 +226,11 @@ module system_top (
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[48]),
.sysref_out (rx_sysref));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -279,6 +283,7 @@ module system_top (
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.rx_core_clk (rx_clk),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),