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Merge branch 'hdl_2016_r1' into dev 

hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
main
AndreiGrozav 2016-04-19 18:05:50 +03:00
parent 402253d308 c291f8f107
commit 679d471d75
45 changed files with 314 additions and 188 deletions
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8
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -202,6 +202,8 @@ module axi_hdmi_tx (
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire [31:0] hdmi_clip_max_s;
wire [31:0] hdmi_clip_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
@ -271,6 +273,8 @@ module axi_hdmi_tx (
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
@ -356,7 +360,9 @@ module axi_hdmi_tx (
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s));
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s));
// hdmi output clock

149
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -97,7 +97,9 @@ module axi_hdmi_tx_core (
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min);
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min);
// parameters
@ -164,6 +166,8 @@ module axi_hdmi_tx_core (
input [15:0] hdmi_vs_width;
input [15:0] hdmi_ve_max;
input [15:0] hdmi_ve_min;
input [23:0] hdmi_clip_max;
input [23:0] hdmi_clip_min;
// internal registers
@ -205,12 +209,24 @@ module axi_hdmi_tx_core (
reg hdmi_vsync_data_e = 'd0;
reg hdmi_data_e = 'd0;
reg [23:0] hdmi_data = 'd0;
reg hdmi_24_csc_hsync = 'd0;
reg hdmi_24_csc_vsync = 'd0;
reg hdmi_24_csc_hsync_data_e = 'd0;
reg hdmi_24_csc_vsync_data_e = 'd0;
reg hdmi_24_csc_data_e = 'd0;
reg [23:0] hdmi_24_csc_data = 'd0;
reg hdmi_24_hsync = 'd0;
reg hdmi_24_vsync = 'd0;
reg hdmi_24_hsync_data_e = 'd0;
reg hdmi_24_vsync_data_e = 'd0;
reg hdmi_24_data_e = 'd0;
reg [23:0] hdmi_24_data = 'd0;
reg hdmi_24_hsync_ss = 'd0;
reg hdmi_24_vsync_ss = 'd0;
reg hdmi_24_hsync_data_e_ss = 'd0;
reg hdmi_24_vsync_data_e_ss = 'd0;
reg hdmi_24_data_e_ss = 'd0;
reg [23:0] hdmi_24_data_ss = 'd0;
reg hdmi_16_hsync = 'd0;
reg hdmi_16_vsync = 'd0;
reg hdmi_16_hsync_data_e = 'd0;
@ -220,6 +236,12 @@ module axi_hdmi_tx_core (
reg hdmi_es_hs_de = 'd0;
reg hdmi_es_vs_de = 'd0;
reg [15:0] hdmi_es_data = 'd0;
reg [23:0] hdmi_clip_data = 'd0;
reg hdmi_clip_hs_de_d = 'd0;
reg hdmi_clip_vs_de_d = 'd0;
reg hdmi_clip_hs_d = 'd0;
reg hdmi_clip_vs_d = 'd0;
reg hdmi_clip_de_d = 'd0;
// internal wires
@ -245,6 +267,10 @@ module axi_hdmi_tx_core (
wire hdmi_ss_vsync_data_e_s;
wire hdmi_ss_data_e_s;
wire [15:0] hdmi_ss_data_s;
wire hdmi_clip_hs_de_s;
wire hdmi_clip_vs_de_s;
wire hdmi_clip_de_s;
wire [23:0] hdmi_clip_data_s;
wire hdmi_es_hs_de_s;
wire hdmi_es_vs_de_s;
wire hdmi_es_de_s;
@ -453,6 +479,68 @@ module axi_hdmi_tx_core (
endcase
end
// Color space conversion bypass (RGB/YCbCr)
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_csc_hsync <= hdmi_hsync;
hdmi_24_csc_vsync <= hdmi_vsync;
hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_csc_data_e <= hdmi_data_e;
hdmi_24_csc_data <= hdmi_data;
end else begin
hdmi_24_csc_hsync <= hdmi_csc_hsync_s;
hdmi_24_csc_vsync <= hdmi_csc_vsync_s;
hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_csc_data_e <= hdmi_csc_data_e_s;
hdmi_24_csc_data <= hdmi_csc_data_s;
end
end
// hdmi clipping
assign hdmi_clip_data_s = hdmi_24_csc_data;
always @(posedge hdmi_clk) begin
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e;
hdmi_clip_de_d <= hdmi_24_csc_data_e;
// Cr (red-diff) / red
if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
end else begin
hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16];
end
// Y (luma) / green
if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
end else begin
hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8];
end
// Cb (blue-diff) / blue
if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
end else begin
hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0];
end
end
// hdmi csc 16, 24 and 36 outputs
assign hdmi_36_hsync = hdmi_24_hsync;
@ -463,21 +551,14 @@ module axi_hdmi_tx_core (
assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]};
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_hsync <= hdmi_hsync;
hdmi_24_vsync <= hdmi_vsync;
hdmi_24_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_data_e <= hdmi_data_e;
hdmi_24_data <= hdmi_data;
end else begin
hdmi_24_hsync <= hdmi_csc_hsync_s;
hdmi_24_vsync <= hdmi_csc_vsync_s;
hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_data_e <= hdmi_csc_data_e_s;
hdmi_24_data <= hdmi_csc_data_s;
end
hdmi_24_hsync <= hdmi_clip_hs_d;
hdmi_24_vsync <= hdmi_clip_vs_d;
hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d;
hdmi_24_vsync_data_e <= hdmi_clip_vs_de_d;
hdmi_24_data_e <= hdmi_clip_de_d;
hdmi_24_data <= hdmi_clip_data;
if (hdmi_ss_bypass == 1'b1) begin
hdmi_16_hsync <= hdmi_24_hsync;
hdmi_16_vsync <= hdmi_24_vsync;
@ -495,7 +576,7 @@ module axi_hdmi_tx_core (
end
end
// hdmi embedded sync clipping
// hdmi embedded sync
assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e;
assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e;
@ -507,31 +588,11 @@ module axi_hdmi_tx_core (
hdmi_es_vs_de <= hdmi_es_vs_de_s;
if (hdmi_es_de_s == 1'b0) begin
hdmi_es_data[15:8] <= 8'h80;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[15:8] > 8'heb)) begin
hdmi_es_data[15:8] <= 8'heb;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[15:8] < 8'h10)) begin
hdmi_es_data[15:8] <= 8'h10;
end else if (hdmi_es_data_s[15:8] > 8'hfe) begin
hdmi_es_data[15:8] <= 8'hfe;
end else if (hdmi_es_data_s[15:8] < 8'h01) begin
hdmi_es_data[15:8] <= 8'h01;
end else begin
hdmi_es_data[15:8] <= hdmi_es_data_s[15:8];
end
if (hdmi_es_de_s == 1'b0) begin
hdmi_es_data[7:0] <= 8'h80;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[7:0] > 8'heb)) begin
hdmi_es_data[7:0] <= 8'heb;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[7:0] < 8'h10)) begin
hdmi_es_data[7:0] <= 8'h10;
end else if (hdmi_es_data_s[7:0] > 8'hfe) begin
hdmi_es_data[7:0] <= 8'hfe;
end else if (hdmi_es_data_s[7:0] < 8'h01) begin
hdmi_es_data[7:0] <= 8'h01;
end else begin
hdmi_es_data[7:0] <= hdmi_es_data_s[7:0];
end
@ -569,13 +630,13 @@ module axi_hdmi_tx_core (
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.s444_de (hdmi_24_data_e),
.s444_sync ({hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_hsync_data_e,
hdmi_24_vsync_data_e,
hdmi_24_data_e}),
.s444_data (hdmi_24_data),
.s444_de (hdmi_clip_de_d),
.s444_sync ({hdmi_clip_hs_d,
hdmi_clip_vs_d,
hdmi_clip_hs_de_d,
hdmi_clip_vs_de_d,
hdmi_clip_de_d}),
.s444_data (hdmi_clip_data),
.s422_sync ({hdmi_ss_hsync_s,
hdmi_ss_vsync_s,
hdmi_ss_hsync_data_e_s,

8
library/axi_i2s_adi/axi_i2s_adi_ip.tcl
View File

@ -19,7 +19,7 @@ adi_ip_files axi_i2s_adi [list \
"axi_i2s_adi_constr.xdc" \
]
adi_ip_properties_lite axi_i2s_adi
adi_ip_properties axi_i2s_adi
adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late
adi_add_bus "DMA_ACK_RX" "slave" \
@ -30,6 +30,7 @@ adi_add_bus "DMA_ACK_RX" "slave" \
{"DMA_REQ_RX_DAREADY" "TREADY"} \
{"DMA_REQ_RX_DATYPE" "TUSER"} \
}
adi_add_bus "DMA_REQ_RX" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
@ -95,8 +96,9 @@ adi_set_ports_dependency "DMA_REQ_RX_ACLK" \
adi_set_ports_dependency "DMA_REQ_RX_RSTN" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \
-of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core]
ipx::save_core [ipx::current_core]

8
library/axi_jesd_gt/axi_jesd_gt.v
View File

@ -668,8 +668,8 @@ module axi_jesd_gt #(
// axi - clock & reset
input axi_aclk,
input axi_aresetn,
input s_axi_aclk,
input s_axi_aresetn,
// axi interface
@ -831,8 +831,8 @@ module axi_jesd_gt #(
// signal name changes
assign up_rstn = axi_aresetn;
assign up_clk = axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// pll

11
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
View File

@ -24,16 +24,7 @@ adi_ip_properties axi_jesd_gt
adi_ip_constraints axi_jesd_gt [list \
"axi_jesd_gt_constr.xdc" ]
ipx::remove_bus_interface qpll0_rst [ipx::current_core]
ipx::remove_bus_interface qpll1_rst [ipx::current_core]
set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_aclk \
-of_objects [ipx::current_core]]]
set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \
-of_objects [ipx::get_bus_interfaces axi_aclk \
-of_objects [ipx::current_core]]]
ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]
adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \
"qpll_rst qpll0_rst "\

3
library/axi_spdif_rx/axi_spdif_rx_ip.tcl
View File

@ -16,7 +16,7 @@ adi_ip_files axi_spdif_rx [list \
"axi_spdif_rx.vhd" \
"axi_spdif_rx_constr.xdc"]
adi_ip_properties_lite axi_spdif_rx
adi_ip_properties axi_spdif_rx
adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc
adi_add_bus "DMA_ACK" "slave" \
@ -49,4 +49,5 @@ adi_set_ports_dependency "DMA_REQ_RSTN" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
ipx::save_core [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]

7
library/axi_spdif_tx/axi_spdif_tx_ip.tcl
View File

@ -14,7 +14,7 @@ adi_ip_files axi_spdif_tx [list \
"axi_spdif_tx.vhd" \
"axi_spdif_tx_constr.xdc" ]
adi_ip_properties_lite axi_spdif_tx
adi_ip_properties axi_spdif_tx
adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc
adi_add_bus "DMA_ACK" "slave" \
@ -46,8 +46,7 @@ adi_set_ports_dependency "DMA_REQ_ACLK" \
adi_set_ports_dependency "DMA_REQ_RSTN" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \
-of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
ipx::save_core [ipx::current_core]

36
library/common/up_hdmi_tx.v
View File

@ -58,6 +58,8 @@ module up_hdmi_tx (
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min,
hdmi_status,
hdmi_tpm_oos,
hdmi_clk_ratio,
@ -107,6 +109,8 @@ module up_hdmi_tx (
output [15:0] hdmi_vs_width;
output [15:0] hdmi_ve_max;
output [15:0] hdmi_ve_min;
output [23:0] hdmi_clip_max;
output [23:0] hdmi_clip_min;
input hdmi_status;
input hdmi_tpm_oos;
input [31:0] hdmi_clk_ratio;
@ -157,6 +161,8 @@ module up_hdmi_tx (
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_ve_max = 'd0;
reg [15:0] up_ve_min = 'd0;
reg [23:0] up_clip_max = 'd0;
reg [23:0] up_clip_min = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -203,6 +209,8 @@ module up_hdmi_tx (
up_vs_width <= 'd0;
up_ve_max <= 'd0;
up_ve_min <= 'd0;
up_clip_max <= 24'hf0ebf0;
up_clip_min <= 24'h101010;
end else begin
up_core_preset <= ~up_resetn;
up_wack <= up_wreq_s;
@ -243,6 +251,21 @@ module up_hdmi_tx (
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin
up_clip_max <= 24'hfefefe;
up_clip_min <= 24'h010101;
end else begin
up_clip_max <= 24'hf0ebf0;
up_clip_min <= 24'h101010;
end
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin
up_clip_max <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
up_clip_min <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_hl_active <= up_wdata[31:16];
up_hl_width <= up_wdata[15:0];
@ -290,6 +313,9 @@ module up_hdmi_tx (
12'h017: up_rdata <= {31'd0, up_hdmi_status_s};
12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos};
12'h01a: up_rdata <= {8'd0, up_clip_max};
12'h01b: up_rdata <= {8'd0, up_clip_min};
12'h100: up_rdata <= {up_hl_active, up_hl_width};
12'h101: up_rdata <= {16'd0, up_hs_width};
12'h102: up_rdata <= {up_he_max, up_he_min};
@ -311,7 +337,7 @@ module up_hdmi_tx (
// hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_ss_bypass,
@ -328,7 +354,9 @@ module up_hdmi_tx (
up_vf_width,
up_vs_width,
up_ve_max,
up_ve_min}),
up_ve_min,
up_clip_max,
up_clip_min}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
@ -346,7 +374,9 @@ module up_hdmi_tx (
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min}));
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min}));
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
.up_rstn (up_rstn),

50
library/scripts/adi_ip.tcl
View File

@ -2,7 +2,7 @@
# check tool version
if {![info exists REQUIRED_VIVADO_VERSION]} {
set REQUIRED_VIVADO_VERSION "2015.2.1"
set REQUIRED_VIVADO_VERSION "2015.4.2"
}
if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
@ -78,13 +78,6 @@ proc adi_ip_bd {ip_name ip_bd_files} {
proc adi_ip_properties {ip_name} {
ipx::package_project -root_dir .
ipx::remove_memory_map {s_axi} [ipx::current_core]
ipx::add_memory_map {s_axi} [ipx::current_core]
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
set_property range {65536} [ipx::get_address_blocks axi_lite \
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
set_property vendor {analog.com} [ipx::current_core]
set_property library {user} [ipx::current_core]
@ -109,6 +102,47 @@ proc adi_ip_properties {ip_name} {
{qzynq} {Production} \
{azynq} {Production}} \
[ipx::current_core]
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface {\
s_axi_awvalid \
s_axi_awaddr \
s_axi_awprot \
s_axi_awready \
s_axi_wvalid \
s_axi_wdata \
s_axi_wstrb \
s_axi_wready \
s_axi_bvalid \
s_axi_bresp \
s_axi_bready \
s_axi_arvalid \
s_axi_araddr \
s_axi_arprot \
s_axi_arready \
s_axi_rvalid \
s_axi_rdata \
s_axi_rresp \
s_axi_rready} \
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::add_memory_map {s_axi} [ipx::current_core]
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
set_property range {65536} [ipx::get_address_blocks axi_lite \
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
-of_objects [ipx::current_core]]
set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces s_axi_aclk \
-of_objects [ipx::current_core]]]
ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
}
proc adi_ip_properties_lite {ip_name} {

3
library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl
View File

@ -15,9 +15,8 @@ adi_ip_constraints util_gmii_to_rgmii [list \
"util_gmii_to_rgmii_constr.xdc" ]
ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core]
set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]]
set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]]
ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core]
set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces reset -of_objects [ipx::current_core]]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \
[ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]]

2
projects/ad6676evb/common/ad6676evb_bd.tcl
View File

@ -11,7 +11,7 @@ create_bd_port -dir I -from 1 -to 0 rx_data_n
set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad6676_jesd]
set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd

2
projects/adv7511/common/adv7511_bd.tcl
View File

@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen

2
projects/common/a10gx/a10gx_system_assign.tcl
View File

@ -2,7 +2,7 @@
# device settings
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115S3F45I2SGE2
set_global_assignment -name DEVICE 10AX115S2F45I2SG
# clocks and resets

12
projects/common/a10gx/a10gx_system_bd.qsys
View File

@ -601,7 +601,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
<parameter name="device" value="10AX115S3F45I2SGE2" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@ -733,7 +733,7 @@
<module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
@ -1862,14 +1862,14 @@
<parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
<parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
<parameter name="SYS_INFO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="SYS_INFO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
<parameter name="TRAIT_SUPPORTS_VID" value="0" />
</module>
<module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="core_variation" value="MAC_PCS" />
<parameter name="deviceFamilyName" value="Arria 10" />
@ -1922,7 +1922,7 @@
<parameter
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
@ -1968,7 +1968,7 @@
<parameter
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
value="AddressWidth = -1" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>

6
projects/common/ac701/ac701_system_bd.tcl
View File

@ -62,7 +62,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
# instance: microblaze- mdm
@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
# instance: ddr (mig)
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl
# instance: default peripherals
set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen]
set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen

4
projects/common/kc705/kc705_system_bd.tcl
View File

@ -68,7 +68,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
# instance: microblaze- mdm
@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
# instance: ddr (mig)
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl

2
projects/common/kcu105/kcu105_system_bd.tcl
View File

@ -66,7 +66,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
# instance: microblaze- mdm

2
projects/common/mitx045/mitx045_system_bd.tcl
View File

@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

4
projects/common/vc707/vc707_system_bd.tcl
View File

@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
# instance: microblaze- mdm
@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
# instance: ddr (mig)
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl

2
projects/common/zc702/zc702_system_bd.tcl
View File

@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

2
projects/common/zc706/zc706_system_bd.tcl
View File

@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

2
projects/common/zc706/zc706_system_plddr3.tcl
View File

@ -31,7 +31,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} {
create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl

2
projects/common/zed/zed_system_bd.tcl
View File

@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

6
projects/daq2/a10gx/system_bd.qsys
View File

@ -313,7 +313,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
<parameter name="device" value="10AX115S3F45I2SGE2" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@ -418,7 +418,7 @@
type="reset"
dir="end" />
<module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_GENERATION_ID" value="0" />
@ -445,7 +445,7 @@
<parameter
name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
value="AddressWidth = 29" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_GENERATION_ID" value="0" />

107
projects/daq2/common/daq2_bd.qsys
View File

@ -413,6 +413,11 @@
value = "2";
type = "int";
}
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
}
element mem_rst
{
@ -421,6 +426,11 @@
value = "3";
type = "int";
}
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
}
element sys_clk
{
@ -429,6 +439,11 @@
value = "0";
type = "int";
}
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
}
element sys_rst
{
@ -437,6 +452,11 @@
value = "1";
type = "int";
}
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
}
element system_bd
{
@ -709,11 +729,16 @@
value = "4";
type = "int";
}
datum sopceditor_expanded
{
value = "1";
type = "boolean";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
<parameter name="device" value="10AX115S3F45I2SGE2" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@ -909,7 +934,7 @@
<module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
<parameter name="ADJCNT" value="0" />
<parameter name="ADJDIR" value="0" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45I2SG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="BID" value="0" />
<parameter name="CF" value="0" />
@ -957,8 +982,8 @@
<parameter name="bitrev_en" value="false" />
<parameter name="bonded_mode" value="non_bonded" />
<parameter name="lane_rate" value="10000.0" />
<parameter name="part_trait_bd" value="NIGHTFURY5ES2" />
<parameter name="part_trait_dp" value="10AX115S3F45I2SGE2" />
<parameter name="part_trait_bd" value="NIGHTFURY5" />
<parameter name="part_trait_dp" value="10AX115S2F45I2SG" />
<parameter name="pll_reconfig_enable" value="false" />
<parameter name="pll_type" value="CMU" />
<parameter name="rcfg_jtag_enable" value="false" />
@ -985,12 +1010,12 @@
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="1" />
<parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="T_PLL_LOCK_HYST" value="1000" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="40" />
<parameter name="T_TX_DIGITALRESET" value="4000" />
<parameter name="T_RX_ANALOGRESET" value="100000" />
<parameter name="T_RX_DIGITALRESET" value="100000" />
<parameter name="T_TX_ANALOGRESET" value="100000" />
<parameter name="T_TX_DIGITALRESET" value="100000" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="1" />
<parameter name="gui_rx_auto_reset" value="0" />
@ -1275,7 +1300,7 @@
<parameter name="gui_use_NDFB_modes" value="false" />
<parameter name="gui_use_locked" value="false" />
<parameter name="gui_vco_frequency" value="600.0" />
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
<parameter name="system_info_device_component" value="10AX115S2F45I2SG" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="2" />
<parameter name="system_part_trait_speed_grade" value="2" />
@ -1291,42 +1316,29 @@
</module>
<module
name="xcvr_tx_lane_pll"
kind="altera_xcvr_atx_pll_a10"
kind="altera_xcvr_cdr_pll_a10"
version="15.1"
enabled="1">
<parameter name="base_device" value="NIGHTFURY5ES2" />
<parameter name="bw_sel" value="medium" />
<parameter name="device" value="10AX115S3F45I2SGE2" />
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="Medium" />
<parameter name="cdr_pll_cgb_div" value="1" />
<parameter name="cdr_pll_initial_settings" value="true" />
<parameter name="cdr_pll_is_cascaded_pll" value="false" />
<parameter name="cdr_pll_optimal" value="false" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
<parameter name="diag_loopback_enable" value="false" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="1" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="generate_docs" value="1" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="mcgb_div" value="1" />
<parameter name="gui_tx_pll_prot_mode" value="Basic" />
<parameter name="manual_counters" value="" />
<parameter name="message_level" value="error" />
<parameter name="pma_width" value="64" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="output_clock_frequency" value="5000" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_file_prefix">altera_xcvr_cdr_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
@ -1340,25 +1352,14 @@
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="refclk_select_mux_powerdown_mode" value="powerup" />
<parameter name="reference_clock_frequency" value="500.0" />
<parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="500.0" />
<parameter name="set_altera_xcvr_cdr_pll_a10_calibration_en" value="1" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
<parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_cascade_predivider" value="1" />
<parameter name="set_l_counter" value="4" />
<parameter name="set_m_counter" value="50" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
<parameter name="set_output_clock_frequency" value="5000.0" />
<parameter name="set_ref_clk_div" value="1" />
<parameter name="set_user_identifier" value="0" />
<parameter name="silicon_rev" value="false" />
<parameter name="support_mode" value="user_mode" />
<parameter name="test_mode" value="0" />
</module>
<module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
<parameter name="gui_active_clk" value="false" />
@ -1638,7 +1639,7 @@
<parameter name="gui_use_NDFB_modes" value="false" />
<parameter name="gui_use_locked" value="false" />
<parameter name="gui_vco_frequency" value="600.0" />
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
<parameter name="system_info_device_component" value="10AX115S2F45I2SG" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="2" />
<parameter name="system_part_trait_speed_grade" value="2" />
@ -2006,8 +2007,8 @@
<connection
kind="conduit"
version="15.1"
start="xcvr_rst_cntrl.pll_cal_busy"
end="xcvr_tx_lane_pll.pll_cal_busy">
start="xcvr_tx_lane_pll.pll_cal_busy"
end="xcvr_rst_cntrl.pll_cal_busy">
<parameter name="endPort" value="" />
<parameter name="endPortLSB" value="0" />
<parameter name="startPort" value="" />

4
projects/daq2/common/daq2_bd.tcl
View File

@ -18,7 +18,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd]
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
@ -42,7 +42,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd

4
projects/daq3/common/daq3_bd.tcl
View File

@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n
set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9152_jesd]
set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd

2
projects/daq3/zc706/system_bd.tcl
View File

@ -30,7 +30,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc
set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc

2
projects/fmcadc2/common/fmcadc2_bd.tcl
View File

@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_jesd]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd

2
projects/fmcadc4/common/fmcadc4_bd.tcl
View File

@ -14,7 +14,7 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0
set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1]
set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd

2
projects/fmcadc4/zc706/system_bd.tcl
View File

@ -28,7 +28,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc
set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc

4
projects/fmcadc5/common/fmcadc5_bd.tcl
View File

@ -19,10 +19,10 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_0_jesd]
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_1_jesd]
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd

2
projects/fmcadc5/vc707/system_bd.tcl
View File

@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc
set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc
set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc

2
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
View File

@ -12,7 +12,7 @@ create_bd_port -dir I -from 3 -to 0 rx_data_n
set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9250_jesd]
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd

2
projects/fmcomms1/common/fmcomms1_bd.tcl
View File

@ -68,7 +68,7 @@
# reference clock
set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen]
set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen]
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen
set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen
set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen

4
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -168,7 +168,7 @@ ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
# ila (adc)
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
@ -188,7 +188,7 @@ ad_connect sys_cpu_clk ila_adc/clk
# ila (tdd)
set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tdd]
set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd

10
projects/fmcomms2/common/prcfg_bd.tcl
View File

@ -148,7 +148,7 @@ ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out
# rx side monitoring
set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_0]
set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0
@ -159,7 +159,7 @@ ad_connect sys_cpu_clk ila_rx_0/clk
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1
set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_1]
set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1
@ -205,7 +205,7 @@ ad_connect axi_ad9361/l_clk ila_tx_0/clk
ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0
ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1
set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_1]
set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1
@ -216,7 +216,7 @@ ad_connect axi_ad9361/l_clk ila_tx_1/clk
ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0
ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1
set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_2]
set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2
@ -227,7 +227,7 @@ ad_connect axi_ad9361/l_clk ila_tx_2/clk
ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0
ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1
set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_3]
set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3

4
projects/fmcomms7/common/fmcomms7_bd.tcl
View File

@ -26,7 +26,7 @@ create_bd_port -dir I spi2_sdi_i
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd]
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
@ -50,7 +50,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd

2
projects/imageon/common/imageon_bd.tcl
View File

@ -76,7 +76,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq
# debug
set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_fifo_dma_rx]
set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_fifo_dma_rx]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx
set_property -dict [list CONFIG.C_DATA_DEPTH {4096}] $ila_fifo_dma_rx

3
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
View File

@ -12,6 +12,7 @@
# current monitor interface
# clock
create_bd_port -dir O adc_clk_o
# data motor 1
create_bd_port -dir I adc_m1_ia_dat_i
create_bd_port -dir I adc_m1_ib_dat_i
@ -159,7 +160,7 @@
set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ]
# xadc
set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.1 xadc_core ]
set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_core ]
set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core
set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core
set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core

2
projects/pzsdr/common/ccfmc_bd.tcl
View File

@ -59,7 +59,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen

2
projects/pzsdr/common/ccpci_bd.tcl
View File

@ -49,7 +49,7 @@ ad_connect pl_gpio1_t axi_gpio/gpio2_io_t
# pci-express
set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.6 axi_pcie_x4]
set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 axi_pcie_x4]
set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4
set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4
set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4

2
projects/scripts/adi_project.tcl
View File

@ -7,7 +7,7 @@ variable p_prcfg_list
variable p_prcfg_status
if {![info exists REQUIRED_VIVADO_VERSION]} {
set REQUIRED_VIVADO_VERSION "2015.2.1"
set REQUIRED_VIVADO_VERSION "2015.4.2"
}
if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {

3
projects/usb_fx3/common/usb_fx3_bd.tcl
View File

@ -60,7 +60,8 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM
# test
set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila]
set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila
set_property -dict [list CONFIG.C_NUM_OF_PROBES {11}] $ila
set_property -dict [list CONFIG.C_PROBE10_WIDTH {4}] $ila

4
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -58,7 +58,7 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:
set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3
set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd]
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd
@ -300,7 +300,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq
# ila
set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_ad9671]
set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671
set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671
set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671