diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 1413a39b3..056eb2fb3 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -202,6 +202,8 @@ module axi_hdmi_tx ( wire [15:0] hdmi_vs_width_s; wire [15:0] hdmi_ve_max_s; wire [15:0] hdmi_ve_min_s; + wire [31:0] hdmi_clip_max_s; + wire [31:0] hdmi_clip_min_s; wire hdmi_fs_toggle_s; wire [ 8:0] hdmi_raddr_g_s; wire hdmi_tpm_oos_s; @@ -271,6 +273,8 @@ module axi_hdmi_tx ( .hdmi_vs_width (hdmi_vs_width_s), .hdmi_ve_max (hdmi_ve_max_s), .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s), .hdmi_status (hdmi_status_s), .hdmi_tpm_oos (hdmi_tpm_oos_s), .hdmi_clk_ratio (32'd1), @@ -356,7 +360,9 @@ module axi_hdmi_tx ( .hdmi_vf_width (hdmi_vf_width_s), .hdmi_vs_width (hdmi_vs_width_s), .hdmi_ve_max (hdmi_ve_max_s), - .hdmi_ve_min (hdmi_ve_min_s)); + .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s)); // hdmi output clock diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index 3831a821e..fd1ccf12c 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -97,7 +97,9 @@ module axi_hdmi_tx_core ( hdmi_vf_width, hdmi_vs_width, hdmi_ve_max, - hdmi_ve_min); + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min); // parameters @@ -164,6 +166,8 @@ module axi_hdmi_tx_core ( input [15:0] hdmi_vs_width; input [15:0] hdmi_ve_max; input [15:0] hdmi_ve_min; + input [23:0] hdmi_clip_max; + input [23:0] hdmi_clip_min; // internal registers @@ -205,12 +209,24 @@ module axi_hdmi_tx_core ( reg hdmi_vsync_data_e = 'd0; reg hdmi_data_e = 'd0; reg [23:0] hdmi_data = 'd0; + reg hdmi_24_csc_hsync = 'd0; + reg hdmi_24_csc_vsync = 'd0; + reg hdmi_24_csc_hsync_data_e = 'd0; + reg hdmi_24_csc_vsync_data_e = 'd0; + reg hdmi_24_csc_data_e = 'd0; + reg [23:0] hdmi_24_csc_data = 'd0; reg hdmi_24_hsync = 'd0; reg hdmi_24_vsync = 'd0; reg hdmi_24_hsync_data_e = 'd0; reg hdmi_24_vsync_data_e = 'd0; reg hdmi_24_data_e = 'd0; reg [23:0] hdmi_24_data = 'd0; + reg hdmi_24_hsync_ss = 'd0; + reg hdmi_24_vsync_ss = 'd0; + reg hdmi_24_hsync_data_e_ss = 'd0; + reg hdmi_24_vsync_data_e_ss = 'd0; + reg hdmi_24_data_e_ss = 'd0; + reg [23:0] hdmi_24_data_ss = 'd0; reg hdmi_16_hsync = 'd0; reg hdmi_16_vsync = 'd0; reg hdmi_16_hsync_data_e = 'd0; @@ -220,6 +236,12 @@ module axi_hdmi_tx_core ( reg hdmi_es_hs_de = 'd0; reg hdmi_es_vs_de = 'd0; reg [15:0] hdmi_es_data = 'd0; + reg [23:0] hdmi_clip_data = 'd0; + reg hdmi_clip_hs_de_d = 'd0; + reg hdmi_clip_vs_de_d = 'd0; + reg hdmi_clip_hs_d = 'd0; + reg hdmi_clip_vs_d = 'd0; + reg hdmi_clip_de_d = 'd0; // internal wires @@ -245,6 +267,10 @@ module axi_hdmi_tx_core ( wire hdmi_ss_vsync_data_e_s; wire hdmi_ss_data_e_s; wire [15:0] hdmi_ss_data_s; + wire hdmi_clip_hs_de_s; + wire hdmi_clip_vs_de_s; + wire hdmi_clip_de_s; + wire [23:0] hdmi_clip_data_s; wire hdmi_es_hs_de_s; wire hdmi_es_vs_de_s; wire hdmi_es_de_s; @@ -453,6 +479,68 @@ module axi_hdmi_tx_core ( endcase end + // Color space conversion bypass (RGB/YCbCr) + + always @(posedge hdmi_clk) begin + if (hdmi_csc_bypass == 1'b1) begin + hdmi_24_csc_hsync <= hdmi_hsync; + hdmi_24_csc_vsync <= hdmi_vsync; + hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e; + hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e; + hdmi_24_csc_data_e <= hdmi_data_e; + hdmi_24_csc_data <= hdmi_data; + end else begin + hdmi_24_csc_hsync <= hdmi_csc_hsync_s; + hdmi_24_csc_vsync <= hdmi_csc_vsync_s; + hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s; + hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s; + hdmi_24_csc_data_e <= hdmi_csc_data_e_s; + hdmi_24_csc_data <= hdmi_csc_data_s; + end + end + + // hdmi clipping + + assign hdmi_clip_data_s = hdmi_24_csc_data; + + always @(posedge hdmi_clk) begin + hdmi_clip_hs_d <= hdmi_24_csc_hsync; + hdmi_clip_vs_d <= hdmi_24_csc_vsync; + hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e; + hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e; + hdmi_clip_de_d <= hdmi_24_csc_data_e; + + // Cr (red-diff) / red + + if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_max[23:16]; + end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_min[23:16]; + end else begin + hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16]; + end + + // Y (luma) / green + + if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_max[15:8]; + end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_min[15:8]; + end else begin + hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8]; + end + + // Cb (blue-diff) / blue + + if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_max[7:0]; + end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_min[7:0]; + end else begin + hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0]; + end + end + // hdmi csc 16, 24 and 36 outputs assign hdmi_36_hsync = hdmi_24_hsync; @@ -463,21 +551,14 @@ module axi_hdmi_tx_core ( assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]}; always @(posedge hdmi_clk) begin - if (hdmi_csc_bypass == 1'b1) begin - hdmi_24_hsync <= hdmi_hsync; - hdmi_24_vsync <= hdmi_vsync; - hdmi_24_hsync_data_e <= hdmi_hsync_data_e; - hdmi_24_vsync_data_e <= hdmi_vsync_data_e; - hdmi_24_data_e <= hdmi_data_e; - hdmi_24_data <= hdmi_data; - end else begin - hdmi_24_hsync <= hdmi_csc_hsync_s; - hdmi_24_vsync <= hdmi_csc_vsync_s; - hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s; - hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s; - hdmi_24_data_e <= hdmi_csc_data_e_s; - hdmi_24_data <= hdmi_csc_data_s; - end + + hdmi_24_hsync <= hdmi_clip_hs_d; + hdmi_24_vsync <= hdmi_clip_vs_d; + hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d; + hdmi_24_vsync_data_e <= hdmi_clip_vs_de_d; + hdmi_24_data_e <= hdmi_clip_de_d; + hdmi_24_data <= hdmi_clip_data; + if (hdmi_ss_bypass == 1'b1) begin hdmi_16_hsync <= hdmi_24_hsync; hdmi_16_vsync <= hdmi_24_vsync; @@ -495,7 +576,7 @@ module axi_hdmi_tx_core ( end end - // hdmi embedded sync clipping + // hdmi embedded sync assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e; assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e; @@ -507,31 +588,11 @@ module axi_hdmi_tx_core ( hdmi_es_vs_de <= hdmi_es_vs_de_s; if (hdmi_es_de_s == 1'b0) begin hdmi_es_data[15:8] <= 8'h80; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[15:8] > 8'heb)) begin - hdmi_es_data[15:8] <= 8'heb; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[15:8] < 8'h10)) begin - hdmi_es_data[15:8] <= 8'h10; - end else if (hdmi_es_data_s[15:8] > 8'hfe) begin - hdmi_es_data[15:8] <= 8'hfe; - end else if (hdmi_es_data_s[15:8] < 8'h01) begin - hdmi_es_data[15:8] <= 8'h01; end else begin hdmi_es_data[15:8] <= hdmi_es_data_s[15:8]; end if (hdmi_es_de_s == 1'b0) begin hdmi_es_data[7:0] <= 8'h80; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[7:0] > 8'heb)) begin - hdmi_es_data[7:0] <= 8'heb; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[7:0] < 8'h10)) begin - hdmi_es_data[7:0] <= 8'h10; - end else if (hdmi_es_data_s[7:0] > 8'hfe) begin - hdmi_es_data[7:0] <= 8'hfe; - end else if (hdmi_es_data_s[7:0] < 8'h01) begin - hdmi_es_data[7:0] <= 8'h01; end else begin hdmi_es_data[7:0] <= hdmi_es_data_s[7:0]; end @@ -569,13 +630,13 @@ module axi_hdmi_tx_core ( ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 ( .clk (hdmi_clk), - .s444_de (hdmi_24_data_e), - .s444_sync ({hdmi_24_hsync, - hdmi_24_vsync, - hdmi_24_hsync_data_e, - hdmi_24_vsync_data_e, - hdmi_24_data_e}), - .s444_data (hdmi_24_data), + .s444_de (hdmi_clip_de_d), + .s444_sync ({hdmi_clip_hs_d, + hdmi_clip_vs_d, + hdmi_clip_hs_de_d, + hdmi_clip_vs_de_d, + hdmi_clip_de_d}), + .s444_data (hdmi_clip_data), .s422_sync ({hdmi_ss_hsync_s, hdmi_ss_vsync_s, hdmi_ss_hsync_data_e_s, diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index 7b036d481..d30ec0834 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -19,7 +19,7 @@ adi_ip_files axi_i2s_adi [list \ "axi_i2s_adi_constr.xdc" \ ] -adi_ip_properties_lite axi_i2s_adi +adi_ip_properties axi_i2s_adi adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late adi_add_bus "DMA_ACK_RX" "slave" \ @@ -30,6 +30,7 @@ adi_add_bus "DMA_ACK_RX" "slave" \ {"DMA_REQ_RX_DAREADY" "TREADY"} \ {"DMA_REQ_RX_DATYPE" "TUSER"} \ } + adi_add_bus "DMA_REQ_RX" "master" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ @@ -95,8 +96,9 @@ adi_set_ports_dependency "DMA_REQ_RX_ACLK" \ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] +ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 41085bfbe..0612f9e6b 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -668,8 +668,8 @@ module axi_jesd_gt #( // axi - clock & reset - input axi_aclk, - input axi_aresetn, + input s_axi_aclk, + input s_axi_aresetn, // axi interface @@ -831,8 +831,8 @@ module axi_jesd_gt #( // signal name changes - assign up_rstn = axi_aresetn; - assign up_clk = axi_aclk; + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; // pll diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl index 558c74b07..79688653b 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl @@ -24,16 +24,7 @@ adi_ip_properties axi_jesd_gt adi_ip_constraints axi_jesd_gt [list \ "axi_jesd_gt_constr.xdc" ] -ipx::remove_bus_interface qpll0_rst [ipx::current_core] -ipx::remove_bus_interface qpll1_rst [ipx::current_core] - -set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ - -of_objects [ipx::get_bus_interfaces axi_aclk \ - -of_objects [ipx::current_core]]] - -set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces axi_aclk \ - -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core] adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \ "qpll_rst qpll0_rst "\ diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl index edbe7f930..9b22be7d6 100644 --- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl +++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -16,7 +16,7 @@ adi_ip_files axi_spdif_rx [list \ "axi_spdif_rx.vhd" \ "axi_spdif_rx_constr.xdc"] -adi_ip_properties_lite axi_spdif_rx +adi_ip_properties axi_spdif_rx adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ @@ -49,4 +49,5 @@ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" ipx::save_core [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index 19d2d7c70..fdc4c38c3 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -14,7 +14,7 @@ adi_ip_files axi_spdif_tx [list \ "axi_spdif_tx.vhd" \ "axi_spdif_tx_constr.xdc" ] -adi_ip_properties_lite axi_spdif_tx +adi_ip_properties axi_spdif_tx adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ @@ -46,8 +46,7 @@ adi_set_ports_dependency "DMA_REQ_ACLK" \ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]] - +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index f63f93d60..e1750e76b 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -58,6 +58,8 @@ module up_hdmi_tx ( hdmi_vs_width, hdmi_ve_max, hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min, hdmi_status, hdmi_tpm_oos, hdmi_clk_ratio, @@ -107,6 +109,8 @@ module up_hdmi_tx ( output [15:0] hdmi_vs_width; output [15:0] hdmi_ve_max; output [15:0] hdmi_ve_min; + output [23:0] hdmi_clip_max; + output [23:0] hdmi_clip_min; input hdmi_status; input hdmi_tpm_oos; input [31:0] hdmi_clk_ratio; @@ -157,6 +161,8 @@ module up_hdmi_tx ( reg [15:0] up_vs_width = 'd0; reg [15:0] up_ve_max = 'd0; reg [15:0] up_ve_min = 'd0; + reg [23:0] up_clip_max = 'd0; + reg [23:0] up_clip_min = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; @@ -203,6 +209,8 @@ module up_hdmi_tx ( up_vs_width <= 'd0; up_ve_max <= 'd0; up_ve_min <= 'd0; + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; end else begin up_core_preset <= ~up_resetn; up_wack <= up_wreq_s; @@ -243,6 +251,21 @@ module up_hdmi_tx ( end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin + if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin + up_clip_max <= 24'hfefefe; + up_clip_min <= 24'h010101; + end else begin + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; + end + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin + up_clip_max <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin + up_clip_min <= up_wdata[23:0]; + end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin up_hl_active <= up_wdata[31:16]; up_hl_width <= up_wdata[15:0]; @@ -290,6 +313,9 @@ module up_hdmi_tx ( 12'h017: up_rdata <= {31'd0, up_hdmi_status_s}; 12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf}; 12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos}; + 12'h01a: up_rdata <= {8'd0, up_clip_max}; + 12'h01b: up_rdata <= {8'd0, up_clip_min}; + 12'h100: up_rdata <= {up_hl_active, up_hl_width}; 12'h101: up_rdata <= {16'd0, up_hs_width}; 12'h102: up_rdata <= {up_he_max, up_he_min}; @@ -311,7 +337,7 @@ module up_hdmi_tx ( // hdmi control & status - up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_ss_bypass, @@ -328,7 +354,9 @@ module up_hdmi_tx ( up_vf_width, up_vs_width, up_ve_max, - up_ve_min}), + up_ve_min, + up_clip_max, + up_clip_min}), .up_xfer_done (), .d_rst (hdmi_rst), .d_clk (hdmi_clk), @@ -346,7 +374,9 @@ module up_hdmi_tx ( hdmi_vf_width, hdmi_vs_width, hdmi_ve_max, - hdmi_ve_min})); + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min})); up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status ( .up_rstn (up_rstn), diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index bd443c882..f9d416a59 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -2,7 +2,7 @@ # check tool version if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.2.1" + set REQUIRED_VIVADO_VERSION "2015.4.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { @@ -78,13 +78,6 @@ proc adi_ip_bd {ip_name ip_bd_files} { proc adi_ip_properties {ip_name} { ipx::package_project -root_dir . - ipx::remove_memory_map {s_axi} [ipx::current_core] - ipx::add_memory_map {s_axi} [ipx::current_core] - set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] - - ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] - set_property range {65536} [ipx::get_address_blocks axi_lite \ - -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] set_property vendor {analog.com} [ipx::current_core] set_property library {user} [ipx::current_core] @@ -109,6 +102,47 @@ proc adi_ip_properties {ip_name} { {qzynq} {Production} \ {azynq} {Production}} \ [ipx::current_core] + + ipx::remove_all_bus_interface [ipx::current_core] + ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ + xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + + ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::add_memory_map {s_axi} [ipx::current_core] + set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] + ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] + set_property range {65536} [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] + set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + + ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] } proc adi_ip_properties_lite {ip_name} { diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl index 48710bf7c..be06aa5d8 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -15,9 +15,8 @@ adi_ip_constraints util_gmii_to_rgmii [list \ "util_gmii_to_rgmii_constr.xdc" ] ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] -set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]] +set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]] ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] -set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces reset -of_objects [ipx::current_core]]] set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index ed30915dc..11d73bd7f 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -11,7 +11,7 @@ create_bd_port -dir I -from 1 -to 0 rx_data_n set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] -set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad6676_jesd] +set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd diff --git a/projects/adv7511/common/adv7511_bd.tcl b/projects/adv7511/common/adv7511_bd.tcl index 1d94c1e4f..51b9c2ab3 100755 --- a/projects/adv7511/common/adv7511_bd.tcl +++ b/projects/adv7511/common/adv7511_bd.tcl @@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl index 3e685aefb..0bb026b18 100755 --- a/projects/common/a10gx/a10gx_system_assign.tcl +++ b/projects/common/a10gx/a10gx_system_assign.tcl @@ -2,7 +2,7 @@ # device settings set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name DEVICE 10AX115S3F45I2SGE2 +set_global_assignment -name DEVICE 10AX115S2F45I2SG # clocks and resets diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys index e45c2bfc7..edbe253f0 100644 --- a/projects/common/a10gx/a10gx_system_bd.qsys +++ b/projects/common/a10gx/a10gx_system_bd.qsys @@ -601,7 +601,7 @@ } ]]> - + @@ -733,7 +733,7 @@ - + @@ -1862,14 +1862,14 @@ - + $${FILENAME}_sys_ddr3_cntrl - + @@ -1922,7 +1922,7 @@ - + @@ -1968,7 +1968,7 @@ - + ]]> diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 32439a5a4..2ee349106 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -62,7 +62,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl # instance: default peripherals -set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen] +set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 50d907d5b..f762c2b5d 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -68,7 +68,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 512058517..80fc8619d 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -66,7 +66,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index ce55e0b17..c114e8302 100644 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 2ddd6d1ba..37c94841f 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 6b1359b0e..bbcf32a50 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 04aead65f..49380211b 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index 1b634937f..fc27c4b3f 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -31,7 +31,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { create_bd_pin -dir I dma_xfer_req create_bd_pin -dir O -from 3 -to 0 dma_xfer_status - set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] + set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 09bed96d4..57e47c751 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys index 9f991b1ec..404b3413b 100755 --- a/projects/daq2/a10gx/system_bd.qsys +++ b/projects/daq2/a10gx/system_bd.qsys @@ -313,7 +313,7 @@ } ]]> - + @@ -418,7 +418,7 @@ type="reset" dir="end" /> - + @@ -445,7 +445,7 @@ - + diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys index 0f76e66a9..fcabfb523 100755 --- a/projects/daq2/common/daq2_bd.qsys +++ b/projects/daq2/common/daq2_bd.qsys @@ -413,6 +413,11 @@ value = "2"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element mem_rst { @@ -421,6 +426,11 @@ value = "3"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sys_clk { @@ -429,6 +439,11 @@ value = "0"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sys_rst { @@ -437,6 +452,11 @@ value = "1"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element system_bd { @@ -709,11 +729,16 @@ value = "4"; type = "int"; } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } } } ]]> - + @@ -909,7 +934,7 @@ - + @@ -957,8 +982,8 @@ - - + + @@ -985,12 +1010,12 @@ - + - - - - + + + + @@ -1275,7 +1300,7 @@ - + @@ -1291,42 +1316,29 @@ - - - + + + + + + + - - + - - - - - - - - - - - - - - - - + + - - GX clock output buffer - + - altera_xcvr_atx_pll_a10 + altera_xcvr_cdr_pll_a10 @@ -1340,25 +1352,14 @@ + + - - + - - - - - - - - - - - - @@ -1638,7 +1639,7 @@ - + @@ -2006,8 +2007,8 @@ + start="xcvr_tx_lane_pll.pll_cal_busy" + end="xcvr_rst_cntrl.pll_cal_busy"> diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index b84a71984..d9c58fdd2 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -18,7 +18,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd] +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd @@ -42,7 +42,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index cfb78a5b8..2eb48bf37 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] -set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9152_jesd] +set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd @@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 8332b3431..655c77173 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -30,7 +30,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index fb1242f1a..7d684044d 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core] -set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_jesd] +set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index 0129b4031..ae3537bd6 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -14,7 +14,7 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1 -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 8e6e65c6c..06ae1973f 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -28,7 +28,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index aaaaa83e7..4b3d0c793 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -19,10 +19,10 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core] set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core -set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_0_jesd] +set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd -set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_1_jesd] +set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl index 40dab996c..6ca32626b 100644 --- a/projects/fmcadc5/vc707/system_bd.tcl +++ b/projects/fmcadc5/vc707/system_bd.tcl @@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index f41f56c89..098001461 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -12,7 +12,7 @@ create_bd_port -dir I -from 3 -to 0 rx_data_n set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core] set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core] -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9250_jesd] +set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 2694abc46..826ecaaf8 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -68,7 +68,7 @@ # reference clock - set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen] + set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen] set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 5e35d8875..b74ba6e76 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -168,7 +168,7 @@ ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq # ila (adc) -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc @@ -188,7 +188,7 @@ ad_connect sys_cpu_clk ila_adc/clk # ila (tdd) -set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tdd] +set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd diff --git a/projects/fmcomms2/common/prcfg_bd.tcl b/projects/fmcomms2/common/prcfg_bd.tcl index e75a63d93..d7313adcc 100644 --- a/projects/fmcomms2/common/prcfg_bd.tcl +++ b/projects/fmcomms2/common/prcfg_bd.tcl @@ -148,7 +148,7 @@ ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out # rx side monitoring -set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_0] +set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0 @@ -159,7 +159,7 @@ ad_connect sys_cpu_clk ila_rx_0/clk ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0 ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1 -set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_1] +set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1 @@ -205,7 +205,7 @@ ad_connect axi_ad9361/l_clk ila_tx_0/clk ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0 ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1 -set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_1] +set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1 @@ -216,7 +216,7 @@ ad_connect axi_ad9361/l_clk ila_tx_1/clk ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0 ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1 -set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_2] +set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2 @@ -227,7 +227,7 @@ ad_connect axi_ad9361/l_clk ila_tx_2/clk ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0 ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1 -set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_3] +set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3 diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index e0175ccdc..59e3cce66 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -26,7 +26,7 @@ create_bd_port -dir I spi2_sdi_i set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd] +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd @@ -50,7 +50,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl index ec5784c68..412705ab3 100644 --- a/projects/imageon/common/imageon_bd.tcl +++ b/projects/imageon/common/imageon_bd.tcl @@ -76,7 +76,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq # debug -set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_fifo_dma_rx] +set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_fifo_dma_rx] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx set_property -dict [list CONFIG.C_DATA_DEPTH {4096}] $ila_fifo_dma_rx diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 795f26750..1cdf24f90 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -12,6 +12,7 @@ # current monitor interface # clock create_bd_port -dir O adc_clk_o + # data motor 1 create_bd_port -dir I adc_m1_ia_dat_i create_bd_port -dir I adc_m1_ib_dat_i @@ -159,7 +160,7 @@ set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] # xadc - set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.1 xadc_core ] + set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_core ] set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl index 96ca5123f..df1e8573a 100644 --- a/projects/pzsdr/common/ccfmc_bd.tcl +++ b/projects/pzsdr/common/ccfmc_bd.tcl @@ -59,7 +59,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/pzsdr/common/ccpci_bd.tcl b/projects/pzsdr/common/ccpci_bd.tcl index f2961a025..6662565ec 100644 --- a/projects/pzsdr/common/ccpci_bd.tcl +++ b/projects/pzsdr/common/ccpci_bd.tcl @@ -49,7 +49,7 @@ ad_connect pl_gpio1_t axi_gpio/gpio2_io_t # pci-express -set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.6 axi_pcie_x4] +set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 axi_pcie_x4] set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4 set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4 set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4 diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index d0c8a5242..335ed839b 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -7,7 +7,7 @@ variable p_prcfg_list variable p_prcfg_status if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.2.1" + set REQUIRED_VIVADO_VERSION "2015.4.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl index 9d8a9af56..19d31f2c4 100644 --- a/projects/usb_fx3/common/usb_fx3_bd.tcl +++ b/projects/usb_fx3/common/usb_fx3_bd.tcl @@ -60,7 +60,8 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM # test -set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila] +set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila set_property -dict [list CONFIG.C_NUM_OF_PROBES {11}] $ila set_property -dict [list CONFIG.C_PROBE10_WIDTH {4}] $ila diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index d71659a1a..4b9f89177 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -58,7 +58,7 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671: set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3 set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3 -set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd] +set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd @@ -300,7 +300,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq # ila -set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_ad9671] +set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671 set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671