From 2524f19ae0c989e9b46592e7b17eecaa64e8fd39 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 7 Mar 2016 12:31:41 +0200 Subject: [PATCH 01/44] Updated interfaces Makefile and Makefiles for the libraries that depend on it --- library/axi_jesd_gt/Makefile | 16 ++++++++-- library/interfaces/Makefile | 55 ++++++++++++++++++++++++++--------- library/util_gtlb/Makefile | 14 +++++++-- library/util_jesd_gt/Makefile | 14 +++++++-- 4 files changed, 79 insertions(+), 20 deletions(-) diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile index 3ac3a89de..e8fdc5069 100644 --- a/library/axi_jesd_gt/Makefile +++ b/library/axi_jesd_gt/Makefile @@ -21,6 +21,16 @@ M_DEPS += ../common/up_gt_channel.v M_DEPS += ../common/up_gt.v M_DEPS += axi_jesd_gt_constr.xdc M_DEPS += axi_jesd_gt.v +M_DEPS += ../interfaces/if_gt_qpll.xml +M_DEPS += ../interfaces/if_gt_qpll_rtl.xml +M_DEPS += ../interfaces/if_gt_pll.xml +M_DEPS += ../interfaces/if_gt_pll_rtl.xml +M_DEPS += ../interfaces/if_gt_rx.xml +M_DEPS += ../interfaces/if_gt_rx_rtl.xml +M_DEPS += ../interfaces/if_gt_rx_ksig.xml +M_DEPS += ../interfaces/if_gt_rx_ksig_rtl.xml +M_DEPS += ../interfaces/if_gt_tx.xml +M_DEPS += ../interfaces/if_gt_tx_rtl.xml M_VIVADO := vivado -mode batch -source @@ -35,8 +45,8 @@ M_FLIST += .Xil -.PHONY: all clean clean-all -all: axi_jesd_gt.xpr +.PHONY: all dep clean clean-all +all: dep axi_jesd_gt.xpr clean:clean-all @@ -50,5 +60,7 @@ axi_jesd_gt.xpr: $(M_DEPS) rm -rf $(M_FLIST) $(M_VIVADO) axi_jesd_gt_ip.tcl >> axi_jesd_gt_ip.log 2>&1 +dep: + make -C ../interfaces #################################################################################### #################################################################################### diff --git a/library/interfaces/Makefile b/library/interfaces/Makefile index cb50c9c27..996cec8d9 100644 --- a/library/interfaces/Makefile +++ b/library/interfaces/Makefile @@ -11,31 +11,58 @@ M_DEPS += ../scripts/adi_ip.tcl M_VIVADO := vivado -mode batch -source -M_FLIST := *.cache -M_FLIST += *.data -M_FLIST += *.xpr -M_FLIST += *.log -M_FLIST += component.xml +M_FLIST := *.log M_FLIST += *.jou -M_FLIST += xgui -M_FLIST += .Xil - +M_FLIST += if_gt_qpll.xml +M_FLIST += if_gt_qpll_rtl.xml +M_FLIST += if_gt_pll.xml +M_FLIST += if_gt_pll_rtl.xml +M_FLIST += if_gt_rx.xml +M_FLIST += if_gt_rx_rtl.xml +M_FLIST += if_gt_tx.xml +M_FLIST += if_gt_tx_rtl.xml +M_FLIST += if_gt_rx_ksig.xml +M_FLIST += if_gt_rx_ksig_rtl.xml .PHONY: all clean clean-all -all: interfaces.xpr - +all: if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml clean:clean-all - clean-all: rm -rf $(M_FLIST) +if_gt_qpll.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_qpll_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_pll.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_pll_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_rx.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_rx_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_tx.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_tx_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_rx_ksig.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_gt_rx_ksig_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 -interfaces.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 #################################################################################### #################################################################################### diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile index 3f3542448..8dc22b792 100644 --- a/library/util_gtlb/Makefile +++ b/library/util_gtlb/Makefile @@ -11,6 +11,14 @@ M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/up_xfer_status.v M_DEPS += util_gtlb_constr.xdc M_DEPS += util_gtlb.v +M_DEPS += ../interfaces/if_gt_qpll.xml +M_DEPS += ../interfaces/if_gt_qpll_rtl.xml +M_DEPS += ../interfaces/if_gt_pll.xml +M_DEPS += ../interfaces/if_gt_pll_rtl.xml +M_DEPS += ../interfaces/if_gt_rx.xml +M_DEPS += ../interfaces/if_gt_rx_rtl.xml +M_DEPS += ../interfaces/if_gt_tx.xml +M_DEPS += ../interfaces/if_gt_tx_rtl.xml M_VIVADO := vivado -mode batch -source @@ -25,8 +33,8 @@ M_FLIST += .Xil -.PHONY: all clean clean-all -all: util_gtlb.xpr +.PHONY: all dep clean clean-all +all: dep util_gtlb.xpr clean:clean-all @@ -40,5 +48,7 @@ util_gtlb.xpr: $(M_DEPS) rm -rf $(M_FLIST) $(M_VIVADO) util_gtlb_ip.tcl >> util_gtlb_ip.log 2>&1 +dep: + make -C ../interfaces #################################################################################### #################################################################################### diff --git a/library/util_jesd_gt/Makefile b/library/util_jesd_gt/Makefile index 618434618..c78666c37 100644 --- a/library/util_jesd_gt/Makefile +++ b/library/util_jesd_gt/Makefile @@ -9,6 +9,14 @@ M_DEPS := util_jesd_gt_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_jesd_gt.v +M_DEPS += ../interfaces/if_gt_qpll.xml +M_DEPS += ../interfaces/if_gt_qpll_rtl.xml +M_DEPS += ../interfaces/if_gt_pll.xml +M_DEPS += ../interfaces/if_gt_pll_rtl.xml +M_DEPS += ../interfaces/if_gt_rx.xml +M_DEPS += ../interfaces/if_gt_rx_rtl.xml +M_DEPS += ../interfaces/if_gt_tx.xml +M_DEPS += ../interfaces/if_gt_tx_rtl.xml M_VIVADO := vivado -mode batch -source @@ -23,8 +31,8 @@ M_FLIST += .Xil -.PHONY: all clean clean-all -all: util_jesd_gt.xpr +.PHONY: all dep clean clean-all +all: dep util_jesd_gt.xpr clean:clean-all @@ -38,5 +46,7 @@ util_jesd_gt.xpr: $(M_DEPS) rm -rf $(M_FLIST) $(M_VIVADO) util_jesd_gt_ip.tcl >> util_jesd_gt_ip.log 2>&1 +dep: + make -C ../interfaces #################################################################################### #################################################################################### From 31cc91d1b922cc4456e8a16d3886ef1faaa37540 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 14 Mar 2016 15:14:18 +0200 Subject: [PATCH 02/44] adi_ip: Updated to 2014.4.2 - automatically infer clocks, resets, axim_mm and axis interfaces --- library/scripts/adi_ip.tcl | 50 ++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index bd443c882..f9d416a59 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -2,7 +2,7 @@ # check tool version if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.2.1" + set REQUIRED_VIVADO_VERSION "2015.4.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { @@ -78,13 +78,6 @@ proc adi_ip_bd {ip_name ip_bd_files} { proc adi_ip_properties {ip_name} { ipx::package_project -root_dir . - ipx::remove_memory_map {s_axi} [ipx::current_core] - ipx::add_memory_map {s_axi} [ipx::current_core] - set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] - - ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] - set_property range {65536} [ipx::get_address_blocks axi_lite \ - -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] set_property vendor {analog.com} [ipx::current_core] set_property library {user} [ipx::current_core] @@ -109,6 +102,47 @@ proc adi_ip_properties {ip_name} { {qzynq} {Production} \ {azynq} {Production}} \ [ipx::current_core] + + ipx::remove_all_bus_interface [ipx::current_core] + ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ + xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + + ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::add_memory_map {s_axi} [ipx::current_core] + set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] + ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] + set_property range {65536} [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] + set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + + ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] } proc adi_ip_properties_lite {ip_name} { From b3ed38107cf590749200350e538fe57fa35478d5 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 10:12:45 +0200 Subject: [PATCH 03/44] axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred --- library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index 7b036d481..0cd080c5e 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -19,7 +19,7 @@ adi_ip_files axi_i2s_adi [list \ "axi_i2s_adi_constr.xdc" \ ] -adi_ip_properties_lite axi_i2s_adi +adi_ip_properties axi_i2s_adi adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late adi_add_bus "DMA_ACK_RX" "slave" \ @@ -30,6 +30,7 @@ adi_add_bus "DMA_ACK_RX" "slave" \ {"DMA_REQ_RX_DAREADY" "TREADY"} \ {"DMA_REQ_RX_DATYPE" "TUSER"} \ } + adi_add_bus "DMA_REQ_RX" "master" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ @@ -95,8 +96,8 @@ adi_set_ports_dependency "DMA_REQ_RX_ACLK" \ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] + ipx::save_core [ipx::current_core] From ef05642e26d79061ce415dc5e4175fc8220ce277 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 10:14:05 +0200 Subject: [PATCH 04/44] axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred --- library/axi_spdif_rx/axi_spdif_rx_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl index edbe7f930..b66848df5 100644 --- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl +++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -16,7 +16,7 @@ adi_ip_files axi_spdif_rx [list \ "axi_spdif_rx.vhd" \ "axi_spdif_rx_constr.xdc"] -adi_ip_properties_lite axi_spdif_rx +adi_ip_properties axi_spdif_rx adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ From 06b79163030471fd0a18d77da97b9b3886ba01dd Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 10:18:25 +0200 Subject: [PATCH 05/44] axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred --- library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index 19d2d7c70..8b27f16fd 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -14,7 +14,7 @@ adi_ip_files axi_spdif_tx [list \ "axi_spdif_tx.vhd" \ "axi_spdif_tx_constr.xdc" ] -adi_ip_properties_lite axi_spdif_tx +adi_ip_properties axi_spdif_tx adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ @@ -46,8 +46,7 @@ adi_set_ports_dependency "DMA_REQ_ACLK" \ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] ipx::save_core [ipx::current_core] From 9b2a106aa0cf0b80ee3fb589fcc40d693015f6f9 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 11:20:31 +0200 Subject: [PATCH 06/44] axi_jesd_gt: changed clock and reset naming to be consistent with the other projects --- library/axi_jesd_gt/axi_jesd_gt.v | 8 ++++---- library/axi_jesd_gt/axi_jesd_gt_ip.tcl | 11 +---------- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 41085bfbe..0612f9e6b 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -668,8 +668,8 @@ module axi_jesd_gt #( // axi - clock & reset - input axi_aclk, - input axi_aresetn, + input s_axi_aclk, + input s_axi_aresetn, // axi interface @@ -831,8 +831,8 @@ module axi_jesd_gt #( // signal name changes - assign up_rstn = axi_aresetn; - assign up_clk = axi_aclk; + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; // pll diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl index 558c74b07..79688653b 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl @@ -24,16 +24,7 @@ adi_ip_properties axi_jesd_gt adi_ip_constraints axi_jesd_gt [list \ "axi_jesd_gt_constr.xdc" ] -ipx::remove_bus_interface qpll0_rst [ipx::current_core] -ipx::remove_bus_interface qpll1_rst [ipx::current_core] - -set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ - -of_objects [ipx::get_bus_interfaces axi_aclk \ - -of_objects [ipx::current_core]]] - -set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces axi_aclk \ - -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core] adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \ "qpll_rst qpll0_rst "\ From 71be9519ecc91248c7d51ca283b9e8149efa9316 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:03:50 +0200 Subject: [PATCH 07/44] adi_project.tcl: Updated to 2015.4 --- projects/scripts/adi_project.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index 92d64577a..15e76142f 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -7,7 +7,7 @@ variable p_prcfg_list variable p_prcfg_status if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.2.1" + set REQUIRED_VIVADO_VERSION "2015.4.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { From d28206410316507e97179911aeaf68686113c4f2 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:16:36 +0200 Subject: [PATCH 08/44] zc706: Updated common design to 2015.4 --- projects/common/zc706/zc706_system_bd.tcl | 2 +- projects/common/zc706/zc706_system_plddr3.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 04aead65f..49380211b 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index 38bc92777..799f55021 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -31,7 +31,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { create_bd_pin -dir I dma_xfer_req create_bd_pin -dir O -from 3 -to 0 dma_xfer_status - set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] + set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl From eb743e0e0371eb2e20f915bb4a5bb900f8626725 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:17:02 +0200 Subject: [PATCH 09/44] ac701: Updated common design to 2015.4 --- projects/common/ac701/ac701_system_bd.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 32439a5a4..2ee349106 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -62,7 +62,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl # instance: default peripherals -set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen] +set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen From 27f5f1dcbe0f3d55c72f2a20e4431c99e481bdd4 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:17:53 +0200 Subject: [PATCH 10/44] kc705: Updated common design to 2015.4 --- projects/common/kc705/kc705_system_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 50d907d5b..f762c2b5d 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -68,7 +68,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl From bcf5bd8137c20219a9c6e3b5635c32a9d4fca490 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:18:31 +0200 Subject: [PATCH 11/44] mitx045: Updated common design to 2015.4 --- projects/common/mitx045/mitx045_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index ce55e0b17..c114e8302 100644 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen From 9a258d5e4c7dc0089393c3f8ceab3bf2a2db45d9 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:20:02 +0200 Subject: [PATCH 12/44] vc707: Updated common design to 2015.4 --- projects/common/vc707/vc707_system_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 2ddd6d1ba..37c94841f 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl From a0c5f469404577cd7f89471b17bdb786a3b399c2 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:20:46 +0200 Subject: [PATCH 13/44] zed: Updated common design to 2015.4 --- projects/common/zed/zed_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 09bed96d4..57e47c751 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen From 6f03998b95981d860559894aa1d1d50e5d7cae25 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:21:22 +0200 Subject: [PATCH 14/44] zc702: Updated common design to 2015.4 --- projects/common/zc702/zc702_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 6b1359b0e..bbcf32a50 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen From ceea7f25b2815533f9eace754a7552223e66f011 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:23:20 +0200 Subject: [PATCH 15/44] fmcomms2: Updated common design to 2015.4 --- projects/fmcomms2/common/fmcomms2_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 17419f02f..6741c7c8b 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -168,7 +168,7 @@ ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq # ila (adc) -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc @@ -188,7 +188,7 @@ ad_connect sys_cpu_clk ila_adc/clk # ila (tdd) -set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tdd] +set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd From 98cc7dad7d5ff8c34e670383b3c520877f98b87c Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:26:05 +0200 Subject: [PATCH 16/44] fmcadc2: Updated common design to 2015.4 --- projects/fmcadc2/common/fmcadc2_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index fb1242f1a..7d684044d 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core] -set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_jesd] +set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd From e8dd5f9788a342b0adcc6b8d60e76eba0a3c5410 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:27:25 +0200 Subject: [PATCH 17/44] fmcadc4: Updated common design to 2015.4 --- projects/fmcadc4/common/fmcadc4_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index a18f2ca6d..8077399da 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -14,7 +14,7 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1 -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd From 334fce03a3c1e204a6df691b55b8acd96551b6bc Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Mar 2016 15:28:11 +0200 Subject: [PATCH 18/44] fmcadc4/zc706: Updated design to 2015.4 --- projects/fmcadc4/zc706/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 8e6e65c6c..06ae1973f 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -28,7 +28,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc From b7be089b82cc68099e1966b9ce702552dc967fa0 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 16 Mar 2016 10:02:42 +0200 Subject: [PATCH 19/44] daq2: Updated common design to 2015.4 --- projects/daq2/common/daq2_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 794f33c09..849f18e5c 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -18,7 +18,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd] +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd @@ -42,7 +42,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd From 1a3aab0c133f5f2ddee8c8305876275c640b6dad Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 16 Mar 2016 10:09:54 +0200 Subject: [PATCH 20/44] fmcomms1: Updated common design to 2015.4 --- projects/fmcomms1/common/fmcomms1_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 2694abc46..826ecaaf8 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -68,7 +68,7 @@ # reference clock - set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen] + set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen] set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen From 59c726ecbe7b5b4ef1e9d7bd81959d2a1441b2ed Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 16 Mar 2016 10:14:06 +0200 Subject: [PATCH 21/44] fmcjesdadc1: Updated common design to 2015.4 --- projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index f41f56c89..098001461 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -12,7 +12,7 @@ create_bd_port -dir I -from 3 -to 0 rx_data_n set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core] set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core] -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9250_jesd] +set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd From abc03fff2cf040605a3a9f3b4784ac94af731710 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 17 Mar 2016 09:11:41 +0200 Subject: [PATCH 22/44] fmcomms7: Updated design to 2015.4 --- projects/fmcomms7/common/fmcomms7_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index e0175ccdc..59e3cce66 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -26,7 +26,7 @@ create_bd_port -dir I spi2_sdi_i set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd] +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd @@ -50,7 +50,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd From 38c3f7474a79da7332f4eb5c40c05792d37af059 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 17 Mar 2016 11:40:46 +0200 Subject: [PATCH 23/44] ad6676: Updated common design to 2015.4 --- projects/ad6676evb/common/ad6676evb_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index ed30915dc..11d73bd7f 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -11,7 +11,7 @@ create_bd_port -dir I -from 1 -to 0 rx_data_n set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] -set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad6676_jesd] +set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd From 012b095006132d3bc1f64d2c542647e5ea5de73c Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 17 Mar 2016 11:44:27 +0200 Subject: [PATCH 24/44] daq3: Updated common design to 2015.4 --- projects/daq3/common/daq3_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index cfb78a5b8..2eb48bf37 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] -set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9152_jesd] +set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd @@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd From d355aa0ea6b051853d0b6d9cd69dcfc357174ef3 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 17 Mar 2016 11:46:48 +0200 Subject: [PATCH 25/44] daq3/zc706: Updated design to 2015.4 --- projects/daq3/zc706/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 8332b3431..655c77173 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -30,7 +30,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc From 28990e362a0d5bb041ccc0514e56425d91e407d8 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 13:31:06 +0200 Subject: [PATCH 26/44] axi_spdif_tx: Fixed the clock association --- library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index 8b27f16fd..fdc4c38c3 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -46,7 +46,7 @@ adi_set_ports_dependency "DMA_REQ_ACLK" \ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] - ipx::save_core [ipx::current_core] From 6d277733d5056175710a5a5d8ce9732539ef8a64 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 13:58:13 +0200 Subject: [PATCH 27/44] axi_spdif_rx: Fixed the clock association --- library/axi_spdif_rx/axi_spdif_rx_ip.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl index b66848df5..9b22be7d6 100644 --- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl +++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -49,4 +49,5 @@ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" ipx::save_core [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] From 412013d939c82034a83fd5b7e30a9ef7e425ee4c Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 15:01:25 +0200 Subject: [PATCH 28/44] adv7511: Update common design to 2015.4 --- projects/adv7511/common/adv7511_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/adv7511/common/adv7511_bd.tcl b/projects/adv7511/common/adv7511_bd.tcl index 1d94c1e4f..51b9c2ab3 100755 --- a/projects/adv7511/common/adv7511_bd.tcl +++ b/projects/adv7511/common/adv7511_bd.tcl @@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen From b555be25d59c11d2624c6a6758f22d3dc8d1958d Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 15:22:42 +0200 Subject: [PATCH 29/44] kcu105: Update common design to 2015.4 --- projects/common/kcu105/kcu105_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 512058517..80fc8619d 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -66,7 +66,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm From 995debedce5e30337ba6c6ec0ebeba7bcacfa115 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 15:26:52 +0200 Subject: [PATCH 30/44] fmcomms2: Update common design to 2015.4 --- projects/fmcomms2/common/prcfg_bd.tcl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/projects/fmcomms2/common/prcfg_bd.tcl b/projects/fmcomms2/common/prcfg_bd.tcl index e75a63d93..d7313adcc 100644 --- a/projects/fmcomms2/common/prcfg_bd.tcl +++ b/projects/fmcomms2/common/prcfg_bd.tcl @@ -148,7 +148,7 @@ ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out # rx side monitoring -set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_0] +set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0 @@ -159,7 +159,7 @@ ad_connect sys_cpu_clk ila_rx_0/clk ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0 ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1 -set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_1] +set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1 @@ -205,7 +205,7 @@ ad_connect axi_ad9361/l_clk ila_tx_0/clk ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0 ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1 -set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_1] +set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1 @@ -216,7 +216,7 @@ ad_connect axi_ad9361/l_clk ila_tx_1/clk ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0 ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1 -set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_2] +set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2 @@ -227,7 +227,7 @@ ad_connect axi_ad9361/l_clk ila_tx_2/clk ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0 ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1 -set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_3] +set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3 From d567af54ef71c9e83c1a5306801d397d8e69ff3a Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 15:27:31 +0200 Subject: [PATCH 31/44] imageon: Update common design to 2015.4 --- projects/imageon/common/imageon_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl index ec5784c68..412705ab3 100644 --- a/projects/imageon/common/imageon_bd.tcl +++ b/projects/imageon/common/imageon_bd.tcl @@ -76,7 +76,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq # debug -set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_fifo_dma_rx] +set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_fifo_dma_rx] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx set_property -dict [list CONFIG.C_DATA_DEPTH {4096}] $ila_fifo_dma_rx From f8b155faab868807548027540841603582304b0c Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 15:28:56 +0200 Subject: [PATCH 32/44] pzsdr/ccfmc: Update common design to 2015.4 --- projects/pzsdr/common/ccfmc_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl index 76ca44c2d..b4da554ca 100644 --- a/projects/pzsdr/common/ccfmc_bd.tcl +++ b/projects/pzsdr/common/ccfmc_bd.tcl @@ -59,7 +59,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen From 24fdd2b9b76136176eb9a62ccc64dd182648b7b1 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 15:30:10 +0200 Subject: [PATCH 33/44] pzsdr/ccpci: Update common design to 2015.4 --- projects/pzsdr/common/ccpci_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/pzsdr/common/ccpci_bd.tcl b/projects/pzsdr/common/ccpci_bd.tcl index f2961a025..6662565ec 100644 --- a/projects/pzsdr/common/ccpci_bd.tcl +++ b/projects/pzsdr/common/ccpci_bd.tcl @@ -49,7 +49,7 @@ ad_connect pl_gpio1_t axi_gpio/gpio2_io_t # pci-express -set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.6 axi_pcie_x4] +set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 axi_pcie_x4] set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4 set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4 set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4 From 05f4f3ac09ad7ef2434c8aba09f5059aacf975a9 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 16:16:38 +0200 Subject: [PATCH 34/44] usb_fx3: Update common design to 2015.4 --- projects/usb_fx3/common/usb_fx3_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl index 31f75ad6b..8c1c8f0ad 100644 --- a/projects/usb_fx3/common/usb_fx3_bd.tcl +++ b/projects/usb_fx3/common/usb_fx3_bd.tcl @@ -60,7 +60,7 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM set vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc] #ad_connect vcc/dout axi_usb_fx3/m_axis_tready -set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila] +set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila set_property -dict [list CONFIG.C_PROBE2_WIDTH {15}] $ila From 714caa964c12e38fa9ac9613df86e3057b252cd2 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 18 Mar 2016 16:29:43 +0200 Subject: [PATCH 35/44] usdrx1: Update common design to 2015.4 --- projects/usdrx1/common/usdrx1_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index d71659a1a..4b9f89177 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -58,7 +58,7 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671: set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3 set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3 -set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd] +set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd @@ -300,7 +300,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq # ila -set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_ad9671] +set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671 set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671 From 769fecbe006ff2ffd766e03693c4dcd746ea0919 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 21 Mar 2016 20:18:45 +0200 Subject: [PATCH 36/44] axi_i2s_adi: Fixed clock association --- library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index 0cd080c5e..d30ec0834 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -97,7 +97,8 @@ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] - +ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] ipx::save_core [ipx::current_core] From b31cdac6bd7909b137a54952029e572aedc112b7 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 23 Mar 2016 10:14:18 +0200 Subject: [PATCH 37/44] util_gmii_to_rgmii: Updated to 2015.4 The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1 --- library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl index 48710bf7c..be06aa5d8 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -15,9 +15,8 @@ adi_ip_constraints util_gmii_to_rgmii [list \ "util_gmii_to_rgmii_constr.xdc" ] ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] -set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]] +set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]] ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] -set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces reset -of_objects [ipx::current_core]]] set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] From 7c2f34549b2c6f3ad68cd19eb5ba05cf92ab58a2 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 23 Mar 2016 10:27:07 +0200 Subject: [PATCH 38/44] motcon2_fmc: Update common design to 2015.4 --- projects/motcon2_fmc/common/motcon2_fmc_bd.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 795f26750..1cdf24f90 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -12,6 +12,7 @@ # current monitor interface # clock create_bd_port -dir O adc_clk_o + # data motor 1 create_bd_port -dir I adc_m1_ia_dat_i create_bd_port -dir I adc_m1_ib_dat_i @@ -159,7 +160,7 @@ set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] # xadc - set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.1 xadc_core ] + set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_core ] set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core From 657144d9a79030dc44c7fb544580d690b596736f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 28 Mar 2016 13:21:36 +0300 Subject: [PATCH 39/44] a10gx: Updated base design and DAQ2 to the new revision of the a10gx board - tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock - CMU PLL works correctly as temporary solution --- projects/common/a10gx/a10gx_system_assign.tcl | 2 +- projects/common/a10gx/a10gx_system_bd.qsys | 12 +- projects/daq2/a10gx/system_bd.qsys | 6 +- projects/daq2/common/daq2_bd.qsys | 107 +++++++++--------- 4 files changed, 64 insertions(+), 63 deletions(-) diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl index 106b99b48..6b65ea2a6 100755 --- a/projects/common/a10gx/a10gx_system_assign.tcl +++ b/projects/common/a10gx/a10gx_system_assign.tcl @@ -2,7 +2,7 @@ # device settings set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name DEVICE 10AX115S3F45I2SGE2 +set_global_assignment -name DEVICE 10AX115S2F45I2SG # clocks and resets diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys index c49ad0640..663ecda37 100644 --- a/projects/common/a10gx/a10gx_system_bd.qsys +++ b/projects/common/a10gx/a10gx_system_bd.qsys @@ -601,7 +601,7 @@ } ]]> - + @@ -733,7 +733,7 @@ - + @@ -1862,14 +1862,14 @@ - + $${FILENAME}_sys_ddr3_cntrl - + @@ -1922,7 +1922,7 @@ - + @@ -1968,7 +1968,7 @@ - + ]]> diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys index 9f991b1ec..404b3413b 100755 --- a/projects/daq2/a10gx/system_bd.qsys +++ b/projects/daq2/a10gx/system_bd.qsys @@ -313,7 +313,7 @@ } ]]> - + @@ -418,7 +418,7 @@ type="reset" dir="end" /> - + @@ -445,7 +445,7 @@ - + diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys index 0f76e66a9..fcabfb523 100755 --- a/projects/daq2/common/daq2_bd.qsys +++ b/projects/daq2/common/daq2_bd.qsys @@ -413,6 +413,11 @@ value = "2"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element mem_rst { @@ -421,6 +426,11 @@ value = "3"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sys_clk { @@ -429,6 +439,11 @@ value = "0"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element sys_rst { @@ -437,6 +452,11 @@ value = "1"; type = "int"; } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } } element system_bd { @@ -709,11 +729,16 @@ value = "4"; type = "int"; } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } } } ]]> - + @@ -909,7 +934,7 @@ - + @@ -957,8 +982,8 @@ - - + + @@ -985,12 +1010,12 @@ - + - - - - + + + + @@ -1275,7 +1300,7 @@ - + @@ -1291,42 +1316,29 @@ - - - + + + + + + + - - + - - - - - - - - - - - - - - - - + + - - GX clock output buffer - + - altera_xcvr_atx_pll_a10 + altera_xcvr_cdr_pll_a10 @@ -1340,25 +1352,14 @@ + + - - + - - - - - - - - - - - - @@ -1638,7 +1639,7 @@ - + @@ -2006,8 +2007,8 @@ + start="xcvr_tx_lane_pll.pll_cal_busy" + end="xcvr_rst_cntrl.pll_cal_busy"> From 21208ca2082fd4630206d571e272dbe04ffa4f58 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 31 Mar 2016 12:37:47 +0300 Subject: [PATCH 40/44] Makefiles: Update Makefiles --- projects/ad6676evb/vc707/Makefile | 2 ++ projects/ad6676evb/zc706/Makefile | 2 ++ projects/ad9265_fmc/zc706/Makefile | 2 ++ projects/ad9434_fmc/zc706/Makefile | 2 ++ projects/ad9467_fmc/kc705/Makefile | 2 ++ projects/ad9467_fmc/zed/Makefile | 2 ++ projects/ad9739a_fmc/zc706/Makefile | 2 ++ projects/adv7511/ac701/Makefile | 2 ++ projects/adv7511/kc705/Makefile | 2 ++ projects/adv7511/kcu105/Makefile | 2 ++ projects/adv7511/mitx045/Makefile | 2 ++ projects/adv7511/vc707/Makefile | 2 ++ projects/adv7511/zc702/Makefile | 2 ++ projects/adv7511/zc706/Makefile | 2 ++ projects/adv7511/zed/Makefile | 2 ++ projects/cftl_cip/zed/Makefile | 2 ++ projects/cftl_std/zed/Makefile | 2 ++ projects/cn0363/zed/Makefile | 2 ++ projects/daq1/zc706/Makefile | 2 ++ projects/daq2/kc705/Makefile | 2 ++ projects/daq2/kcu105/Makefile | 2 ++ projects/daq2/vc707/Makefile | 2 ++ projects/daq2/zc706/Makefile | 2 ++ projects/daq3/zc706/Makefile | 2 ++ projects/fmcadc2/vc707/Makefile | 2 ++ projects/fmcadc2/zc706/Makefile | 2 ++ projects/fmcadc4/zc706/Makefile | 2 ++ projects/fmcadc5/vc707/Makefile | 2 ++ projects/fmcjesdadc1/kc705/Makefile | 2 ++ projects/fmcjesdadc1/vc707/Makefile | 2 ++ projects/fmcjesdadc1/zc706/Makefile | 2 ++ projects/fmcomms1/ac701/Makefile | 2 ++ projects/fmcomms1/kc705/Makefile | 2 ++ projects/fmcomms1/vc707/Makefile | 2 ++ projects/fmcomms1/zc702/Makefile | 2 ++ projects/fmcomms1/zc706/Makefile | 2 ++ projects/fmcomms1/zed/Makefile | 2 ++ projects/fmcomms2/ac701/Makefile | 2 ++ projects/fmcomms2/kc705/Makefile | 2 ++ projects/fmcomms2/mitx045/Makefile | 2 ++ projects/fmcomms2/vc707/Makefile | 2 ++ projects/fmcomms2/zc702/Makefile | 2 ++ projects/fmcomms2/zc706/Makefile | 2 ++ projects/fmcomms2/zed/Makefile | 2 ++ projects/fmcomms5/zc702/Makefile | 2 ++ projects/fmcomms5/zc706/Makefile | 2 ++ projects/fmcomms6/zc706/Makefile | 2 ++ projects/fmcomms7/zc706/Makefile | 2 ++ projects/imageon/zc706/Makefile | 2 ++ projects/imageon/zed/Makefile | 2 ++ projects/motcon2_fmc/zed/Makefile | 2 ++ projects/pzsdr/ccbrk/Makefile | 2 ++ projects/pzsdr/ccfmc/Makefile | 2 ++ projects/pzsdr/ccpci/Makefile | 2 ++ projects/usb_fx3/zc706/Makefile | 2 ++ projects/usdrx1/a5gt/Makefile | 1 + projects/usdrx1/zc706/Makefile | 2 ++ 57 files changed, 113 insertions(+) diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile index 789699d30..5e0c9487c 100644 --- a/projects/ad6676evb/vc707/Makefile +++ b/projects/ad6676evb/vc707/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile index a6cbba810..b11811429 100644 --- a/projects/ad6676evb/zc706/Makefile +++ b/projects/ad6676evb/zc706/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile index d1dc365b9..9ad95e317 100644 --- a/projects/ad9265_fmc/zc706/Makefile +++ b/projects/ad9265_fmc/zc706/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile index 3f18dcb7a..70d247f5c 100644 --- a/projects/ad9434_fmc/zc706/Makefile +++ b/projects/ad9434_fmc/zc706/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile index b9b6a3516..887838189 100644 --- a/projects/ad9467_fmc/kc705/Makefile +++ b/projects/ad9467_fmc/kc705/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile index a08832b57..0eee2b11c 100644 --- a/projects/ad9467_fmc/zed/Makefile +++ b/projects/ad9467_fmc/zed/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile index f9e98a2b3..481327975 100644 --- a/projects/ad9739a_fmc/zc706/Makefile +++ b/projects/ad9739a_fmc/zc706/Makefile @@ -33,6 +33,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile index 16e4a1588..0dfca3289 100644 --- a/projects/adv7511/ac701/Makefile +++ b/projects/adv7511/ac701/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile index 970c44988..69dea3d47 100644 --- a/projects/adv7511/kc705/Makefile +++ b/projects/adv7511/kc705/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile index 7793cadb1..9a09b9f4f 100644 --- a/projects/adv7511/kcu105/Makefile +++ b/projects/adv7511/kcu105/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile index 3c03e7595..80c65e379 100644 --- a/projects/adv7511/mitx045/Makefile +++ b/projects/adv7511/mitx045/Makefile @@ -31,6 +31,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile index 9fd0f4623..b347dcd33 100644 --- a/projects/adv7511/vc707/Makefile +++ b/projects/adv7511/vc707/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile index 6c520c266..876158ecd 100644 --- a/projects/adv7511/zc702/Makefile +++ b/projects/adv7511/zc702/Makefile @@ -29,6 +29,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile index 3c4655c04..d00baa5e9 100644 --- a/projects/adv7511/zc706/Makefile +++ b/projects/adv7511/zc706/Makefile @@ -29,6 +29,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile index d0360c3ce..26d233c0b 100644 --- a/projects/adv7511/zed/Makefile +++ b/projects/adv7511/zed/Makefile @@ -31,6 +31,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile index 33231bac1..687b6a0e0 100644 --- a/projects/cftl_cip/zed/Makefile +++ b/projects/cftl_cip/zed/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile index ad3de3c44..55923a3eb 100644 --- a/projects/cftl_std/zed/Makefile +++ b/projects/cftl_std/zed/Makefile @@ -33,6 +33,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile index 7d982d5dd..c9f80d8c5 100644 --- a/projects/cn0363/zed/Makefile +++ b/projects/cn0363/zed/Makefile @@ -43,6 +43,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile index bcb19e751..8df754906 100644 --- a/projects/daq1/zc706/Makefile +++ b/projects/daq1/zc706/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile index 62d217be4..f5349f760 100644 --- a/projects/daq2/kc705/Makefile +++ b/projects/daq2/kc705/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile index 6c51e2d2d..82e1efb04 100644 --- a/projects/daq2/kcu105/Makefile +++ b/projects/daq2/kcu105/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile index 5ea067321..879592ecc 100644 --- a/projects/daq2/vc707/Makefile +++ b/projects/daq2/vc707/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile index 710142553..14e469a0c 100644 --- a/projects/daq2/zc706/Makefile +++ b/projects/daq2/zc706/Makefile @@ -46,6 +46,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile index 260244908..2e77582c0 100644 --- a/projects/daq3/zc706/Makefile +++ b/projects/daq3/zc706/Makefile @@ -47,6 +47,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile index 261bcba5c..3ae995270 100644 --- a/projects/fmcadc2/vc707/Makefile +++ b/projects/fmcadc2/vc707/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile index 034ea3b33..352efb7bc 100644 --- a/projects/fmcadc2/zc706/Makefile +++ b/projects/fmcadc2/zc706/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile index eddeba7f9..e3d0a21a2 100644 --- a/projects/fmcadc4/zc706/Makefile +++ b/projects/fmcadc4/zc706/Makefile @@ -43,6 +43,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile index 0b5ddbfe3..38905f714 100644 --- a/projects/fmcadc5/vc707/Makefile +++ b/projects/fmcadc5/vc707/Makefile @@ -41,6 +41,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile index 71ce938e1..7050c879e 100644 --- a/projects/fmcjesdadc1/kc705/Makefile +++ b/projects/fmcjesdadc1/kc705/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile index dcfd2dbef..379caa28b 100644 --- a/projects/fmcjesdadc1/vc707/Makefile +++ b/projects/fmcjesdadc1/vc707/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile index 72db888ec..e3c623304 100644 --- a/projects/fmcjesdadc1/zc706/Makefile +++ b/projects/fmcjesdadc1/zc706/Makefile @@ -38,6 +38,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile index 238362c27..9c8a6771c 100644 --- a/projects/fmcomms1/ac701/Makefile +++ b/projects/fmcomms1/ac701/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile index 8a42ea764..5d00e2573 100644 --- a/projects/fmcomms1/kc705/Makefile +++ b/projects/fmcomms1/kc705/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile index fcb4df7c3..8b7b14948 100644 --- a/projects/fmcomms1/vc707/Makefile +++ b/projects/fmcomms1/vc707/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile index 50e606602..c5faab08a 100644 --- a/projects/fmcomms1/zc702/Makefile +++ b/projects/fmcomms1/zc702/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile index db02e1958..5170046cd 100644 --- a/projects/fmcomms1/zc706/Makefile +++ b/projects/fmcomms1/zc706/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile index 133c9cef9..79e54721f 100644 --- a/projects/fmcomms1/zed/Makefile +++ b/projects/fmcomms1/zed/Makefile @@ -39,6 +39,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile index 5824fd77f..03282725e 100644 --- a/projects/fmcomms2/ac701/Makefile +++ b/projects/fmcomms2/ac701/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile index 8a038d42e..ab24ca35e 100644 --- a/projects/fmcomms2/kc705/Makefile +++ b/projects/fmcomms2/kc705/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile index 6a2874776..ca53855ce 100644 --- a/projects/fmcomms2/mitx045/Makefile +++ b/projects/fmcomms2/mitx045/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile index a6db3e1a1..46327e71d 100644 --- a/projects/fmcomms2/vc707/Makefile +++ b/projects/fmcomms2/vc707/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile index 5fb3b22c3..439cfe22c 100644 --- a/projects/fmcomms2/zc702/Makefile +++ b/projects/fmcomms2/zc702/Makefile @@ -38,6 +38,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile index cdc3bd188..d3c52de44 100644 --- a/projects/fmcomms2/zc706/Makefile +++ b/projects/fmcomms2/zc706/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile index 03edb148a..9fd8dcfc5 100644 --- a/projects/fmcomms2/zed/Makefile +++ b/projects/fmcomms2/zed/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile index 8bfcc6aeb..bba74f74a 100644 --- a/projects/fmcomms5/zc702/Makefile +++ b/projects/fmcomms5/zc702/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile index bac1ce596..5aee574f5 100644 --- a/projects/fmcomms5/zc706/Makefile +++ b/projects/fmcomms5/zc706/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile index 15699ccfb..3846e87f0 100644 --- a/projects/fmcomms6/zc706/Makefile +++ b/projects/fmcomms6/zc706/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile index 95fc249f4..2caa37ee7 100644 --- a/projects/fmcomms7/zc706/Makefile +++ b/projects/fmcomms7/zc706/Makefile @@ -46,6 +46,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile index 7e0d311db..c4981bb84 100644 --- a/projects/imageon/zc706/Makefile +++ b/projects/imageon/zc706/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile index dc58dca51..1148228ee 100644 --- a/projects/imageon/zed/Makefile +++ b/projects/imageon/zed/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile index e891adcde..e214e56d0 100644 --- a/projects/motcon2_fmc/zed/Makefile +++ b/projects/motcon2_fmc/zed/Makefile @@ -39,6 +39,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile index 49d742665..001dbd654 100644 --- a/projects/pzsdr/ccbrk/Makefile +++ b/projects/pzsdr/ccbrk/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile index a29f3d69a..aa9dfe4fb 100644 --- a/projects/pzsdr/ccfmc/Makefile +++ b/projects/pzsdr/ccfmc/Makefile @@ -44,6 +44,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile index 5668a66a3..fafebeaaa 100644 --- a/projects/pzsdr/ccpci/Makefile +++ b/projects/pzsdr/ccpci/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile index f16d3c455..eb786cf55 100644 --- a/projects/usb_fx3/zc706/Makefile +++ b/projects/usb_fx3/zc706/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile index 9be0289b1..d461204bb 100644 --- a/projects/usdrx1/a5gt/Makefile +++ b/projects/usdrx1/a5gt/Makefile @@ -8,6 +8,7 @@ M_DEPS += system_project.tcl M_DEPS += ../common/usdrx1_spi.v M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v M_DEPS += ../../../library/common/altera/ad_jesd_align.v diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile index 4a0ec0f19..936fbbcfe 100644 --- a/projects/usdrx1/zc706/Makefile +++ b/projects/usdrx1/zc706/Makefile @@ -39,6 +39,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil From 6fe41ebb08b21a684eb92fd83ae1d0945d83c486 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 12 Apr 2016 22:01:07 +0300 Subject: [PATCH 41/44] axi_hdmi_tx: Upgrade hdmi clipping process -added two registers that control the clipping ranges (0x01a and 0x01b) -extend clipping process for all output data formats --- library/axi_hdmi_tx/axi_hdmi_tx.v | 8 +- library/axi_hdmi_tx/axi_hdmi_tx_core.v | 149 +++++++++++++++++-------- library/common/up_hdmi_tx.v | 36 +++++- 3 files changed, 145 insertions(+), 48 deletions(-) diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 1413a39b3..056eb2fb3 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -202,6 +202,8 @@ module axi_hdmi_tx ( wire [15:0] hdmi_vs_width_s; wire [15:0] hdmi_ve_max_s; wire [15:0] hdmi_ve_min_s; + wire [31:0] hdmi_clip_max_s; + wire [31:0] hdmi_clip_min_s; wire hdmi_fs_toggle_s; wire [ 8:0] hdmi_raddr_g_s; wire hdmi_tpm_oos_s; @@ -271,6 +273,8 @@ module axi_hdmi_tx ( .hdmi_vs_width (hdmi_vs_width_s), .hdmi_ve_max (hdmi_ve_max_s), .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s), .hdmi_status (hdmi_status_s), .hdmi_tpm_oos (hdmi_tpm_oos_s), .hdmi_clk_ratio (32'd1), @@ -356,7 +360,9 @@ module axi_hdmi_tx ( .hdmi_vf_width (hdmi_vf_width_s), .hdmi_vs_width (hdmi_vs_width_s), .hdmi_ve_max (hdmi_ve_max_s), - .hdmi_ve_min (hdmi_ve_min_s)); + .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s)); // hdmi output clock diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index 3831a821e..fd1ccf12c 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -97,7 +97,9 @@ module axi_hdmi_tx_core ( hdmi_vf_width, hdmi_vs_width, hdmi_ve_max, - hdmi_ve_min); + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min); // parameters @@ -164,6 +166,8 @@ module axi_hdmi_tx_core ( input [15:0] hdmi_vs_width; input [15:0] hdmi_ve_max; input [15:0] hdmi_ve_min; + input [23:0] hdmi_clip_max; + input [23:0] hdmi_clip_min; // internal registers @@ -205,12 +209,24 @@ module axi_hdmi_tx_core ( reg hdmi_vsync_data_e = 'd0; reg hdmi_data_e = 'd0; reg [23:0] hdmi_data = 'd0; + reg hdmi_24_csc_hsync = 'd0; + reg hdmi_24_csc_vsync = 'd0; + reg hdmi_24_csc_hsync_data_e = 'd0; + reg hdmi_24_csc_vsync_data_e = 'd0; + reg hdmi_24_csc_data_e = 'd0; + reg [23:0] hdmi_24_csc_data = 'd0; reg hdmi_24_hsync = 'd0; reg hdmi_24_vsync = 'd0; reg hdmi_24_hsync_data_e = 'd0; reg hdmi_24_vsync_data_e = 'd0; reg hdmi_24_data_e = 'd0; reg [23:0] hdmi_24_data = 'd0; + reg hdmi_24_hsync_ss = 'd0; + reg hdmi_24_vsync_ss = 'd0; + reg hdmi_24_hsync_data_e_ss = 'd0; + reg hdmi_24_vsync_data_e_ss = 'd0; + reg hdmi_24_data_e_ss = 'd0; + reg [23:0] hdmi_24_data_ss = 'd0; reg hdmi_16_hsync = 'd0; reg hdmi_16_vsync = 'd0; reg hdmi_16_hsync_data_e = 'd0; @@ -220,6 +236,12 @@ module axi_hdmi_tx_core ( reg hdmi_es_hs_de = 'd0; reg hdmi_es_vs_de = 'd0; reg [15:0] hdmi_es_data = 'd0; + reg [23:0] hdmi_clip_data = 'd0; + reg hdmi_clip_hs_de_d = 'd0; + reg hdmi_clip_vs_de_d = 'd0; + reg hdmi_clip_hs_d = 'd0; + reg hdmi_clip_vs_d = 'd0; + reg hdmi_clip_de_d = 'd0; // internal wires @@ -245,6 +267,10 @@ module axi_hdmi_tx_core ( wire hdmi_ss_vsync_data_e_s; wire hdmi_ss_data_e_s; wire [15:0] hdmi_ss_data_s; + wire hdmi_clip_hs_de_s; + wire hdmi_clip_vs_de_s; + wire hdmi_clip_de_s; + wire [23:0] hdmi_clip_data_s; wire hdmi_es_hs_de_s; wire hdmi_es_vs_de_s; wire hdmi_es_de_s; @@ -453,6 +479,68 @@ module axi_hdmi_tx_core ( endcase end + // Color space conversion bypass (RGB/YCbCr) + + always @(posedge hdmi_clk) begin + if (hdmi_csc_bypass == 1'b1) begin + hdmi_24_csc_hsync <= hdmi_hsync; + hdmi_24_csc_vsync <= hdmi_vsync; + hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e; + hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e; + hdmi_24_csc_data_e <= hdmi_data_e; + hdmi_24_csc_data <= hdmi_data; + end else begin + hdmi_24_csc_hsync <= hdmi_csc_hsync_s; + hdmi_24_csc_vsync <= hdmi_csc_vsync_s; + hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s; + hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s; + hdmi_24_csc_data_e <= hdmi_csc_data_e_s; + hdmi_24_csc_data <= hdmi_csc_data_s; + end + end + + // hdmi clipping + + assign hdmi_clip_data_s = hdmi_24_csc_data; + + always @(posedge hdmi_clk) begin + hdmi_clip_hs_d <= hdmi_24_csc_hsync; + hdmi_clip_vs_d <= hdmi_24_csc_vsync; + hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e; + hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e; + hdmi_clip_de_d <= hdmi_24_csc_data_e; + + // Cr (red-diff) / red + + if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_max[23:16]; + end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_min[23:16]; + end else begin + hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16]; + end + + // Y (luma) / green + + if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_max[15:8]; + end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_min[15:8]; + end else begin + hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8]; + end + + // Cb (blue-diff) / blue + + if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_max[7:0]; + end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_min[7:0]; + end else begin + hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0]; + end + end + // hdmi csc 16, 24 and 36 outputs assign hdmi_36_hsync = hdmi_24_hsync; @@ -463,21 +551,14 @@ module axi_hdmi_tx_core ( assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]}; always @(posedge hdmi_clk) begin - if (hdmi_csc_bypass == 1'b1) begin - hdmi_24_hsync <= hdmi_hsync; - hdmi_24_vsync <= hdmi_vsync; - hdmi_24_hsync_data_e <= hdmi_hsync_data_e; - hdmi_24_vsync_data_e <= hdmi_vsync_data_e; - hdmi_24_data_e <= hdmi_data_e; - hdmi_24_data <= hdmi_data; - end else begin - hdmi_24_hsync <= hdmi_csc_hsync_s; - hdmi_24_vsync <= hdmi_csc_vsync_s; - hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s; - hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s; - hdmi_24_data_e <= hdmi_csc_data_e_s; - hdmi_24_data <= hdmi_csc_data_s; - end + + hdmi_24_hsync <= hdmi_clip_hs_d; + hdmi_24_vsync <= hdmi_clip_vs_d; + hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d; + hdmi_24_vsync_data_e <= hdmi_clip_vs_de_d; + hdmi_24_data_e <= hdmi_clip_de_d; + hdmi_24_data <= hdmi_clip_data; + if (hdmi_ss_bypass == 1'b1) begin hdmi_16_hsync <= hdmi_24_hsync; hdmi_16_vsync <= hdmi_24_vsync; @@ -495,7 +576,7 @@ module axi_hdmi_tx_core ( end end - // hdmi embedded sync clipping + // hdmi embedded sync assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e; assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e; @@ -507,31 +588,11 @@ module axi_hdmi_tx_core ( hdmi_es_vs_de <= hdmi_es_vs_de_s; if (hdmi_es_de_s == 1'b0) begin hdmi_es_data[15:8] <= 8'h80; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[15:8] > 8'heb)) begin - hdmi_es_data[15:8] <= 8'heb; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[15:8] < 8'h10)) begin - hdmi_es_data[15:8] <= 8'h10; - end else if (hdmi_es_data_s[15:8] > 8'hfe) begin - hdmi_es_data[15:8] <= 8'hfe; - end else if (hdmi_es_data_s[15:8] < 8'h01) begin - hdmi_es_data[15:8] <= 8'h01; end else begin hdmi_es_data[15:8] <= hdmi_es_data_s[15:8]; end if (hdmi_es_de_s == 1'b0) begin hdmi_es_data[7:0] <= 8'h80; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[7:0] > 8'heb)) begin - hdmi_es_data[7:0] <= 8'heb; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[7:0] < 8'h10)) begin - hdmi_es_data[7:0] <= 8'h10; - end else if (hdmi_es_data_s[7:0] > 8'hfe) begin - hdmi_es_data[7:0] <= 8'hfe; - end else if (hdmi_es_data_s[7:0] < 8'h01) begin - hdmi_es_data[7:0] <= 8'h01; end else begin hdmi_es_data[7:0] <= hdmi_es_data_s[7:0]; end @@ -569,13 +630,13 @@ module axi_hdmi_tx_core ( ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 ( .clk (hdmi_clk), - .s444_de (hdmi_24_data_e), - .s444_sync ({hdmi_24_hsync, - hdmi_24_vsync, - hdmi_24_hsync_data_e, - hdmi_24_vsync_data_e, - hdmi_24_data_e}), - .s444_data (hdmi_24_data), + .s444_de (hdmi_clip_de_d), + .s444_sync ({hdmi_clip_hs_d, + hdmi_clip_vs_d, + hdmi_clip_hs_de_d, + hdmi_clip_vs_de_d, + hdmi_clip_de_d}), + .s444_data (hdmi_clip_data), .s422_sync ({hdmi_ss_hsync_s, hdmi_ss_vsync_s, hdmi_ss_hsync_data_e_s, diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index f63f93d60..e1750e76b 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -58,6 +58,8 @@ module up_hdmi_tx ( hdmi_vs_width, hdmi_ve_max, hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min, hdmi_status, hdmi_tpm_oos, hdmi_clk_ratio, @@ -107,6 +109,8 @@ module up_hdmi_tx ( output [15:0] hdmi_vs_width; output [15:0] hdmi_ve_max; output [15:0] hdmi_ve_min; + output [23:0] hdmi_clip_max; + output [23:0] hdmi_clip_min; input hdmi_status; input hdmi_tpm_oos; input [31:0] hdmi_clk_ratio; @@ -157,6 +161,8 @@ module up_hdmi_tx ( reg [15:0] up_vs_width = 'd0; reg [15:0] up_ve_max = 'd0; reg [15:0] up_ve_min = 'd0; + reg [23:0] up_clip_max = 'd0; + reg [23:0] up_clip_min = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; @@ -203,6 +209,8 @@ module up_hdmi_tx ( up_vs_width <= 'd0; up_ve_max <= 'd0; up_ve_min <= 'd0; + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; end else begin up_core_preset <= ~up_resetn; up_wack <= up_wreq_s; @@ -243,6 +251,21 @@ module up_hdmi_tx ( end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin + if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin + up_clip_max <= 24'hfefefe; + up_clip_min <= 24'h010101; + end else begin + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; + end + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin + up_clip_max <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin + up_clip_min <= up_wdata[23:0]; + end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin up_hl_active <= up_wdata[31:16]; up_hl_width <= up_wdata[15:0]; @@ -290,6 +313,9 @@ module up_hdmi_tx ( 12'h017: up_rdata <= {31'd0, up_hdmi_status_s}; 12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf}; 12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos}; + 12'h01a: up_rdata <= {8'd0, up_clip_max}; + 12'h01b: up_rdata <= {8'd0, up_clip_min}; + 12'h100: up_rdata <= {up_hl_active, up_hl_width}; 12'h101: up_rdata <= {16'd0, up_hs_width}; 12'h102: up_rdata <= {up_he_max, up_he_min}; @@ -311,7 +337,7 @@ module up_hdmi_tx ( // hdmi control & status - up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_ss_bypass, @@ -328,7 +354,9 @@ module up_hdmi_tx ( up_vf_width, up_vs_width, up_ve_max, - up_ve_min}), + up_ve_min, + up_clip_max, + up_clip_min}), .up_xfer_done (), .d_rst (hdmi_rst), .d_clk (hdmi_clk), @@ -346,7 +374,9 @@ module up_hdmi_tx ( hdmi_vf_width, hdmi_vs_width, hdmi_ve_max, - hdmi_ve_min})); + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min})); up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status ( .up_rstn (up_rstn), From 62bd057106e3b2ee6732bfac3789b53c56ce0069 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 14 Apr 2016 23:01:38 +0300 Subject: [PATCH 42/44] fmcadc5/common: Update common design to 2015.4 --- projects/fmcadc5/common/fmcadc5_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index aaaaa83e7..4b3d0c793 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -19,10 +19,10 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core] set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core -set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_0_jesd] +set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd -set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_1_jesd] +set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd From 469b4ea5e83ab5efdb4fc8ab4ba74beffa1b6033 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 14 Apr 2016 23:18:23 +0300 Subject: [PATCH 43/44] fmcadc5: Updated design to 2015.4 --- projects/fmcadc5/vc707/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl index 40dab996c..6ca32626b 100644 --- a/projects/fmcadc5/vc707/system_bd.tcl +++ b/projects/fmcadc5/vc707/system_bd.tcl @@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc From c291f8f10732f6f9d45b586ad31371e69d887e4d Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 14 Apr 2016 23:36:47 +0300 Subject: [PATCH 44/44] daq1: Updated design to 2015.4 --- projects/daq1/common/daq1_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 1dd1448a8..4f2fe6dee 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -57,7 +57,7 @@ set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_a set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core] -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd] +set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd