From 67a5737fa17fe109e45da1b061d01f86fb2368a1 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 17 May 2022 10:56:01 +0300 Subject: [PATCH] ad9083_vna: Init commit Compatible with RevB --- projects/ad9083_vna/Makefile | 7 + projects/ad9083_vna/Readme.md | 15 + projects/ad9083_vna/common/ad9083_vna_bd.tcl | 92 ++++++ projects/ad9083_vna/zcu102/Makefile | 28 ++ projects/ad9083_vna/zcu102/system_bd.tcl | 12 + projects/ad9083_vna/zcu102/system_constr.xdc | 109 +++++++ projects/ad9083_vna/zcu102/system_project.tcl | 14 + projects/ad9083_vna/zcu102/system_top.v | 297 ++++++++++++++++++ 8 files changed, 574 insertions(+) create mode 100644 projects/ad9083_vna/Makefile create mode 100644 projects/ad9083_vna/Readme.md create mode 100644 projects/ad9083_vna/common/ad9083_vna_bd.tcl create mode 100644 projects/ad9083_vna/zcu102/Makefile create mode 100644 projects/ad9083_vna/zcu102/system_bd.tcl create mode 100644 projects/ad9083_vna/zcu102/system_constr.xdc create mode 100644 projects/ad9083_vna/zcu102/system_project.tcl create mode 100644 projects/ad9083_vna/zcu102/system_top.v diff --git a/projects/ad9083_vna/Makefile b/projects/ad9083_vna/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/ad9083_vna/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9083_vna/Readme.md b/projects/ad9083_vna/Readme.md new file mode 100644 index 000000000..a8e80affe --- /dev/null +++ b/projects/ad9083_vna/Readme.md @@ -0,0 +1,15 @@ +# AD9083-VNA HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/eval-ad9083-vna) + * Part : [AD9083 - 16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter](https://www.analog.com/ad9083) + * Part : [ADMV8818 - 2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter](https://www.analog.com/admv8818) + * Part : [ADRF5021 - 9 kHz to 30 GHz, Silicon SPDT Switch](https://www.analog.com/adrf5021) + * Part : [ADRF5045 - 9 kHz to 30 GHz, Silicon, SP4T Switch](https://www.analog.com/adrf5045) + * Part : [ADF4371S - Microwave Wideband Synthesizer with Integrated VCO](https://www.analog.com/adf4371) + * Part : [ADL5960 - 10 MHz to 20 GHz, Integrated Vector Network Analyzer Front-End](https://www.analog.com/adl5960) + * Part : [HMC8411 - Low Noise Amplifier, 0.01 GHz to 10 GHz](https://www.analog.com/hmc8411) + * Part : [HMC994 - 0.5 Watt Power Amplifier, DC - 30 GHz](https://www.analog.com/hmc994) + * Project Doc: https://wiki.analog.com/resources/eval/ad9083-vna + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad9083_vna/ad9083_vna_reference_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad9083 diff --git a/projects/ad9083_vna/common/ad9083_vna_bd.tcl b/projects/ad9083_vna/common/ad9083_vna_bd.tcl new file mode 100644 index 000000000..977550249 --- /dev/null +++ b/projects/ad9083_vna/common/ad9083_vna_bd.tcl @@ -0,0 +1,92 @@ + +# RX parameters +set RX_NUM_OF_LANES 1 ; # L +set RX_NUM_OF_CONVERTERS 32 ; # M +set RX_SAMPLES_PER_FRAME 1 ; # S +set RX_SAMPLE_WIDTH 16 ; # N/NP + +source ../../ad9083_evb/common/ad9083_evb_bd.tcl + +# add spi interfaces + +create_bd_port -dir O -from 1 -to 0 spi_bus1_csn_o +create_bd_port -dir I -from 1 -to 0 spi_bus1_csn_i +create_bd_port -dir I spi_bus1_clk_i +create_bd_port -dir O spi_bus1_clk_o +create_bd_port -dir I spi_bus1_sdo_i +create_bd_port -dir O spi_bus1_sdo_o +create_bd_port -dir I spi_bus1_sdi_i + +create_bd_port -dir O -from 3 -to 0 spi_adl5960_1_csn_o +create_bd_port -dir I -from 3 -to 0 spi_adl5960_1_csn_i +create_bd_port -dir I spi_adl5960_1_clk_i +create_bd_port -dir O spi_adl5960_1_clk_o +create_bd_port -dir I spi_adl5960_1_sdo_i +create_bd_port -dir O spi_adl5960_1_sdo_o +create_bd_port -dir I spi_adl5960_1_sdi_i + +create_bd_port -dir O -from 3 -to 0 spi_adl5960_2_csn_o +create_bd_port -dir I -from 3 -to 0 spi_adl5960_2_csn_i +create_bd_port -dir I spi_adl5960_2_clk_i +create_bd_port -dir O spi_adl5960_2_clk_o +create_bd_port -dir I spi_adl5960_2_sdo_i +create_bd_port -dir O spi_adl5960_2_sdo_o +create_bd_port -dir I spi_adl5960_2_sdi_i + +# spi instances + +ad_ip_instance axi_quad_spi axi_spi_bus1 +ad_ip_parameter axi_spi_bus1 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_bus1 CONFIG.C_NUM_SS_BITS 2 +ad_ip_parameter axi_spi_bus1 CONFIG.C_SCK_RATIO 8 + +ad_ip_instance axi_quad_spi axi_spi_adl5960_1 +ad_ip_parameter axi_spi_adl5960_1 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_adl5960_1 CONFIG.C_NUM_SS_BITS 4 +ad_ip_parameter axi_spi_adl5960_1 CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi_adl5960_1 CONFIG.Multiples16 8 + +ad_ip_instance axi_quad_spi axi_spi_adl5960_2 +ad_ip_parameter axi_spi_adl5960_2 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_adl5960_2 CONFIG.C_NUM_SS_BITS 4 +ad_ip_parameter axi_spi_adl5960_2 CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi_adl5960_2 CONFIG.Multiples16 8 + +# spi connections + +ad_connect sys_cpu_clk axi_spi_bus1/ext_spi_clk +ad_connect spi_bus1_csn_i axi_spi_bus1/ss_i +ad_connect spi_bus1_csn_o axi_spi_bus1/ss_o +ad_connect spi_bus1_clk_i axi_spi_bus1/sck_i +ad_connect spi_bus1_clk_o axi_spi_bus1/sck_o +ad_connect spi_bus1_sdo_i axi_spi_bus1/io0_i +ad_connect spi_bus1_sdo_o axi_spi_bus1/io0_o +ad_connect spi_bus1_sdi_i axi_spi_bus1/io1_i + +ad_connect sys_cpu_clk axi_spi_adl5960_1/ext_spi_clk +ad_connect spi_adl5960_1_csn_i axi_spi_adl5960_1/ss_i +ad_connect spi_adl5960_1_csn_o axi_spi_adl5960_1/ss_o +ad_connect spi_adl5960_1_clk_i axi_spi_adl5960_1/sck_i +ad_connect spi_adl5960_1_clk_o axi_spi_adl5960_1/sck_o +ad_connect spi_adl5960_1_sdo_i axi_spi_adl5960_1/io0_i +ad_connect spi_adl5960_1_sdo_o axi_spi_adl5960_1/io0_o +ad_connect spi_adl5960_1_sdi_i axi_spi_adl5960_1/io1_i + +ad_connect sys_cpu_clk axi_spi_adl5960_2/ext_spi_clk +ad_connect spi_adl5960_2_csn_i axi_spi_adl5960_2/ss_i +ad_connect spi_adl5960_2_csn_o axi_spi_adl5960_2/ss_o +ad_connect spi_adl5960_2_clk_i axi_spi_adl5960_2/sck_i +ad_connect spi_adl5960_2_clk_o axi_spi_adl5960_2/sck_o +ad_connect spi_adl5960_2_sdo_i axi_spi_adl5960_2/io0_i +ad_connect spi_adl5960_2_sdo_o axi_spi_adl5960_2/io0_o +ad_connect spi_adl5960_2_sdi_i axi_spi_adl5960_2/io1_i + +ad_cpu_interconnect 0x48000000 axi_spi_bus1 +ad_cpu_interconnect 0x48100000 axi_spi_adl5960_1 +ad_cpu_interconnect 0x48200000 axi_spi_adl5960_2 + +# interrupts + +ad_cpu_interrupt ps-9 mb-8 axi_spi_bus1/ip2intc_irpt +ad_cpu_interrupt ps-10 mb-15 axi_spi_adl5960_1/ip2intc_irpt +ad_cpu_interrupt ps-11 mb-14 axi_spi_adl5960_2/ip2intc_irpt diff --git a/projects/ad9083_vna/zcu102/Makefile b/projects/ad9083_vna/zcu102/Makefile new file mode 100644 index 000000000..e8ed2d726 --- /dev/null +++ b/projects/ad9083_vna/zcu102/Makefile @@ -0,0 +1,28 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9083_vna_zcu102 + +M_DEPS += ../common/ad9083_vna_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../ad9083_evb/common/ad9083_evb_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9083_vna/zcu102/system_bd.tcl b/projects/ad9083_vna/zcu102/system_bd.tcl new file mode 100644 index 000000000..64d10c41d --- /dev/null +++ b/projects/ad9083_vna/zcu102/system_bd.tcl @@ -0,0 +1,12 @@ + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +source ../common/ad9083_vna_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +sysid_gen_sys_init_file + diff --git a/projects/ad9083_vna/zcu102/system_constr.xdc b/projects/ad9083_vna/zcu102/system_constr.xdc new file mode 100644 index 000000000..1645c2113 --- /dev/null +++ b/projects/ad9083_vna/zcu102/system_constr.xdc @@ -0,0 +1,109 @@ + +# ad9083 + +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports glblclk_p] ; ## G6 FMC_HPC0_LA00_CC_P +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports glblclk_n] ; ## G7 FMC_HPC0_LA00_CC_N + +set_property -dict {PACKAGE_PIN G8} [get_ports ref_clk0_p] ; ## D4 FMC_HPC0 GBTCLK0 M2C_C_P +set_property -dict {PACKAGE_PIN G7} [get_ports ref_clk0_n] ; ## D5 FMC_HPC0_GBTCLK0_M2C_C_N + +set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[0]] ; ## C6 FMC_HPC0_DP0_M2C_P +set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[0]] ; ## C7 FMC_HPC0_DP0_M2C_N +set_property -dict {PACKAGE_PIN J4} [get_ports rx_data_p[1]] ; ## A2 FMC_HPC0_DP1_M2C_P +set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[1]] ; ## A3 FMC_HPC0_DP1_M2C_N +set_property -dict {PACKAGE_PIN F2} [get_ports rx_data_p[2]] ; ## A6 FMC_HPC0_DP2_M2C_P +set_property -dict {PACKAGE_PIN F1} [get_ports rx_data_n[2]] ; ## A7 FMC_HPC0_DP2_M2C_N +set_property -dict {PACKAGE_PIN K2} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC0_DP3_M2C_P +set_property -dict {PACKAGE_PIN K1} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC0_DP3_M2C_N + +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## H14 FMC_HPC0_LA07_N +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## H7 FMC_HPC0_LA02_P +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D8 FMC_HPC0_LA01_CC_P +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D9 FMC_HPC0_LA01_CC_N +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports spi_sdo] ; ## C26 FMC_HPC0_LA27_P + + +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports pwdn] ; ## H8 FMC_HPC0_LA02_N +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports rstb] ; ## H13 FMC_HPC0_LA07_P +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adc_lvsft_en] ; ## G9 FMC_HPC0_LA03_P + +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H10 FMC_HPC0_LA04_P +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H11 FMC_HPC0_LA04_N + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports sysref_p] ; ## G12 FMC_HPC0_LA08_P +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports sysref_n] ; ## G13 FMC_HPC0_LA08_N + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_1] ; ## H16 FMC_HPC0_LA11_P +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_2] ; ## H17 FMC_HPC0_LA11_N +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_3] ; ## H19 FMC_HPC0_LA15_P +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_4] ; ## H20 FMC_HPC0_LA15_N +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_5] ; ## H22 FMC_HPC0_LA19_P +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_6] ; ## H23 FMC_HPC0_LA19_N +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_7] ; ## H25 FMC_HPC0_LA21_P +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_8] ; ## H26 FMC_HPC0_LA21_N + +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports gpio_sw0 ] ; ## D11 FMC_HPC0_LA05_P +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports gpio_sw1 ] ; ## D12 FMC_HPC0_LA05_N +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports gpio_sw2 ] ; ## D14 FMC_HPC0_LA09_P +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports gpio_sw3_v1] ; ## D15 FMC_HPC0_LA09_N +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports gpio_sw3_v2] ; ## D17 FMC_HPC0_LA13_P +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports gpio_sw4_v1] ; ## D18 FMC_HPC0_LA13_N +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports gpio_sw4_v2] ; ## D20 FMC_HPC0_LA17_P_CC + +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports adl5960x_sync1] ; ## D21 FMC_HPC0_LA17_N_CC + +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports spi_bus0_sck] ; ## G18 FMC_HPC0_LA16_P +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports spi_bus0_sdi] ; ## G15 FMC_HPC0_LA12_P +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports spi_bus0_sdo] ; ## G16 FMC_HPC0_LA12_N +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports clkd_lvsft_en] ; ## G19 FMC_HPC0_LA16_N + +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports spi_bus0_csn_f2] ; ## G21 FMC_HPC0_LA20_P +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports spi_bus0_csn_sen] ; ## G22 FMC_HPC0_LA20_N + +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports spi_bus1_sck] ; ## G27 FMC_HPC0_LA25_P +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports spi_bus1_sdi] ; ## G24 FMC_HPC0_LA22_P +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports spi_bus1_sdo] ; ## G25 FMC_HPC0_LA22_N +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports spi_bus1_csn_dat1] ; ## G28 FMC_HPC0_LA25_N +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports spi_bus1_csn_dat2] ; ## G30 FMC_HPC0_LA29_P + +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_sck] ; ## D23 FMC_HPC0_LA23_P +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_sdio] ; ## D24 FMC_HPC0_LA23_N +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn1] ; ## D26 FMC_HPC0_LA26_P +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn2] ; ## D27 FMC_HPC0_LA26_N +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn3] ; ## C10 FMC_HPC0_LA06_P +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn4] ; ## C11 FMC_HPC0_LA06_N + +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_sck] ; ## C14 FMC_HPC0_LA10_P +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_sdio] ; ## C15 FMC_HPC0_LA10_N +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn5] ; ## C18 FMC_HPC0_LA14_P +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn6] ; ## C19 FMC_HPC0_LA14_N +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn7] ; ## C22 FMC_HPC0_LA18_P_CC +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn8] ; ## C23 FMC_HPC0_LA18_N_CC + +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[0]] ; ## H28 FMC_HPC0_LA24_P +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[1]] ; ## H29 FMC_HPC0_LA24_N +set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[2]] ; ## H31 FMC_HPC0_LA28_P +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[3]] ; ## H32 FMC_HPC0_LA28_N +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[4]] ; ## H34 FMC_HPC0_LA30_P +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[5]] ; ## H35 FMC_HPC0_LA30_N +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[6]] ; ## H37 FMC_HPC0_LA32_P +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[7]] ; ## H38 FMC_HPC0_LA32_N + +# clocks +create_clock -period 2 -name rx_ref_clk [get_ports ref_clk0_p] +create_clock -period 8 -name rx_ref_clk2 [get_ports glblclk_p] + +set_input_delay -clock [get_clocks rx_ref_clk2] [get_property PERIOD [get_clocks rx_ref_clk2]] \ + [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }] + +create_generated_clock -name clk_sck0 \ + -source [get_pins i_system_wrapper/system_i/axi_spi_bus1/ext_spi_clk] \ + -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_bus1/sck_o] + +create_generated_clock -name clk_sck1 \ + -source [get_pins i_system_wrapper/system_i/axi_spi_adl5960_1/ext_spi_clk] \ + -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_adl5960_1/sck_o] + +create_generated_clock -name clk_sck2 \ + -source [get_pins i_system_wrapper/system_i/axi_spi_adl5960_2/ext_spi_clk] \ + -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_adl5960_2/sck_o] diff --git a/projects/ad9083_vna/zcu102/system_project.tcl b/projects/ad9083_vna/zcu102/system_project.tcl new file mode 100644 index 000000000..67b4e1001 --- /dev/null +++ b/projects/ad9083_vna/zcu102/system_project.tcl @@ -0,0 +1,14 @@ + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad9083_vna_zcu102 +adi_project_files ad9083_fmc_zcu102 [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_3w_spi.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run ad9083_vna_zcu102 diff --git a/projects/ad9083_vna/zcu102/system_top.v b/projects/ad9083_vna/zcu102/system_top.v new file mode 100644 index 000000000..c2f5cacb7 --- /dev/null +++ b/projects/ad9083_vna/zcu102/system_top.v @@ -0,0 +1,297 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + input ref_clk0_p, + input ref_clk0_n, + + input glblclk_p, + input glblclk_n, + + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + output rx_sync_p, + output rx_sync_n, + + input sysref_p, + input sysref_n, + + output pwdn, + output rstb, + + output spi_sdio, + input spi_sdo, + output spi_csn_clk, + output spi_csn_adc, + output spi_clk, + output adc_lvsft_en, + output clkd_lvsft_en, + + output spi_bus0_sck, + output spi_bus0_sdi, + input spi_bus0_sdo, + output spi_bus0_csn_f2, + output spi_bus0_csn_sen, + + output spi_bus1_sck, + output spi_bus1_sdi, + input spi_bus1_sdo, + output spi_bus1_csn_dat1, + output spi_bus1_csn_dat2, + + output spi_adl5960_1_sck, + inout spi_adl5960_1_sdio, + output spi_adl5960_1_csn1, + output spi_adl5960_1_csn2, + output spi_adl5960_1_csn3, + output spi_adl5960_1_csn4, + + output spi_adl5960_2_sck, + inout spi_adl5960_2_sdio, + output spi_adl5960_2_csn5, + output spi_adl5960_2_csn6, + output spi_adl5960_2_csn7, + output spi_adl5960_2_csn8, + + output adl5960_temp_1, + output adl5960_temp_2, + output adl5960_temp_3, + output adl5960_temp_4, + output adl5960_temp_5, + output adl5960_temp_6, + output adl5960_temp_7, + output adl5960_temp_8, + + output gpio_sw0, + output gpio_sw1, + output gpio_sw2, + output gpio_sw3_v1, + output gpio_sw3_v2, + output gpio_sw4_v1, + output gpio_sw4_v2, + + output [ 7:0] prten, + + output adl5960x_sync1 +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [20:0] gpio_bd; + wire ref_clk0; + wire rx_sync; + wire sysref; + wire rx_ref_core_clk0_s; + wire rx_ref_core_clk0; + + wire [ 2:0] spi0_csn; + wire spi0_mosi; + wire spi0_miso; + + wire [ 2:0] spi_bus0_csn; + wire [ 1:0] spi_bus1_csn; + + wire [ 3:0] spi_adl5960_1_csn_s; + wire spi_adl5960_1_clk_s; + wire spi_adl5960_1_mosi_s; + wire spi_adl5960_1_miso_s; + + wire [ 3:0] spi_adl5960_2_csn_s; + wire spi_adl5960_2_clk_s; + wire spi_adl5960_2_mosi_s; + wire spi_adl5960_2_miso_s; + wire [ 2:0] pr_check; + + // assignments + + assign spi_csn_adc = spi0_csn[0]; + assign spi_csn_clk = spi0_csn[1]; + + assign spi_bus0_csn_sen = spi_bus0_csn[2]; + assign spi_bus0_csn_f2 = spi_bus0_csn[1]; + + assign spi_bus1_csn_dat1 = spi_bus1_csn[0]; + assign spi_bus1_csn_dat2 = spi_bus1_csn[1]; + + assign spi_adl5960_1_sck = spi_adl5960_1_clk_s; + assign spi_adl5960_1_csn1 = spi_adl5960_1_csn_s[0]; + assign spi_adl5960_1_csn2 = spi_adl5960_1_csn_s[1]; + assign spi_adl5960_1_csn3 = spi_adl5960_1_csn_s[2]; + assign spi_adl5960_1_csn4 = spi_adl5960_1_csn_s[3]; + + assign spi_adl5960_2_sck = spi_adl5960_2_clk_s; + assign spi_adl5960_2_csn5 = spi_adl5960_2_csn_s[0]; + assign spi_adl5960_2_csn6 = spi_adl5960_2_csn_s[1]; + assign spi_adl5960_2_csn7 = spi_adl5960_2_csn_s[2]; + assign spi_adl5960_2_csn8 = spi_adl5960_2_csn_s[3]; + + assign adl5960_temp_8 = gpio_o[48]; + assign adl5960_temp_7 = gpio_o[47]; + assign adl5960_temp_6 = gpio_o[46]; + assign adl5960_temp_5 = gpio_o[45]; + assign adl5960_temp_4 = gpio_o[44]; + assign adl5960_temp_3 = gpio_o[43]; + assign adl5960_temp_2 = gpio_o[42]; + assign adl5960_temp_1 = gpio_o[41]; + assign gpio_sw3_v2 = gpio_o[40]; + assign gpio_sw4_v2 = gpio_o[40]; + assign gpio_sw3_v1 = gpio_o[39]; + assign gpio_sw4_v1 = gpio_o[39]; + assign gpio_sw2 = gpio_o[38]; + assign gpio_sw1 = gpio_o[37]; + assign gpio_sw0 = gpio_o[36]; + assign adl5960x_sync1 = gpio_o[35]; + assign rstb = gpio_o[33]; + assign pwdn = gpio_o[32]; + + assign pr_check = {gpio_o[38],gpio_o[40],gpio_o[39]}; + assign prten = (pr_check == 3'b000) ? 8'd1 : + (pr_check == 3'b001) ? 8'd2 : + (pr_check == 3'b010) ? 8'd4 : 8'd0; + + assign gpio_i[94:32] = gpio_o[94:32]; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; + + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[7:0]; + + // instantiations + + IBUFDS IBUFDS_inst ( + .O(rx_ref_core_clk0_s), + .I(glblclk_p), + .IB(glblclk_n)); + + BUFG BUFG_inst ( + .O(rx_ref_core_clk0), + .I(rx_ref_core_clk0_s)); + + IBUFDS_GTE4 i_ibufds_ref_clk0 ( + .CEB (1'd0), + .I (ref_clk0_p), + .IB (ref_clk0_n), + .O (ref_clk0), + .ODIV2 ()); + + assign adc_lvsft_en = spi_csn_adc; + assign clkd_lvsft_en = spi_csn_clk; + + ad_3w_spi #( + .NUM_OF_SLAVES(4) + ) i_spi_adl5960_1 ( + .spi_csn(spi_adl5960_1_csn_s), + .spi_clk(spi_adl5960_1_clk_s), + .spi_mosi(spi_adl5960_1_mosi_s), + .spi_miso(spi_adl5960_1_miso_s), + .spi_sdio(spi_adl5960_1_sdio), + .spi_dir()); + + ad_3w_spi #( + .NUM_OF_SLAVES(4) + ) i_spi_adl5960_2 ( + .spi_csn(spi_adl5960_2_csn_s), + .spi_clk(spi_adl5960_2_clk_s), + .spi_mosi(spi_adl5960_2_mosi_s), + .spi_miso(spi_adl5960_2_miso_s), + .spi_sdio(spi_adl5960_2_sdio), + .spi_dir()); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (ref_clk0), + .rx_core_clk_0 (rx_ref_core_clk0), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (sysref), + .spi0_sclk (spi_clk), + .spi0_csn (spi0_csn), + .spi0_miso (spi_sdo), + .spi0_mosi (spi_sdio), + .spi1_csn (spi_bus0_csn), + .spi1_miso (spi_bus0_sdo), + .spi1_mosi (spi_bus0_sdi), + .spi1_sclk (spi_bus0_sck), + .spi_bus1_csn_i (spi_bus1_csn), + .spi_bus1_csn_o (spi_bus1_csn), + .spi_bus1_clk_i (spi_bus1_sck), + .spi_bus1_clk_o (spi_bus1_sck), + .spi_bus1_sdo_i (spi_bus1_sdi), + .spi_bus1_sdo_o (spi_bus1_sdi), + .spi_bus1_sdi_i (spi_bus1_sdo), + .spi_adl5960_1_csn_i (spi_adl5960_1_csn_s), + .spi_adl5960_1_csn_o (spi_adl5960_1_csn_s), + .spi_adl5960_1_clk_i (spi_adl5960_1_clk_s), + .spi_adl5960_1_clk_o (spi_adl5960_1_clk_s), + .spi_adl5960_1_sdo_i (spi_adl5960_1_mosi_s), + .spi_adl5960_1_sdo_o (spi_adl5960_1_mosi_s), + .spi_adl5960_1_sdi_i (spi_adl5960_1_miso_s), + .spi_adl5960_2_csn_i (spi_adl5960_2_csn_s), + .spi_adl5960_2_csn_o (spi_adl5960_2_csn_s), + .spi_adl5960_2_clk_i (spi_adl5960_2_clk_s), + .spi_adl5960_2_clk_o (spi_adl5960_2_clk_s), + .spi_adl5960_2_sdo_i (spi_adl5960_2_mosi_s), + .spi_adl5960_2_sdo_o (spi_adl5960_2_mosi_s), + .spi_adl5960_2_sdi_i (spi_adl5960_2_miso_s)); + +endmodule