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util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain

main
Adrian Costina 2015-04-28 14:50:00 +03:00
parent 1eebfd3155
commit 67c581cef8
2 changed files with 16 additions and 4 deletions
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14
library/util_wfifo/util_wfifo.v
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@ -123,6 +123,7 @@ module util_wfifo (
reg adc_wovf = 'd0;
reg dma_wr_int = 'd0;
reg fifo_rst = 'd0;
reg fifo_rst_p = 'd0;
reg fifo_rstn = 'd0;
// internal signals
@ -172,9 +173,16 @@ module util_wfifo (
// reset & resetn
always @(posedge adc_clk) begin
fifo_rst <= adc_rst;
fifo_rstn <= ~adc_rst;
always @(posedge dma_clk or posedge adc_rst) begin
if (adc_rst == 1'b1) begin
fifo_rst_p <= 1'd1;
fifo_rst <= 1'd1;
fifo_rstn <= 1'd0;
end else begin
fifo_rst_p <= 1'b0;
fifo_rst <= fifo_rst_p;
fifo_rstn <= ~fifo_rst_p;
end
end
// axis

6
library/util_wfifo/util_wfifo_constr.xdc
View File

@ -1,5 +1,9 @@
set_property ASYNC_REG TRUE \
[get_cells -hier *adc_wovf_m*]
[get_cells -hier *adc_wovf_m*] \
[get_cells -hier *fifo_rst_p*]
set_false_path \
-to [get_cells -hier adc_wovf_m_reg[0]* -filter {primitive_subgroup == flop}]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*fifo_rst*}]