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motcon2_fmc: Updated design 

- separated clocks for ethernet and other cores in the design
- removed constraints that were not needed
main
Adrian Costina 2015-03-12 16:55:36 +02:00
parent 27afec5f9e
commit 68224f82de
2 changed files with 48 additions and 107 deletions
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21
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
View File

@ -107,9 +107,14 @@
set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT5_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT2_DRIVES {No_buffer} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_DRIVES {No_buffer} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_DRIVES {No_buffer} ] $sys_audio_clkgen
# speed detectors
# speed detector core motor 1
@ -281,7 +286,7 @@
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5]
connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i]
connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i]
connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i]
@ -330,7 +335,7 @@
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5]
connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i]
connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i]
connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i]
@ -375,7 +380,7 @@
# motor 1
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5]
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source
@ -464,7 +469,7 @@
# motor 2
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5]
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source
@ -568,9 +573,9 @@
connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc]
connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w]
connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r]
@ -578,9 +583,9 @@
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1]
connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc]
connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w]

134
projects/motcon2_fmc/zed/system_constr.xdc
View File

@ -48,16 +48,6 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}]
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}]
#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}]
#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}]
#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}]
#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0]
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0]
@ -88,12 +78,12 @@ set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_txc]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}]
# Ethernet 2
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc]
@ -102,20 +92,26 @@ set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}]
#create clocks
# Clock Period Constraints
create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC]
create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc]
create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \
-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q]
create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \
-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q]
set_clock_groups -asynchronous \
-group [get_clocks {pwm_ctrl_1}] \
-group [get_clocks {pwm_ctrl_2}]
create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q]
@ -124,9 +120,6 @@ create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/
create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q]
set_clock_groups -asynchronous \
-group [get_clocks {cm1_ia cm1_ib cm1_vbus }]
create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q]
create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \
@ -134,87 +127,30 @@ create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/
create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q]
set_clock_groups -asynchronous \
-group [get_clocks {cm1_ia cm1_ib cm1_vbus }]
set_clock_groups -asynchronous \
-group [get_clocks {cm2_ia cm2_ib cm2_vbus }]
set_clock_groups -asynchronous \
-group [get_clocks {pwm_ctrl_1 }] \
-group [get_clocks {pwm_ctrl_2 }]
# Ethernet common
set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl]
create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC]
set_clock_groups -logically_exclusive \
-group [get_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \
-group [get_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \
-group [get_clocks {clk_out4_system_sys_audio_clkgen_0_1 }]
set_clock_groups -asynchronous \
-group [get_clocks {mdio_mdc}] \
-group [get_clocks -include_generated_clocks {clk_out1_system_sys_audio_clkgen_0_1 }] \
-group [get_clocks -include_generated_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \
-group [get_clocks -include_generated_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \
-group [get_clocks -include_generated_clocks {clk_out4_system_sys_audio_clkgen_0_1}]
# Ethernet 1
# Clock Period Constraints
create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1]
#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1]
create_clock -name eth1_rx_clk_vir -period 8
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
#IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max 1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -setup
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -setup
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -hold
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -hold
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -setup
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -setup
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -hold
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -hold
set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to [get_clocks rgmii_rx_ctl_clk_s] -setup 0
create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc]
#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1]
#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1]
create_clock -name eth2_rx_clk_vir -period 8
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3]
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
# Ethernet 2
#IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max 1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -0.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -0.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -setup
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -setup
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -hold
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -hold
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}]
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}]
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay